JPH10271006A - Output level adjustment circuit - Google Patents

Abstract

(57) [Summary] [Problem] To adjust an output level accurately by an adjuster simply by inputting a timing signal using a switch or the like, regardless of the level of an input signal and without making an adjustment error. In a device for transmitting an analog signal by PCM, a serial-parallel converter (1) for converting a transmitted PCM signal (S1) into a parallel signal, a reference PCM signal (S2) encoding a desired output level, and the serial A subtracter 2 for subtracting from the output of the parallel converter 1
And a sample-and-hold circuit 3 for storing the output of the subtracter 2 when the timing signal S3 is given, and adding and subtracting the value stored in the sample-and-hold circuit 3 from the output of the serial-parallel converter 1. Adder / subtractor 4
A parallel-serial converter 5 for converting the output of the adder / subtractor 4 into a serial signal; a digital-analog converter 6 for digital-to-analog conversion of the output of the parallel-serial converter 5; And a low-pass filter 7 for removing high-frequency components from the output of the filter 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for adjusting an output level of an analog signal in an apparatus for transmitting an analog signal by pulse code modulation (hereinafter referred to as PCM).

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional circuit. Conventionally, as shown in FIG. 2, a transmitted PCM signal S1 is digital-analog (hereinafter D / A
D / A conversion is performed by a converter 6 and a high-frequency component is removed by a low-pass filter (hereinafter referred to as LPF) 7, and the output level of an analog signal is adjusted by a variable amplifier 8A.

[0003]

In the above-mentioned prior art, when the circuit is the same and the level of the reference input signal is different, the adjustment is manually performed. There is a problem that it varies from individual to individual.

[0004]

SUMMARY OF THE INVENTION The circuit of the present invention solves the problems of the prior art, such as adjustment errors and variations in accuracy, and provides an output level adjustment circuit that allows anyone to easily and accurately adjust the output level. As shown in FIG. 1, in a device for transmitting an analog signal by PCM, a serial-parallel converter 1 for converting a transmitted PCM signal S1 to a parallel signal, and a reference PCM signal S2 for encoding a desired output level. , A subtractor 2 for subtracting from the output of the serial-parallel converter 1, a sample-and-hold circuit 3 for storing the output of the subtractor 2 when a timing signal S3 is given, An adder / subtractor 4 for adding / subtracting the value stored in the sample / hold circuit 3 from the output; and converting the output of the adder / subtractor 4 into a serial signal. Serial converter 5 - parallel to
And a digital-analog converter 6 for digital-to-analog conversion of the output of the parallel-serial converter 5
And a low-pass filter 7 for removing high-frequency components from the output of the digital-analog converter 6.

[0005]

FIG. 1 shows a first embodiment of the circuit of the present invention.
It is a block diagram which shows the structure of an example. In this embodiment, in a device for transmitting an analog signal by PCM, a serial-parallel (hereinafter referred to as S / P) converter 1 for converting a transmitted PCM signal S1 into a parallel signal, and encoding a desired output level The reference PCM signal S2
A subtractor 2 for subtracting from the output of the converter 1, a sample-and-hold (S / H) circuit 3 for storing an output value of the subtractor 2 when a timing signal S3 is given,
An adder / subtractor 4 for adding / subtracting a value stored in the S / H circuit 3 from an output of the P converter 1 and a parallel-serial (hereinafter P / S) for converting an output signal of the adder / subtractor 4 into a serial signal.
), A digital-analog (hereinafter referred to as D / A) converter 6 for digital-to-analog conversion of the output signal of the P / S converter 5, and a high-frequency signal from the output signal of the D / A converter 6. Low-pass filter (hereinafter LP)
F) 7) and an amplifier 8 for amplifying the output signal of the LPF 7.

In the above configuration, the transmitted PCM
The signal S1 is converted into a parallel signal by the S / P converter 1 so that arithmetic processing can be performed. From this signal, a reference PCM signal S2 obtained by encoding a desired output level is subtracted by a subtractor 2.
To subtract. This value is stored by the S / H circuit 3 when the timing signal S3 is input. This timing signal S3 is added / subtracted by the adder / subtractor 4 to add / subtract the signal of the input level serving as a reference for defining the output level to the S / P converter 1 (addition and sampling when the output of the sample hold circuit ≧ the output of the S / P converter). Hold circuit output <S / P
Subtract when the output is a converter). This signal is converted back to a serial signal by the P / S converter 5, converted into an analog signal by the D / A converter 6, and after removing high-frequency components by the LPF 7, amplified by the fixed amplifier 8 and output.

[0007]

As described above, according to the present invention, the adjuster only inputs a timing signal by a switch or the like,
The output level can be adjusted accurately regardless of the level of the input signal and without making adjustment errors. In addition, adjustment costs can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an example of an embodiment of a circuit of the present invention.

FIG. 2 is a block diagram showing a configuration of an example of a conventional circuit.

[Description of Signs] 1 Serial-parallel (S / P) converter 2 Subtractor 3 Sample hold (S / H) circuit 4 Adder-subtractor 5 Parallel-serial (P / S) converter 6 Digital-analog (D / A) ) Converter 7 Low pass filter (LPF) 8 Amplifier 8A Variable amplifier S1 PCM signal S2 Reference PCM signal S3 Timing signal

Claims (1)

[Claims] 1. An apparatus for transmitting an analog signal by PCM, comprising: a serial-parallel converter for converting a transmitted PCM signal into a parallel signal; a reference PCM signal encoding a desired output level; A subtractor for subtracting from the output of the converter, a sample and hold circuit for storing the output of the subtractor when a timing signal is given, and a sample and hold circuit for storing the output of the serial-parallel converter. An adder / subtractor for adding / subtracting a value, a parallel-serial converter for converting an output of the adder / subtractor to a serial signal, a digital-analog converter for digital-to-analog conversion of the output of the parallel-serial converter, and A low-pass filter that removes high-frequency components from the output of an analog converter. An output level adjustment circuit characterized in that: