JPH10276428A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an inexpensive divided image reproducing system, without using any special camera by reading video data from 1st and 2nd storage means synchronously with the synchronizing signal of the camera on one side. SOLUTION: Image information from a television camera A is read from 1st and 2nd frame memories 3 add 4 alternately at timing delayed from recording timing for three fields and 3/4H, and image information from a television camera B is read out of 3rd and 4th frame memories 6 and 7 alternately at timing delayed from the recording timing for three fields and 1/4H and at timing delayed for three fields and 3/4H. Read video signals A3 and B3 are inputted to a D/A converter 10 while being switched at the interval of 1/2H through a switching circuit 9, and converted from digital signals to analog signals. At a synchronizing signal synthesizer circuit 11, vertical and horizontal synchronizing signals VDa and HDa and the analog video signals are synthesized and outputted to a monitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for displaying two images captured by two cameras in almost real time by dividing the screen of one monitor into two.

[0002]

2. Description of the Related Art Reproduced images using a television camera are employed in many systems such as a crime prevention system, a measurement control system, and a traffic monitoring system. In particular, when shooting a relatively fast-moving symmetrical object, or in a system that needs to capture the moment when a certain event occurs, for example, capture the moment when a car collides and record the image on video tape or the like. To analyze the accident occurrence mechanism,
When a golf or baseball swing is recorded to correct a form or the like, it is easier to capture the object from multiple viewpoints, and it is required that images captured from multiple viewpoints be synchronized.

[0003] For image processing in such a system, there is a demand for a reproduction method capable of simultaneously monitoring images obtained by a plurality of cameras on a single monitor and capable of simultaneous monitoring.

[0004] In order to divide two camera images and display them on one monitor, it is necessary to synchronize the two camera image signals. Conventionally, an externally-synchronized camera is used as the camera. Was realized.

For example, FIG. 12 is a block diagram showing a schematic configuration of a conventional image processing apparatus using two such externally synchronized cameras. In FIG. 12, reference numeral 101 denotes a first analog / digital converter (hereinafter referred to as an A / D converter 101) for converting analog image information transmitted from the first television camera 100 into 8-bit digital image information. Abbreviations), 103 denotes the second television camera 10
2 is a second analog / digital converter 103 (hereinafter abbreviated as A / D converter 103) for converting analog image information sent from the second to 8-bit digital image information.

Reference numeral 105 denotes a first line memory made of a semiconductor memory. The first line memory 105 is supplied from the first A / D converter 101 at the timing of the recording control signal from the first timing control circuit 107. The digital image information to be transmitted is recorded, and the first timing control circuit 107
From the recording control signal by the read control signal from
(H is a horizontal scanning period. For example, in the NTSC system, 63.
Reading is performed at a timing delayed by 5 μs), and digital image information from the television camera 100 is output.

Reference numeral 103 denotes a second line memory made of a semiconductor memory. The second line memory 103 is transmitted from the second A / D converter 103 at the timing of the recording control signal of the second timing control circuit 111. The digital image information is recorded and read out at a timing delayed by 1 / 4H from the recording control signal by the read control signal from the second timing control circuit 111, and the digital image information from the television camera 102 is output. .

[0008] The reference numeral 113 designates a first signal at a timing synchronized with image information from the first television camera 100 every 1 / 2H.
Is a switching circuit for switching between digital image information from the line memory 105 and digital image information from the second line memory 109.

Reference numeral 115 denotes a digital / analog converter (hereinafter abbreviated as D / A converter 117) for converting a digital signal from the switching circuit 113 into an analog signal.

Reference numeral 117 denotes an input of the vertical synchronizing signal VD,
This is a synchronizing signal synthesizing circuit that synchronizes an analog signal output from the / A converter 117 with a vertical synchronizing signal VD to generate a synthesized signal and outputs the synthesized signal to a monitor.

The conventional image processing apparatus configured as described above is composed of two television cameras 10 controlled synchronously with each other.
0, 102 to the first and second A
Are converted into digital image information by the / D converters 101 and 103, and are recorded in the first and second line memories 105 and 109, respectively.
In response to the control signals from 07 and 111, the data is read out with a delay of ／ H and ４H from the recording timing, and is switched by the switching circuit 113 at a timing of ＤH to perform D / A.
The signal is input to the converter 115, converted into an analog signal, and the analog signal is synthesized with the vertical synchronizing signal VD by the synchronizing signal synthesizing circuit 117 and output to a monitor (not shown) such as a CRT. In this way, the screen of the monitor can be divided into right and left, and the images captured by the first and second cameras 100 and 102 can be synchronized and simultaneously displayed on one monitor.

[0012]

However, such a conventional image processing apparatus has a problem that the cost is high because an expensive external synchronous camera is required.

[0013] Even when an expensive external synchronous camera is used, there is a phase delay between the left and right divided images displayed on the monitor, and there may be a case where the right and left images are synchronized.

An object of the present invention is to solve the above-mentioned problems, and to provide an image processing apparatus and an image processing apparatus capable of realizing an inexpensive divided image reproducing system without using a special camera including an external synchronous camera. It is intended to provide a method.

Another object of the present invention is to reduce the phase difference between divided images as much as possible to improve the synchronism between the divided images.

[0016]

In order to achieve the above object, an image processing apparatus according to the first aspect of the present invention divides an image shot by two cameras onto a screen of one monitor. In an image processing apparatus for projecting images simultaneously, first storage means for recording one frame of the video signals of the two cameras as reference video data for two frames, and two frames of video signals of the other camera. And a second storage means for synchronizing with the synchronization signal of the one camera,
A synchronizing means for reading out video data from the first and second storage means.

In the image processing apparatus according to a second aspect of the present invention, the first storage means stores the video signal of the one camera in the first signal with respect to the synchronization signal under the control of the synchronization means.
Recording a video signal of the one camera in frame units at a second predetermined timing with respect to the synchronization signal under the control of the synchronization means; A second frame memory for storing the video signal of the other camera in a frame unit at a third predetermined timing with respect to the synchronization signal under the control of the synchronization unit. A third frame memory for recording, and a fourth frame memory for recording the video signal of the other camera in frame units at a fourth predetermined timing with respect to the synchronization signal under the control of the synchronization means. It is provided.

According to a third aspect of the present invention, in the image processing apparatus, the synchronization means synchronizes with the synchronization signal to record and read the video signal of the one camera from the first and second frame memories. A first timing control circuit for controlling timing, and in synchronization with the synchronization signal,
A second timing control circuit for controlling recording timing and reading timing of the video signal of the other camera with respect to the third and fourth frame memories.

According to a fourth aspect of the present invention, in the image processing apparatus, the first timing control circuit delays the timing of reading video data from the first and second frame memories by 3/4 field from the recording timing. Is controlled.

According to a fifth aspect of the present invention, in the image processing apparatus, the first timing control circuit controls the third and fourth frames at the timing of reading video data from the first and second frame memories. This is for reading the video data recorded in the memory.

According to a sixth aspect of the present invention, there is provided an image processing apparatus, wherein the two cameras output analog video signals, and convert the analog video signals of the one camera into digital signals to generate a first video signal. And a first analog / digital converter for outputting to the second frame memory, and a second analog for converting an analog video signal of the other camera into a digital signal and outputting the digital signal to the first and second frame memories. / Digital converter, a switching circuit for switching and outputting video data read from the first to fourth frame memories at a predetermined timing, and a digital for converting a digital output signal from the switching circuit into an analog signal. / Analog converter.

According to a seventh aspect of the present invention, in the image processing apparatus, a vertical synchronizing signal and a horizontal synchronizing signal are separated from an output signal of the one camera and output to the first and second timing control circuits and the switching circuit. And a vertical synchronizing signal and a horizontal synchronizing signal separated by the first synchronizing signal separating circuit.
And a synchronizing signal synthesizing circuit for synthesizing the analog output signal from the analog converter and outputting the synthesized signal to the monitor.

[0023]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a timing chart showing recording timing and reading timing of a frame memory of a first television camera, and FIG. 5 is a timing chart showing recording timing and reading timing of the frame memory on the second television camera side. In FIG. 1, reference numeral 1A denotes a first synchronizing signal separation circuit for separating a vertical synchronizing signal VDa and a horizontal synchronizing signal HDb from an output signal of the first television camera A, and 2A denotes an output of the second television camera B. This is a second synchronization signal separation circuit that separates a vertical synchronization signal VDb and a horizontal synchronization signal HDb from a signal.

1B represents the analog image information A1 included in the output signal transmitted from the first television camera A as 8
A first analog / digital converter (hereinafter abbreviated as A / D converter 1B) that converts the digital image information into bits of digital image information A2;
Reference numeral 2B denotes a second analog / digital converter (hereinafter referred to as an A / D converter 2B) for converting analog image information B1 included in an output signal transmitted from the second telephoto camera B into 8-bit digital image information B2. (Abbreviation).

Reference numeral 3 denotes a first frame memory made of a semiconductor memory. The first frame memory 3 stores the first A / D converter 1B at the timing of the recording control signal T1 from the first timing control circuit 5. The digital image information A2 sent from the first timing control circuit 5 is read, and the read is performed at a timing delayed by three fields in the vertical direction and 3 / 4H in the horizontal direction from the recording control signal T1 by the read control signal T3 from the first timing control circuit 5. Then, half of the digital image information A3 is output.

Reference numeral 4 denotes a second frame memory made of a semiconductor memory. The second frame memory 4 is provided with a first A at a timing T2 which is an inverted logic of the recording control signal T1 of the first timing control circuit 5. The digital image information A2 sent from the / D converter 1B is recorded, and the read control signal T3
The read is performed at the timing of the read control signal T4 which is the inverted logic of the above, and the other half of the digital image information A3 is output.

Reference numeral 5 denotes a first timing control circuit. The first timing control circuit 5 receives the vertical synchronizing signal VDa and the horizontal synchronizing signal HDa from the first synchronizing signal separating circuit 1A, and outputs the timing shown in FIG. As shown in the chart, recording control signals T1 and T2, which are signals for alternately storing data in the first and second frame memories 3 and 4 at timings synchronized with the analog image information A1, are generated. Also, from these recording control signals T1 and T2, 3
At the timing delayed by 3 / 4H in the field and the horizontal direction, read control signals T3 and T4 for alternately reading from the first and second frame memories 3 and 4 are generated.

Reference numeral 6 denotes a third frame memory made of a semiconductor memory. The third frame memory 6 stores the second A / D converter 2B at the timing of the recording control signal T5 from the second timing control circuit 8. The digital image information B2 sent out from the memory is recorded and read at the timing of the read control signal T7 which is 1 / 2H earlier than the timing of the read control signal T3, and outputs half of the digital image information B3.

Numeral 7 denotes a fourth frame memory made of a semiconductor memory. The fourth frame memory 7 operates at the timing of the read control signal T6 which is the inverted logic of the recording control signal T5 of the second timing control circuit 8. The digital image information B2 sent from the second A / D converter 2B is recorded and read out at the timing of the readout control signal T8 which is the inverted logic of the readout control signal T7.
Output the other half of 3.

Reference numeral 8 denotes a second timing control circuit. The second timing control circuit 8 receives the vertical synchronizing signal VDa and the horizontal synchronizing signal HDa from the first synchronizing signal separating circuit 1A, and outputs a second synchronizing signal. The vertical synchronizing signal VDb is input from the signal separation circuit 2A, and is supplied to the third and fourth frame memories 6 and 7 at the timing synchronized with the analog image information B1 as shown in the timing chart of FIG. It generates recording control signals T5 and T6, which are signals for performing recording alternately, and generates the first timing control circuit 5
At a timing 1 / 4H earlier than the read control signals T3 and T4 of the third and fourth frame memories 6 and 7 to generate read control signal signals T7 and T8 for alternately reading.

Reference numeral 9 denotes a switching circuit which receives the horizontal synchronizing signal HDa from the synchronizing signal separating circuit 1A, and switches between digital image information A3 and digital image information B3 every 1 / 2H at a timing synchronized with the image information A1. is there.

Reference numeral 10 denotes a digital / analog converter (hereinafter abbreviated as D / A converter 10) for converting a digital signal output from the switching circuit 9 into an analog signal.

A vertical synchronizing signal VDa and a horizontal synchronizing signal HDa output from the synchronizing signal separating circuit 1A are input to the synchronizing signals VDa, HDa and the D / A converter 1.
This is a synchronizing signal synthesizing circuit that synthesizes an analog output signal of 0 and outputs it to a monitor such as a CRT.

The first and second frame memories 3, 4
Constitutes the first storage means of the present invention, the third and fourth frame memories 6 and 7 constitute the second storage means of the present invention, and the first and second timing control circuits 5 and 8 This constitutes the synchronization means of the present invention.

Next, the working of this embodiment will be described with reference to FIGS.

In the output signal of the first television camera A, the vertical synchronizing signal VDa and the horizontal synchronizing signal HDa contained therein are separated by the first synchronizing signal separating circuit 1A, and the first and second signals are output. The signals are input to the frame memories 3 and 4 and the first timing control circuit 5 and also input to the synchronizing signal synthesizing circuit 11.

Further, after the analog image information A1 included in the output signal of the first television camera A is converted into a digital signal by the first A / D converter 1B, as shown in FIG. 1 is written to the first frame memory 3 at the high level timing of the recording control signal T1 from the timing control circuit 5, and is written to the second frame memory 4 at the high level timing of the inverted signal of the recording control signal T1. It is. The image information is read from the first frame memory 3 at the high level timing of the read control signal T3 from the first timing control circuit 5, and the read control signal T3
The image information is read from the second frame memory 4 at the high-level timing of the inverted signal of. That is, in the illustrated example, the image information from the television camera A includes the first and second images.
Are alternately read from the frame memories 3 and 4 at a timing delayed by 3 fields and 3 / 4H from the recording timing.

On the other hand, in the output signal of the second television camera B, the vertical synchronizing signal VDb and the horizontal synchronizing signal HDb contained therein are separated by the second synchronizing signal separating circuit 1B, and the third and the second signals are output. 4 and is input to a third timing control circuit 8.

Further, after the analog image information B1 included in the output signal of the second television camera B is converted into a digital signal by the second A / D converter 2B, as shown in FIG. 2 is written to the third frame memory 6 at the high level timing of the recording control signal T5 from the second timing control circuit 8, and is written to the fourth frame memory 7 at the high level timing of the inverted signal of the recording control signal T5. It is. The image information is read from the third frame memory 6 at the high level timing of the read control signal T5 from the second timing control circuit 8, and the read control signal T5
The image information is read from the fourth frame memory 7 at the high-level timing of the inverted signal of. That is, in the illustrated example, the image information from the television camera B is the third and fourth image information.
Are alternately read from the frame memories 6 and 7 at a timing delayed by 3 fields and 1 / 4H from the recording timing.
Because of the shift, it is read at a timing further shifted by 1 / 2H, and thus at a timing delayed by 3 fields and 3 / 4H.

The video signal A3 read from the first and second frame memories 3 and 4 and the video signal B3 read from the third and fourth frame memories 6 and 7 are switched by the switching circuit 9 to 1 / 2H, D
The signal is input to the / A converter 10, where it is converted from a digital signal to an analog signal and sent to the synchronizing signal synthesizing circuit 11. In the synchronizing signal synthesizing circuit 11, the synchronizing signal separating circuit 1A
Vertical synchronization signal VDa and horizontal synchronization signal H output from
Da and the analog video signal from the D / A converter 10 are combined and output to a monitor (not shown) such as a CRT. In this manner, on the monitor screen, the image information from the first television camera A and the image information from the second television camera B are synchronously split and displayed on the left and right.

Note that the video signal A3 of the first television camera A is
Is delayed by three fields from the input.
This is to minimize the phase difference with the video signal B3 of the television camera B.

When photographing certain scenes 0 to 10 without delaying the reading of the video signal A3, the video signal A3
And the video signal B3 have a phase difference of 0H, 1 / 4H,
FIGS. 4A to 4D show the cases of 2 / 4H and 3 / 4H, respectively.

The video signal B1 of the second television camera B is
In order to synchronize with the video signal A1, it is necessary to record it once in the image memory (frame memories 6, 7). FIG.
As can be seen from FIG. 4, the phase difference between the video signal B3 and the video signal A3 is a maximum of 4/60 seconds ((b) in FIG. 4).

To improve this, the video signal A1 is delayed by three fields as shown in FIG.
The video signal A1 is recorded in the first and second frame memories 3 and 4 and read at a timing delayed by three fields.
And the maximum phase difference between the two video signals A3 and B3 is 1/6
0 seconds.

FIG. 6 shows the first and second television cameras A,
The video of TV camera A is displayed in real time while the phase of B is the same, and the video of TV camera B is once recorded in frame memories 6 and 7 and then reproduced and recorded in the vertical synchronization signal and the frame memory. The relationship with the timing is shown. In this case, the image of the television camera B is recorded in the frame memories 6 and 2 by two fields, and then synchronized with the vertical synchronization signal VDa of the television camera A (the one recorded in the odd field is the odd field). 2/60 second (2 fields) with respect to the image (real time) of the television camera A because the data is read out every two fields.
Be late.

FIG. 7 shows the first and second television cameras A,
When the phase difference of B is 1/60 second (one field), the image of TV camera A is displayed in real time.
The relationship between the vertical synchronizing signal and the recording and reading timings to and from the frame memory when the video is once recorded in the frame memories 6 and 7 and then reproduced. In this case, the image of the television camera A is displayed in real time, but the image of the television camera B is delayed by two fields (odd and even fields) by one field with respect to the vertical synchronization signal VDa of the television camera A. After being recorded in the frame memory, the vertical synchronization signal VDa
Is read out in the next odd-numbered field in synchronization with.

The first and second television cameras A and B
When the phase difference is within the range of 0 to 1/60 second (one field), the timing of reading the image of the television camera B from the frame memories 6 and 7 does not change. Seconds.

Therefore, when the image of the television camera A is displayed in real time and the image of the television camera B is once recorded in the frame memories 6 and 7 and then reproduced, the time difference between the left and right divided images displayed on the monitor screen is considered. Occurs for a maximum of 4/60 seconds.

Therefore, the image of the television camera A is also temporarily recorded in the frame memories 3 and 4, and the time until the reading is 3/3.
By setting 60 seconds, the time difference between the left and right divided images displayed on the monitor screen can be reduced to 1/60 second. The reason will be described below.

FIG. 8 shows the first and second television cameras A,
When the video of both TV cameras A and B is once recorded in the frame memories 3, 4, 6, and 7 and then reproduced, the vertical synchronization signal and the recording and reading timings to and from the frame memory have the same phase of B. Shows the relationship. In this case, the image of the television camera A is recorded in the frame memories 3 and 4 in two fields at a time, and then 3/60 seconds (3 fields)
The video of the television camera B is read out with a delay, and the video of the television camera A is simultaneously recorded with the frame memories 6 and 7.
Are recorded in two fields at a time, and are read out two fields at a time in synchronization with the vertical synchronization signal VDa of the television camera A (that is, with a delay of 2/60 seconds). For this reason, the image of the television camera A is 1/6 of the image of the television camera B.
It is displayed on the monitor with a delay of 0 seconds (one field).

FIG. 9 shows the first and second television cameras A,
When the phase difference of B is 1/60 second (one field), the images of both television cameras A and B are once stored in the frame memories 3, 4,
6 shows the relationship between the vertical synchronizing signal and the timing of recording and reading to and from the frame memory in the case where the data is reproduced after being recorded in 6, 7. In this case, recording of the video of the TV camera A,
The reading is the same as that of FIG. 8, but the images of the television camera B have two fields (odd field and even field) delayed by one field with respect to the vertical synchronization signal VDa of the television camera A, and the frame memories 6 and 7 are read. Is recorded in the next odd field in synchronization with the vertical synchronization signal VDa of the television camera A.
The data is read out with a delay of 60 seconds (3 fields). Accordingly, the delay of the video camera A video readout timing and the delay of the video camera B video readout timing are equal, and the phase difference between the video of the television camera A and the video of the television camera B projected on the left and right screens of the monitor. Is zero.

Next, with reference to FIG. 11, a description will be given of a method of displaying the screen of the monitor by dividing the screen into right and left.

The data recorded in the frame memories 3, 4, 6 and 7 is transferred to the horizontal synchronization signal HDa of the first television camera A.
By changing the readout timing in synchronization with the above, the video projected on the monitor can be shifted in the horizontal (left / right) direction. For example, in the case of the NTSC system, FIG.
As shown in (1), since the horizontal scanning period is 63.5 μs, data reading from the frame memories 3, 4, 6, and 7 is performed at 31.
By delaying by 75 μs, the image displayed on the monitor can be shifted by half a screen in the horizontal direction.

Therefore, data reading from the frame memories 3 and 4 of the television camera A is performed by 3 / 4H (47.625 μm).
s) The frame memory 6 on the TV camera B side is delayed by
If the reading of data from 7 is delayed by 1 / 4H (15.875 μs), and the images on the left side of FIG. 10 are recorded in the frame memories 3, 4, 6, and 7, respectively, the reproduced image of the television camera A is 11 is shown on the upper left side, and the reproduced image of the television camera B is shown on the upper right side of FIG. Therefore, these two playback images are
By switching at the timing of 1 / 2H, FIG.
The reproduced image is as shown in the lower part of FIG.

As described above, when the images of the two television cameras A and B are reproduced on the left and right sides of the monitor, the images can be reproduced synchronously without using an externally synchronized camera. In the above description of the embodiment, the television cameras that output analog signals are used as the cameras A and B. However, cameras that output digital signals may be used. In this case, the first and second A are used. The / D converters 1B and 2B are omitted, and the digital signals from the cameras A and B are directly input to the frame memories 3, 4, 6, and 7.

[0057]

As described above, according to the present invention, in an image processing apparatus, the use of an external synchronization type camera is not required.
There is an effect that two images captured by two cameras can be divided into two on the left and right sides of one monitor screen and projected almost in real time.

Also, by reading the data with a delay of 3/4 field after recording the data in the memory, the phase difference between the left and right divided images on the monitor can be minimized, and therefore, the movement is relatively fast. This is very effective when photographing an object, or in a system or the like that needs to capture the moment when a certain event occurs, when synchronizing the left and right images is required.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an image processing apparatus according to the present invention.

FIG. 2 is a timing chart showing a relationship between a vertical synchronization signal VDa of a camera A, recording control signals T1 and T2 of a first timing control circuit, and read control signals T3 and T4.

FIG. 3 is a timing chart illustrating a relationship among a vertical synchronization signal VDa of a camera A, a vertical synchronization signal VDb of a camera B, recording control signals T5 and T6, and read control signals T7 and T8 of a second timing control circuit.

FIG. 4 is a diagram showing a state in which the phase difference between the synchronizing signals of the video signal A3 and the video signal B3 is 0H, １ ／ H, 2D without delaying the reading of the video signal A3 when photographing certain scenes 0 to 10;
Recording of image data in each case of ４H, ／ H,
FIG. 6 is a diagram showing a read state.

FIG. 5 shows the recording and reading states of image data and two video signals A3 and B when the reading of the video signal A3 is delayed by three fields when shooting certain scenes 0 to 10.
FIG. 4 is a diagram illustrating a phase difference of No. 3;

FIG. 6 shows that the first and second television cameras A and B have the same phase, display the image of the television camera A in real time, and temporarily store the image of the television camera B in the frame memories 6 and 7;
FIG. 4 is a diagram showing a relationship between a vertical synchronization signal and recording / readout timings to a frame memory and a state of a display image on a monitor when the information is reproduced after recording.

FIG. 7 is a diagram showing the image of the television camera A in real time with the phase difference between the first and second television cameras A and B being 1/60 second (one field), and temporarily storing the image of the television camera B in the frame memory 6; 7 shows the relationship between the vertical synchronizing signal and the recording and reading timings to and from the frame memory and the state of the display image on the monitor when the data is reproduced after being recorded in.

FIG. 8 shows a case where the phases of the first and second television cameras A and B are the same, and the video of both television cameras A and B is once recorded in the frame memory and then reproduced to the vertical synchronization signal and the frame memory. FIG. 4 is a diagram showing a relationship between recording and reading timings of the image and a state of a display image on a monitor.

FIG. 9 shows a case where the phase difference between the first and second television cameras A and B is 1/60 second (one field), and the images of both television cameras A and B are once recorded in the frame memory and then reproduced. FIG. 5 is a diagram showing a relationship between vertical synchronization signals and recording and reading timings to and from a frame memory and a state of a display image on a monitor.

FIG. 10 is a diagram illustrating a state of a display image on a monitor when read timing from a frame memory is shifted by の of a horizontal scanning period (1H).

FIG. 11 is a diagram illustrating a state in which memory playback images of cameras A and B are switched at 1 / 2H and divided and displayed on a monitor.

FIG. 12 is a block diagram illustrating a schematic configuration of a conventional image processing apparatus.

[Explanation of symbols]

Reference Signs List 1 A / D conversion circuit, 2 A / D conversion circuit, 3 first frame memory (first storage unit), 4 second frame memory (first storage unit), 5 first timing circuit (control Means), 6 third frame memory (second storage means), 7 fourth frame memory (second storage means), 8 second timing circuit (control means), 9 switching circuit, 10 digital / analog Converter, 11 synchronizing signal synthesizing circuit, 1A first synchronizing signal separating circuit, 2B
Second synchronization signal separation circuit, A first camera (one camera), B second camera (the other camera).

Claims (7)

[Claims] 1. An image processing apparatus for dividing an image captured by two cameras onto a screen of one monitor and simultaneously displaying the divided images, wherein one of the video signals of the two cameras is used as a reference image. A first storage unit for recording two frames of data as data, a second storage unit for recording a video signal of the other camera for two frames, and the second storage unit in synchronization with a synchronization signal of the one camera. An image processing apparatus comprising: a synchronization unit that reads out video data from the first and second storage units. 2. The first storage means stores a video signal of the one camera in a frame unit at a first predetermined timing with respect to the synchronization signal under the control of the synchronization means. A frame memory, and a second frame memory that records the video signal of the one camera in frame units at a second predetermined timing with respect to the synchronization signal under the control of the synchronization unit. A storage unit configured to record a video signal of the other camera in a frame unit at a third predetermined timing with respect to the synchronization signal under the control of the synchronization unit; And a fourth frame memory for recording the video signal of the other camera in a frame unit at a fourth predetermined timing with respect to the synchronization signal under the control of The image processing apparatus according to claim 1, wherein. 3. A first timing control circuit for controlling a recording timing and a reading timing of a video signal of the one camera with respect to the first and second frame memories in synchronization with the synchronization signal. And a second timing control circuit that controls a recording timing and a reading timing of the video signal of the other camera with respect to the third and fourth frame memories in synchronization with the synchronization signal. The image processing apparatus according to claim 2. 4. The apparatus according to claim 1, wherein the first timing control circuit controls the timing of reading the video data from the first and second frame memories to be delayed by ／ field from the recording timing. 3. The image processing device according to 3. 5. The first timing control circuit reads video data recorded in the third and fourth frame memories at a timing of reading video data from the first and second frame memories. The image processing apparatus according to claim 4, wherein: 6. A camera for outputting an analog video signal, wherein the two cameras convert an analog video signal of the one camera into a digital signal and output the digital signal to first and second frame memories. A first analog / digital converter, a second analog / digital converter that converts an analog video signal of the other camera into a digital signal and outputs the digital signal to first and second frame memories, A switching circuit for switching and outputting video data read from the fourth frame memory at a predetermined timing; and a digital / analog converter for converting a digital output signal from the switching circuit into an analog signal. The image processing device according to claim 2, wherein: 7. A first synchronizing signal separating circuit for separating a vertical synchronizing signal and a horizontal synchronizing signal from an output signal of the one camera and outputting the signals to the first and second timing control circuits and the switching circuit; A synchronizing signal synthesizing circuit which receives the vertical synchronizing signal and the horizontal synchronizing signal separated by the first synchronizing signal separating circuit, synthesizes the same with an analog output signal from the digital / analog converter, and outputs the synthesized signal to a monitor. The image processing apparatus according to claim 2, further comprising: