JPH1027887A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a punch-through hardly occur thereby enhancing the memory preservation characteristics by a method wherein the thickness in a specific range in contact with a silicon substrate out of the filling up material of a contact connecting the diffused layer of a silicon substrate to a lower electrode is formed of single crystalline silicon hardly diffusing any impurities than amorphous silicon. SOLUTION: An element separating region 102 is provided on a P type silicon substrate 101 and then a gate insulating film 100, a gate electrode 104, an n type source diffused layer 105 and a drain diffused layer 106 are formed on an element region 103. Next, an interlayer insulating film 221 is grown on the whole surface of the source diffused layer 105 so as to open a capacity contact 231 wherein single crystalline silicon 301 hardly diffusing impurities than amorphous is halfway grown in the part 50-200nm thick in contact with the silicon substrate 101 so that a lower electrode 411 may be formed on the single crystalline silicon 301 to be connected to the source diffused layer 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a dynamic RAM (Dynamic) having a memory cell having one charge storage capacitor and one charge input / output control MOSFET.
RandomAccess Memory, DR
AM).

[0001]

2. Description of the Related Art FIGS. 12 to 15 illustrate a method of manufacturing a conventional DRAM memory cell. As shown in FIG. 12A, an element isolation region 1202 is provided on a p-type silicon substrate 1201, and a gate electrode 1 is provided on an element region 1203.
204, source diffusion layer 1205 and drain diffusion layer 1
Step 206 is formed. Next, as shown in FIG. 12B, after an interlayer insulating film 1207 is formed on the entire surface, a bit contact 1208 is opened on the drain diffusion layer 1206, and thin polysilicon or amorphous silicon 1209 is formed on the entire surface. To implant phosphorus. Next, as shown in FIG. 12C, thick polysilicon or amorphous silicon 121 is formed.
0 is formed to bury the bit contact 1208, and phosphorus is ion-implanted over the entire surface. This ion implantation is performed to reduce the contact resistance with the silicon substrate. Next, as shown in FIG. 13A, the polysilicon or amorphous silicon 1210 is etched back until the surface of the interlayer insulating film appears, and
8 only in polysilicon or amorphous silicon 1209
And 1210 form an embedded plug structure.
Next, a tungsten silicide film 1311 is formed on the entire surface, and a bit line 1312 is formed by photolithography and etching as shown in FIG.
Next, as shown in FIG. 13C, an interlayer insulating film 1321 is grown on the entire surface, and a capacitor contact 1331 is formed on the source diffusion layer.
Open. Next, as shown in FIG. 14A, thin polysilicon or amorphous silicon 1411 is grown, and phosphorus is ion-implanted over the entire surface. This ion implantation is performed to reduce the contact resistance with the silicon substrate. Next, as shown in FIG. 14B, thick polysilicon or amorphous silicon is grown to bury the capacitor contact 1331, phosphorus is ion-implanted over the entire surface, and etched back until the surface of the interlayer insulating film appears. A plug structure in which polysilicon or amorphous silicon 1411 and 1412 are buried only in the capacitor contact 1331 is formed. Next, as shown in FIG. 15A, phosphorus-doped amorphous silicon is grown on the entire surface, a lower electrode 1511 having a capacity is formed by photolithography and etching, and HSG (Hemi- sphe
The surface area of the lower electrode is increased by forming minute irregularities called “Rical-Grain”. Next, as shown in FIG. 15B, a capacitance insulating film 1521 and an upper electrode 1522 are formed, and a DRAM memory cell is completed.

[0002] Filling materials 1209, 1210, 141 for bit contacts 1208 and capacitance contacts 1331
1,1412 is usually grown by thermally decomposing SiH ₄ or Si ₂ H ₆ by a thermal CVD method. When the thermal decomposition temperature exceeds the transition temperature of about 600 ° C., the filling material of the contact is polysilicon having a grain size of about 30 to 200 nm. If the temperature of the pyrolysis is below the transition temperature,
The filling material is amorphous silicon immediately after growth, but becomes polysilicon having a grain size of about 30 to 300 nm by a heat treatment applied in a subsequent process. Since the diffusion coefficient of the impurity in the polysilicon as the filling material is large, the concentration of the impurity inside the contact becomes almost uniform at the time of completion of the element forming process.

FIG. 20 shows another conventional DR method.
4 illustrates a method of manufacturing an AM memory cell. As shown in FIG. 14C, after opening the capacitor contact 1331, as shown in FIG. 20A, a thick amorphous silicon 2001 containing 1 × 10 ²⁰ cm ⁻³ or more of phosphorus is grown on the entire surface. Next, as shown in FIG. 20B, the lower electrode 20 of the capacitor is formed by photolithography and etching.
02, and the surface area of the lower electrode is increased by forming minute irregularities called HSG by a known technique. In this case as well, the contact filling material 2001 is amorphous silicon immediately after growth, but becomes polysilicon having a grain size of about 30 to 300 nm by a heat treatment applied in a subsequent process.

[0004]

In the above-mentioned DRAM memory cell, a high-concentration dopant is usually added to the lower electrode of the normal capacitor in order to prevent the electrode from being depleted when the voltage is applied to the capacitor and to reduce the capacity. Is doped. The contact holes 1208 and 1331 are filled with polysilicon. Since the diffusion of the dopant in the polysilicon is 100 to 10,000 times faster than in the single crystal silicon, the high concentration dopant contained in the lower electrode 1511 easily diffuses into the silicon substrate through the polysilicon inside the contact, The spread of the n-type source or drain diffusion layer is increased. As a result, MOSFE
There have been problems such as the tendency of punch-through of T, deterioration of element isolation characteristics, and deterioration of retention characteristics of stored information.

As one of the methods for solving this problem, it is conceivable to use a single crystal silicon as a filling material of the contact. JP-A-2-143456 discloses a contact hole 120.
A method has been proposed in which the filling of 8 and the formation of the lower electrode are performed by selective epitaxial growth. According to this method, after opening the contact hole 1331 in FIG. 13, doped single-crystal silicon is epitaxially grown using the source or drain diffusion layer as a seed, and the lower electrode is also formed of epitaxial silicon. Selective epitaxial silicon formation
When the lower electrode has grown to a desired size, it is stopped. It is stated that this eliminates the need for a photolithography step and an etching step for forming the lower electrode.

However, this method has the following problems. First, since the shape of the lower electrode is determined by the lateral growth rate corresponding to the plane orientation of the electrode side surface, the structure of the lower electrode cannot be arbitrarily determined. Second, in order to reduce the resistance of the contact and the lower electrode, it is necessary to increase the impurity concentration of the selectively epitaxially grown silicon. However, this also increases the concentration near the interface with the source or drain. Cannot be sufficiently suppressed. Third, since the lower electrode immediately after the growth is not amorphous, it is impossible to increase the capacitance by HSG formation.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS transistor.
It suppresses the diffusion of dopants from the filling material in the contacts opened on the source and drain of the FET to the silicon substrate, and hardly causes punch-through between the source and drain of the MOSFET and between adjacent elements, thereby improving the memory retention characteristics. An object of the present invention is to provide a good DRAM structure and a manufacturing method thereof. In order to achieve this object, according to the present invention, a capacitor for storing charge and a MOSF for controlling charge
And a memory cell having a structure in which the source of the MOSFET is connected to the storage electrode of the capacitor via a conductor embedded in a contact hole opened in an insulating film. At least MOSFE among the conductors embedded in
It is characterized in that the doping concentration of silicon in the contact portion of T with the source is low on the source side of the MOSFET and high on the storage capacitor side. In addition, the DRAM of the present invention
The filling material of the contact connecting the drain of the OSFET and the wiring is silicon, and its doping concentration is
It is characterized in that it is low on the drain side of the SFET and high on the storage capacitor side. Further, the DRAM of the present invention is characterized in that a portion of the silicon filling the contact with a source or a drain of the MOSFET is made of single crystal silicon. Further, the method of manufacturing a DRAM of the present invention
The storage capacitor is formed as amorphous silicon doped with an impurity.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Next, the present invention will be described with reference to the drawings. 1 to 5 illustrate a method of manufacturing a DRAM cell according to Embodiment 1 of the present invention. As shown in FIG. 1A, an element isolation region 102 is provided on a p-type silicon substrate 101, and a gate insulating film 100, a gate electrode 104 and an n-type source diffusion layer 105 and a drain diffusion layer 106 are formed on an element region 103. To form Next, as shown in FIG. 1B, after an interlayer insulating film 107 is formed on the entire surface, a bit contact 108 is opened on the drain diffusion layer 106, and a thin polysilicon or amorphous silicon 109 is formed on the entire surface. Then, phosphorus of an n-type dopant is ion-implanted. Next, FIG.
As shown in FIG. 3C, a thick polysilicon or amorphous silicon 110 is formed to bury the bit contact 108, and phosphorus is ion-implanted over the entire surface. Next, as shown in FIG.
Is etched back until the surface of the interlayer insulating film appears, thereby forming a plug structure in which polysilicon or amorphous silicon is embedded only in the bit contact 108. Next, a tungsten silicide film 211 is formed on the entire surface, and a bit line 212 is formed by photolithography and etching as shown in FIG. Next, as shown in FIG. 2C, an interlayer insulating film 221 is grown on the entire surface, and a capacitor contact 231 is opened on the source diffusion layer. Next, FIG.
As shown in (a), a single crystal silicon layer 301 containing about 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ^{−3 of} an n-type dopant is formed in a contact hole by selective epitaxial growth using a silicon substrate exposed in an opening as a seed. Grow halfway. Next, as shown in FIG. 3B, an amorphous silicon layer 302 containing at least 1 × 10 ²⁰ cm ⁻³ of an n-type dopant is grown on the entire surface to a thickness of about 400 to 1000 nm. Next, as shown in FIG. 4A, a lower electrode of the capacitor is formed by a photolithography technique and an etching technique, and an HSG (Hemi-spherical-G) is formed by a known method.
The surface area of the lower electrode 411 is increased by forming minute irregularities called “rain”. Next, FIG.
As shown in (b), the capacitance insulating film 421 and the upper electrode 42
2 is completed, and the DRAM memory cell is completed. In addition,
If the surface area of the lower electrode is not increased by HSG, the amorphous silicon 302 may be polycrystalline silicon having a higher growth rate. Also, n to the lower electrode
The doping of the type dopant may be performed by ion implantation or the like after the film formation. Before growing the n-type amorphous silicon 302, amorphous silicon having a thickness of about 5 to 50 nm and an n-type dopant concentration of 5 × 10 ¹⁹ cm ⁻³ or less may be grown. As the n-type dopant, phosphorus or arsenic is used.

In this case, since the filling material of the capacitor contact 231 is single crystal silicon in which the diffusion of the dopant is slower than that of polysilicon, the diffusion of the dopant from the storage capacitor and the contact to the silicon substrate is suppressed. Even if the dopant concentration in the storage electrode portion is increased in order to prevent a reduction in capacitance due to the formation of a semiconductor device, punch-through can be sufficiently prevented, and the retention characteristics of stored information as a DRAM can be improved. Also, since single crystal silicon has a lower resistivity than polysilicon, a sufficiently low contact resistance can be obtained even at a dopant concentration of 1 × 10 ²⁰ cm ⁻³ or less. Furthermore, if the lower electrode of the capacitor is formed of amorphous silicon, H
It is possible to increase the capacity by SG. (Embodiment 2) FIGS. 5 to 8 show a DRA according to Embodiment 2 of the present invention.
4 illustrates a method for manufacturing an M cell. As shown in FIG. 5A, an element isolation region 502 is provided on a p-type silicon 501 substrate, and a gate electrode 504, an n-type source diffusion layer 505 and a drain diffusion layer 506 are provided on the element region 503.
To form Next, as shown in FIG. 5B, after an interlayer insulating film 507 is formed on the entire surface, a bit contact 508 is opened on the drain diffusion layer 506, and a thin polysilicon or amorphous silicon 509 is formed on the entire surface. To implant phosphorus. Next, as shown in FIG. 5C, thick polysilicon or amorphous silicon 510 is formed, the bit contact 508 is buried, and phosphorus is ion-implanted over the entire surface. Next, as shown in FIG. 6A, polysilicon or amorphous silicon 510 is etched back until the surface of the interlayer insulating film appears, and a plug in which polysilicon or amorphous silicon is embedded only in bit contact 508 is formed. Form the structure. Next, a tungsten silicide film 611 is formed on the entire surface, and a bit line 612 is formed by photolithography and etching as shown in FIG. Next, as shown in FIG. 6C, an interlayer insulating film 621 is grown on the entire surface, and a capacitor contact 631 is opened on the source diffusion layer. Next, as shown in FIG. 7A, an n-type dopant is added to the silicon substrate exposed at the opening by selective epitaxial growth at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²⁰ c.
50 to 100 n of a single crystal silicon layer 711 containing about m ⁻³
m, and then a single-crystal silicon layer 7 containing at least 1 × 10 ²⁰ cm ^{−3 of an} n-type dopant.
12 is selectively epitaxially grown. Next, FIG.
As shown in, the entire surface n-type dopant 1 × 10 ²⁰ cm
400 to 1000 n of amorphous silicon 721 containing ^-3 or more
It grows to a thickness of about m. Next, as shown in FIG. 8A, after the shape of the lower electrode is determined by a photolithography technique and an etching technique, HSG (He
The lower electrode 811 whose surface area is increased by forming minute irregularities called “mi-spherical-grain” is formed. Next, as shown in FIG. 8B, a capacitance insulating film 821 and an upper electrode 822 are formed,
The AM memory cell is completed. If the surface area of the lower electrode is not increased by HSG, the amorphous silicon 721 may be polycrystalline silicon having a higher growth rate. The doping of the n-type dopant into the lower electrode may be performed by ion implantation or the like after the film formation.

In this case, the filling material of the capacitor contact 631 is a single crystal silicon having a dopant diffusion slower than that of polysilicon, and the dopant concentration is 1 × 10 ²⁰ c.
On the single crystal silicon layer 711 of m ⁻³ or less, a dopant concentration of 1 × 1 is used instead of polysilicon or amorphous silicon.
Since it has a two-layer structure in which a single-crystal silicon layer 712 having a low resistance of 0 ²⁰ cm ⁻³ or more is stacked, it is possible to suppress punch-through and improve the holding characteristics as a DRAM as in the first embodiment. In addition, the contact resistance can be further reduced than in the case of the first embodiment. (Embodiment 3) FIGS. 9 to 11 show DR according to Embodiment 3 of the present invention.
4 illustrates a method of manufacturing an AM cell. FIG. 9 (a)
As shown in FIG. 7, an element isolation region 902 is provided on a p-type silicon substrate 901 and a gate electrode 904 is formed on an element region 903.
And n-type source diffusion layer 905 and drain diffusion layer 90
6 is formed. Next, as shown in FIG. 9B, after an interlayer insulating film 907 is formed on the entire surface, a bit contact 908 is opened on the drain diffusion layer 906, and selective epitaxial growth is performed by using a silicon substrate exposed in the opening as a seed. , An n-type dopant in an amount of 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³
Is grown to a thickness of about 50 to 100 nm, and then a single-crystal silicon layer 912 containing an n-type dopant of 1 × 10 ²⁰ cm ⁻³ or more is grown until the bit contact 908 is almost buried. ,
Thereafter, a tungsten silicide film 913 is formed on the entire surface. Next, as shown in FIG. 9C, a bit line 931 is formed by photolithography and etching. Next, as shown in FIG.
011 is grown on the entire surface, a capacitor contact 1012 is opened on the source diffusion layer, and an n-type dopant is added to the opening at about 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ^-3 by selective epitaxial growth using a silicon substrate as a seed. A single-crystal silicon layer 1013 containing silicon is grown to a thickness of about 50 to 100 nm, and then an n-type dopant is further added to 1 × 10 ²⁰ cm ^−3.
The single crystal silicon layer 1014 including the above
Selective epitaxial growth until 012 is almost buried, and then 400-1000 nm of amorphous silicon 1015 containing 1 × 10 ²⁰ cm ⁻³ or more of n-type dopant on the entire surface.
It grows to a thickness of the order. Next, as shown in FIG. 10B, after the shape of the lower electrode is determined by a photolithography technique and an etching technique, the HSG is formed by a known method.
The lower electrode 1021 whose surface area is increased by forming minute irregularities called (hemi-spherical-grain) is formed. Next, as shown in FIG. 11, a capacitor insulating film 1101 and an upper electrode 1102 are formed, and a DRAM memory cell is completed. Note that if HS
In the case where the surface area of the lower electrode is not increased by changing to G,
The amorphous silicon 1015 may be polycrystalline silicon having a higher growth rate. The doping of the n-type dopant into the lower electrode may be performed by ion implantation or the like after the film formation.

In this case, since the filling material of not only the capacity contact 1012 but also the bit contact 908 is made of single crystal silicon, the diffusion from the bit contact to the substrate can be suppressed, and the punch-through suppressing effect is larger than in the first and second embodiments. Is obtained. (Embodiment 4) FIGS. 16 to 19 show D according to Embodiment 4 of the present invention.
4 illustrates a method of manufacturing a RAM cell. FIG.
As shown in (a), an element isolation region 1602 is provided on a p-type silicon substrate 1601, and a gate electrode 1604 and an n-type source diffusion layer 1605 and a drain diffusion layer 1606 are formed on the element region 1603. Next, as shown in FIG. 16B, after an interlayer insulating film 1607 is formed on the entire surface,
A bit contact 1608 is formed on the drain diffusion layer 1606.
Through which polysilicon or amorphous silicon 1609 having an n-type dopant concentration of 1 × 10 ²⁰ cm ⁻³ or less is
It is formed to a thickness of 100 nm. Next, as shown in FIG. 16C, thick polysilicon or amorphous silicon 1610 having an n-type dopant concentration of 1 × 10 ²⁰ cm ⁻³ or more is formed, and the bit contact 1608 is buried. Next, polysilicon or amorphous silicon 1610 is etched back until the surface of the interlayer insulating film appears, and bit contact 160
8 only in polysilicon or amorphous silicon 1609
Then, a plug structure in which the plug structure 1610 is embedded is formed, and then a tungsten silicide film 1711 is formed on the entire surface as shown in FIG. Next, as shown in FIG. 17B, a bit line 1712 is formed by photolithography and etching. Next, as shown in FIG. 17C, an interlayer insulating film 1721 is grown on the entire surface, and a capacitor contact 1731 is opened on the source diffusion layer 1605. Next, as shown in FIG. 18A, polysilicon or amorphous silicon 1811 having an n-type dopant concentration of 1 × 10 ²⁰ cm ⁻³ or less is formed to a thickness of ²⁰ to 100 nm. Next, as shown in FIG. 18B, a thick polysilicon or amorphous silicon 1812 having an n-type dopant concentration of 1 × 10 ²⁰ cm ⁻³ or more is formed, and a capacitor contact 173 is formed.
1 and then etched back until an interlayer insulating film appears to form a plug structure in which polysilicon or amorphous silicon 1811 and 1812 are embedded only in the capacitor contact 1731. Next, 400 to 1 amorphous silicon containing an n-type dopant of 1 × 10 ²⁰ cm ⁻³ or more over the entire surface.
After growing to a thickness of about 000 nm and defining the lower electrode shape by photolithography technology and etching technology,
HSG (Hemi-Spherica) is obtained by a known method.
The lower electrode 1911 whose surface area is increased by forming minute unevenness called “l-Grain” is formed. Next, as shown in FIG.
1 and an upper electrode 1922 are formed, and a DRAM memory cell is completed. If the surface area of the lower electrode is not increased by HSG, the amorphous silicon 1911 may be polycrystalline silicon having a higher growth rate. The doping of the n-type dopant into the lower electrode may be performed by ion implantation or the like after the film formation.

In this case, low-doped polysilicon or amorphous silicon and highly-doped polysilicon or amorphous silicon are used as filling materials for the capacity contact 1731 and the bit contact 1608 without using selective epitaxial silicon. A contact can be formed only by a conventional CVD apparatus without a special apparatus for obtaining a high vacuum. Further, diffusion of the dopant into the substrate can be suppressed by controlling the heat treatment time after the contact is formed.

[0013]

According to the first embodiment of the present invention, of the filling material of the contact connecting the diffusion layer of the silicon substrate and the lower electrode, the portion having a thickness of 50 to 200 nm in contact with the silicon substrate is made of polysilicon or amorphous. It is made of single-crystal silicon, in which impurities are less likely to diffuse than porous silicon, so that it is possible to prevent the dopant in the highly doped amorphous silicon from diffusing to the silicon substrate and deepening the source diffusion layer. It is possible to improve punch-through and storage information retention characteristics. Further, since the doping concentration in the single-crystal silicon is 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ , which is almost the same as that of the source or drain diffusion layer, the diffusion of the dopant from the single-crystal silicon to the silicon substrate is performed. Does not occur. Furthermore, since the resistivity of the single crystal silicon portion is sufficiently low even at the above-mentioned doping concentration unlike polycrystalline silicon conventionally used as a filling material, the contact resistance can be set to a desired low value. it can. Further, since the storage electrode is grown as amorphous silicon, the capacity can be increased by HSG. Further, according to the second embodiment of the present invention, since the filling material above the contact is made of highly doped single crystal silicon, the contact resistance can be further reduced as compared with the case where polycrystalline silicon is used. According to the third embodiment of the present invention, the filling material of the bit contact in addition to the capacitance contact is 1 ×.
Since single crystal silicon containing a dopant of 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ is used, not only the source diffusion layer but also the drain diffusion layer can be suppressed from being deepened, so that punch-through can be more effectively prevented. it can. According to the fourth embodiment of the present invention, the selective epitaxial silicon is not used for the filling material of the capacitor contact and the bit contact,
By using low-doped polysilicon or amorphous silicon and highly-doped polysilicon or amorphous silicon,
A contact can be formed only by a conventional CVD device without a special device of a high vacuum.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a DRAM memory cell according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the second embodiment of the present invention.

FIG. 6 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the second embodiment of the present invention.

FIG. 7 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the second embodiment of the present invention.

FIG. 8 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the second embodiment of the present invention.

FIG. 9 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the third embodiment of the present invention.

FIG. 10 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the third embodiment of the present invention.

FIG. 11 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the third embodiment of the present invention.

FIG. 12 is a diagram illustrating a manufacturing process of a conventional DRAM memory cell.

FIG. 13 is a diagram illustrating a manufacturing process of a conventional DRAM memory cell.

FIG. 14 is a diagram illustrating a manufacturing process of a conventional DRAM memory cell.

FIG. 15 is a diagram illustrating a manufacturing process of a conventional DRAM memory cell.

FIG. 16 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the fourth embodiment of the present invention.

FIG. 17 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the fourth embodiment of the present invention.

FIG. 18 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the fourth embodiment of the present invention.

FIG. 19 is a diagram illustrating a manufacturing process of the DRAM memory cell according to the fourth embodiment of the present invention.

FIG. 20 is a diagram illustrating a manufacturing process of a conventional DRAM memory cell.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 gate insulating film 101 silicon substrate 102 element isolation oxide film 103 element region 104 gate electrode 105 source diffusion layer 106 drain diffusion layer 107 interlayer insulation film 108 bit contact 109, 110 polysilicon or amorphous silicon 211 tungsten silicide film 212 wiring silicide 221 Interlayer insulating film 231 Capacitance contact 301 Single crystal silicon 302 Amorphous silicon 411 Lower electrode 421 Capacitive insulating film 422 Amorphous silicon or polysilicon 500 Gate insulating film 501 Silicon substrate 502 Element isolation oxide film 503 Element region 504 Gate electrode 505 Source diffusion layer 506 Drain diffusion layer 507 Interlayer insulating film 508 Bit contact 509, 510 Polysilicon or amorphous silicon 611 Tungsten Silicide film 612 Wiring silicide 621 Interlayer insulating film 631 Capacitive contact 711, 712 Monocrystalline silicon 721 Amorphous silicon 811 Lower storage electrode 821 Capacitive insulating film 822 Amorphous silicon or polysilicon 900 Gate insulating film 901 Silicon substrate 902 Element isolation oxidation Film 903 element region 904 gate electrode 905 source diffusion layer 906 drain diffusion layer 907 interlayer insulating film 908 bit contact 911,912 single crystal silicon 913 tungsten silicide film 931 wiring silicide 1011 interlayer insulating film 1012 capacitance contact 1013,1014 single crystal silicon 1015 non Amorphous silicon 1021 Lower storage electrode 1101 Capacitive insulating film 1102 Amorphous silicon or polysilicon 1200 Gate insulating film 1201 Silicon substrate 1202 Device isolation oxide film 1203 Device region 1204 Gate electrode 1205 Source diffusion layer 1206 Drain diffusion layer 1207 Interlayer insulation film 1208 Bit contact 1209, 1210 Polysilicon or amorphous silicon 1311 Tungsten silicide film 1312 Wiring silicide 1321 Interlayer insulation film 1331 Capacitance contacts 1411, 1412 Amorphous silicon or polysilicon 1511 Lower storage electrode 1521 Capacitive insulating film 1522 Amorphous silicon or polysilicon 1600 Gate insulating film 1601 Silicon substrate 1602 Device isolation oxide film 1603 Device region 1604 Gate electrode 1605 Source diffusion layer 1606 Drain diffusion layer 1607 Interlayer insulating film 1608 Bit contact 1609, 1610 Polysilicon Or amorphous silicon 1711 tungsten silicide film 1712 wiring silicide 1721 interlayer insulating film 1731 capacity contact 1811, 1812 amorphous silicon or polysilicon 1911 lower storage electrode 1921 capacity insulating film 1922 amorphous silicon or polysilicon 2001 capacity contact 2002 Storage electrode

Claims (6)

[Claims] 1. A filling material of a contact connecting a silicon substrate and an upper structure formed on the silicon substrate via an insulating film is a single crystal silicon in which at least a contact portion with the silicon substrate is doped with impurities. Wherein the upper structure is made of amorphous silicon. 2. A contact filling material for connecting a silicon substrate and an upper structure formed on the silicon substrate via an insulating film is silicon, and an impurity concentration doped in silicon in the contact is: A semiconductor device, which is lower on the silicon substrate side than on the upper structure side. 3. A contact connecting a silicon substrate and an upper structure formed on the silicon substrate via an insulating film is made of an amorphous material having a dopant concentration of 1 × 10 ²⁰ cm ⁻³ or less and a thickness of 100 nm or less. A semiconductor device characterized in that silicon and polysilicon and amorphous silicon or polysilicon having a dopant concentration of 1 × 10 ²⁰ cm ⁻³ or more are sequentially stacked and filled. 4. A capacitor for accumulating electric charge and a MOSFET for charge input / output control, wherein a source of the MOSFET is connected to a storage electrode of the capacitor and a conductor in a contact opened to an insulating film. 4. A dynamic RAM having connected memory cells, wherein the contact has a structure according to claim 1. 5. A dynamic memory having a memory cell having a capacitor portion for accumulating charges and a MOSFET for charge input / output control, wherein a drain of the MOSFET is connected to a wiring via a conductor in a contact. 4. A dynamic RAM according to claim 1, wherein said contacts have a structure according to claim 1. 6. The method of manufacturing a dynamic RAM according to claim 4, wherein the electrode of the capacitor is formed as amorphous silicon doped with an impurity.