JPH10285190A - Signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To smoothly transmit data by executing mediation so that one processing is preceded when the reception of transmission data and the reception of data transmitted through a serial interface bus are simultaneously executed. SOLUTION: A storage information signal S106 by a transmission preprocessing circuit 106, a read control signal S107 by a transmission post processing circuit 107, a storage information signal S108 by a reception preprocessing circuit 108 and a read control signal S109 by a reception postprocessing circuit are inputted to a FIFO access mediation circuit 112. It is assumed that timing when the circuit 106 or the circuit 107 and the circuit 108 or the circuit 109 are simultaneously accessed. In such a case, a mediation circuit 112 mediates a system so that the access processing of the circuit 108 or the circuit 109 is preceded to the access processing of the circuit 106 or the circuit 107. Thus, the reception processing precedes the transmission processing and data are precisely outputted at a specified time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit used for a serial interface.

[0002]

2. Description of the Related Art In recent years, as an interface for multimedia data transfer, the IEEE (The Institute of Elect) has realized high-speed data transfer and real-time transfer.
ricaland Electronic Engineers) 1394, High
Performance Serial Bus has been standardized.

The data transfer of the IEEE 1394 serial interface includes a conventional request of request and acknowledge, a conventional asynchronous transfer for confirming reception, and an isochronous transfer in which data is always transmitted from a certain node once every 125 μs. is there.

As described above, an I having two transfer modes
The data in the EEE1394 serial interface is
Transfer is performed in packet units.

FIG. 6 is a diagram showing the byte size of one source packet in isochronous communication. FIG.
FIG. 6A shows the packet size in DVB (Digital Video Broadcast) specification, and FIG. 6B shows the packet size in DSS (Digital Satelite System) specification.

[0006] The source packet size in the DVB specification is
As shown in FIG. 6A, it is 192 bytes of a 4-byte source packet header (SPH; Source Packet Header) and 188 bytes of data.

[0007] On the other hand, the source packet size in the DSS specification is, as shown in FIG. 6B, a 4-byte source packet header (SPH), 10-byte additional data, and 144-byte 130-byte data. Bytes. Additional bytes are inserted between the source packet header and the data. In the IEEE 1394 standard, the minimum data unit handled is one quadlet (=
(4 bytes = 32 bits), it is necessary that the total of the transport stream data and the additional data be set in a 32-bit unit. However, it is set without additional bytes by default.

FIG. 7 shows original data when data is transmitted by isochronous communication of the IEEE 1394 standard,
FIG. 6 is a diagram illustrating an example of a correspondence relationship with a packet to be actually transmitted.

As shown in FIG. 7, a source packet which is original data is divided into a predetermined number of data blocks after adding a 4-byte source packet header and padding data for adjusting the data length. Is done. Since the unit of data when transferring a packet is one quadlet (4 bytes), the byte lengths of data blocks and various headers are all set to multiples of four.

FIG. 8 is a diagram showing a format of a source packet header. As shown in FIG. 8, 25 bits of the source packet header include, for example, the D
M used in digital satellite broadcasting such as VB system
PEG (Moving Picture Experts Group)-TS (Transpo
(rt Stream) Time stamp used to suppress jitter when transmitting data by isochronous communication
(TimeStamp) is written.

Then, such a packet header or CI
Data such as P (Common Isochronous Packet) header
A packet is generated by being added to a predetermined number of data blocks.

FIG. 9 is a diagram showing a basic configuration example of an isochronous communication packet. As shown in FIG. 9, the packet of the isochronous communication has a first quadlet of 1394.
Header (Header), the second quadlet is the header CRC (Hea
der-CRC), the third quadlet is CIP header 1 (CIP-He
ader1), the fourth quadlet is CIP header 2 (CIP-Head
er2), the fifth quadlet is the source packet header (SP
In H), the data area is the sixth and subsequent quadlets. The last quadlet is a data CRC (Data-CRC).

The 1394 header has a data-l representing a data length.
ength, the number of the channel to which this packet is transferred (0
63), the transfer speed (10
Speed indicating 0 Mbps, 200 Mbps or 400 Mbps) (or tcod indicating processing code)
e) and a synchronization code sy defined by each application. The header CRC is an error detection code of the packet header.

The CIP header 1 includes an SID (Source node ID) area for a transmission node number, a DBS (Data Block Size) area for a data block length, and an FN (FN) for a data division number in packetization. Fraction Number)
QPC for the number of quadlets in area and padding data
(Quadlet Padding Count) area, SPH area for a flag indicating the presence or absence of a source packet header, and DBC (Da) for a counter for detecting the number of isochronous packets.
ta Block Continuty Counter) area. Note that the DBS area indicates the number of quadlets transferred in one isochronous packet.

The CIP header 2 has an FMT area for a signal format indicating the type of data to be transferred, and an FDF (Format) used corresponding to the signal format.
Dependent Field) area.

The SPH header has a time stamp area in which a value obtained by adding a fixed delay value to the axis on which the transport stream packet has arrived is set. The data CRC is an error detection code of the data field.

The signal processing circuit of the IEEE 1394 serial interface for transmitting and receiving packets having the above-described configuration is mainly composed of a physical layer circuit for directly driving the IEEE 1394 serial bus, and a link for controlling data transfer of the physical layer circuit.
And a layer circuit.

[0018]

By the way, the above-mentioned I
The signal processing circuit of the EEE1394 serial interface is an application-side MPEG transporter.
(Transporter) and access on the serial interface bus side are arbitrarily performed. In the signal processing circuit of the IEEE 1394 serial interface, transmission data and reception data are temporarily stored in a storage device such as a first-in first-out (FIFO) memory (hereinafter simply referred to as a FIFO). Is shared on the side. Therefore, it is necessary to provide a circuit for arbitrating transmission processing for transmitting data to the serial interface bus and reception processing for outputting received data to the application side, but since this arbitration circuit has not been provided yet, smooth data transfer is possible. It may not be possible.

The present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible to arbitrate both processes accurately when a request for a transmission process and a request for a reception process occur at the same time, thereby achieving a smooth data transfer. It is to provide a signal processing circuit that can be realized.

[0020]

In order to achieve the above object, a signal processing circuit according to the present invention comprises: a transmission circuit for receiving transmission data from an application side and transmitting the transmission data to a serial interface bus in a predetermined time cycle; A receiving circuit that receives the data transmitted through the serial interface bus and outputs the data to the application side; and a process of the transmitting circuit when reception of transmission data and reception of data transmitted through the serial interface bus are performed simultaneously. And an arbitration circuit that causes one of the processes of the receiving circuit to be performed in advance.

Further, the signal processing circuit of the present invention further comprises storage means, wherein the transmission circuit stores the received transmission data in a predetermined format in the storage means, and reads out the stored data from the storage means. The received data is transmitted to the serial interface bus, the receiving circuit restores the received data and stores the data in the storage means, reads out the stored data at a predetermined timing, and outputs the read data to the application side. The access circuit arbitrates access to the storage means.

Further, the signal processing circuit of the present invention further has a measuring means for measuring time, and the transmission circuit should output the transmission data received from the application side and the reception data to the application side on the reception side. Time information is added and stored in the storage means, the receiving circuit extracts the time information from the packet data transmitted through the serial interface bus, and the time measured by the measuring means is larger than the time information value. Then, the received data is read from the storage means and output to the application side.

In the signal processing circuit of the present invention, the arbitration circuit precedes the processing of the reception circuit.

According to the signal processing circuit of the present invention, in the transmission circuit, the transmission data is transmitted from the application side to the serial interface bus in a predetermined time cycle. The data transmitted through the serial interface bus is received by the receiving circuit. If the reception of the transmission data and the reception of the data transmitted through the serial interface bus are performed at the same time,
In the arbitration circuit, arbitration is performed such that one of the processing of the transmission circuit and the processing of the reception circuit, for example, the processing of the reception circuit is performed in advance.

According to the present invention, in the transmission circuit, the received transmission data is stored in the storage means in a predetermined format, and the stored data is read out from the storage means and transmitted to the serial interface bus. . In the receiving circuit, the received data is restored and stored in the storage means, and the stored data is read out at a predetermined timing and output to the application side. Then, in the arbitration circuit, access to the storage means of the transmission circuit and the reception circuit is arbitrated.

Further, according to the present invention, in the transmission circuit, the transmission data received from the application side is added with time information for the reception side to output the reception data to the application side and stored in the storage means. In the receiving circuit, the time information is extracted from the packet data transmitted through the serial interface bus, and when the time value measured by the measuring means is larger than the time information value, the received data is read from the storage means. Output to application.

[0027]

FIG. 1 is a block diagram showing an embodiment of an MPEG signal processing circuit according to the present invention applied to an IEEE 1394 serial interface.

This signal processing circuit comprises a link layer circuit 10, a physical layer circuit 20, and a CPU 30 as a host computer. Also, 4
0 indicates an MPEG transporter.

Under the control of the CPU 30, the link layer circuit 10 controls asynchronous transfer and isochronous transfer, and controls the physical layer circuit 20. Specifically, as shown in FIG. 1, the link core (L
ink Core) 101, host interface circuit (Host I)
/ F) 102, application interface circuit (AP
I / F) 103, an asynchronous communication FIFO 104 including a transmission FIFO (AT-FIFO) 104a, a reception FIFO (AR-FIFO) 104b, and a self-ID resolver (Resol).
ver) 105, transmission preprocessing circuit for isochronous communication (TXO
PRE) 106, transmission post-processing circuit for isochronous communication (TXO
PRO) 107, isochronous communication reception preprocessing circuit (TXI
PRE) 108, isochronous communication post-processing circuit (TXI
PRO) 109, FIFO (I-FIFO) 1 for isochronous communication
10. Configuration register (Configuratio
n Register (hereinafter referred to as CFR) 111 and FIF
An O access arbitration circuit 112 is provided.

In the circuit shown in FIG. 1, a host interface circuit 102, a transmission FIFO 104a, a reception FIFO 104b for asynchronous communication, and a link core 101
Constitutes an asynchronous communication system circuit. The application interface circuit 103, the pre-transmission processing circuit 106, the post-transmission processing circuit 107, the pre-reception processing circuit 108, the post-reception processing circuit 109, the FIFO 110, and the link core 101 constitute an isochronous communication system circuit.

The link core 101 includes a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets, an interface circuit for these packets with the physical layer circuit 20 that directly drives the IEEE 1394 serial bus BS, and is reset every 125 μs. It comprises a cycle timer, a cycle monitor and a CRC circuit. Then, time data such as a cycle timer is supplied to the isochronous communication processing circuit through the CFR 111.

The host interface circuit 102 mainly includes a CPU 30 as a host computer and a transmission F
Arbitration of writing and reading of asynchronous communication packets with the FIFO 104a and the receiving FIFO 104b,
Also, arbitration of transmission and reception of various data between the CPU 30 and the CFR 111 is performed. For example, the CPU 30 sets the time stamp delay time Txdelay set in the SPH (source packet header) of the isochronous communication packet in the CFR 111 through the host interface 102.

The transmission FIFO 104a has IEEE1
The asynchronous communication packet transmitted by the 394 serial bus BS is stored, and the asynchronous communication packet transmitted by the IEEE 1394 serial bus BS is stored in the reception FIFO 104b.

Application interface circuit 10
Reference numeral 3 arbitrates the transmission and reception of MPEG transport stream data including a clock signal, a control signal, and the like between the MPEG transporter 40 and the pre-transmission circuit 106 for isochronous communication and the post-processing circuit 109 for isochronous communication.

The resolver 105 analyzes the self ID packet transmitted through the IEEE 1394 serial bus BS and stores the packet in the CFR 111.

The transmission pre-processing circuit 106 receives the MPEG transport stream data from the MPEG transporter 40 via the application interface circuit 103 and adjusts the data length in quadlets (4 bytes) for isochronous communication according to the IEEE 1394 standard. And the delay time Txde set in the CFR 111
The time stamp value is set using lay, and a 4-byte source packet header (SPH) is added to the FIFO1
10 and outputs a storage information signal S 106 such as a so-called FIFO write pointer to the post-transmission processing circuit 107 and the FIFO access arbitration circuit 112.

When a source packet header is added, a time stamp for determining the data output time on the receiving side is set. This setting is performed as follows. First, the value of the internal cycle register is latched at the timing when the final data of the packet is received from the MPEG transporter 40. Next, the delay time Txdelay set in the CFR 111 from the CPU 30 via the host interface 102 is added to the value of the cycle register. Then, the added value is inserted into the source packet header of the received packet as a time stamp (setting).
I do.

FIG. 2 is a diagram for explaining a specific configuration of the time stamp. As shown in FIG. 2, the time stamp for determining the data output time on the receiving side is 2
The current time is represented by 5 bits. That is, the time stamp is composed of 25 bits, the lower 12 bits are allocated as a cycle offset CO (cycle-offset) area, and the upper 13 bits are allocated as a cycle count CC (cycle-count) area. The cycle offset is 0-3071 (12b
(111111111111) is counted (clock CLK = 24.576 MHz), and the cycle count is 0 to 7999 (13b 111110011).
1111) is counted for one second. Therefore, in principle, the lower 12 bits of the time stamp are 3
072 or more, and the upper 13 bits are 800
It does not indicate 0 or more.

The post-transmission processing circuit 107 receives the storage information signal S106 from the pre-transmission processing circuit 106, and
The data including the source packet header stored in the H.110 is read, and as shown in FIG.
Headers 1 and 2 are added and output to the transmission circuit of the link core 101, and a read information signal S 107 indicating a read pointer or the like of the FIFO 110 is output to the FIFO access arbitration circuit 112.

The reception pre-processing circuit 108 includes the link core 10
1 receives an isochronous communication packet transmitted on the IEEE 1394 serial bus BS via the IEEE 1394, analyzes the contents of the 1394 header, CIP headers 1, 2 and the like of the received packet, restores the data, and extracts the source packet header and data. Stored in the FIFO 110 and the FIFO
A storage information signal S108 indicating that data has been written to 110 is output to the post-reception processing circuit 109 and the FIFO access arbitration circuit 112 every time a packet is written.

The post-reception processing circuit 109 includes an internal register 1091 and a comparison circuit 109, as shown in FIG.
2 and a data read control circuit 1093.
Then, the storage information signal S1 by the reception pre-processing circuit 108
08, the FIFO 11 is stored in the internal register 1091.
The time data of the time stamp of the source packet header stored in 0 is read, and the read time stamp data (TS) is compared with the cycle time (CT) of the cycle timer in the link core 101, and the cycle time CT is set to the time stamp. If it is larger than data TS, it outputs data read instruction pulse signal S1092 to data read control circuit 1093. The comparison circuit 10
The specific comparison operation of 92 will be described later. When receiving the pulse signal S1092, the data read control circuit 1093 outputs a data read signal S1093,
And reads out the data excluding the source packet header stored in 0.
, As MPEG transport stream data to the MPEG transporter 40,
A read information signal S109 indicating a read pointer or the like of the FIFO 110 is output to the FIFO access arbitration circuit 112.

The FIFO access arbitration circuit 112 includes a storage information signal S106 by the pre-transmission processing circuit 106, a read control signal S107 by the post-transmission processing circuit 107, a storage information signal S108 by the pre-reception processing circuit 108, and a read by the post-reception processing circuit 109. In response to the control signal S109, when a timing occurs in which the pre-transmission processing 106 or the post-transmission processing circuit 107 and the pre-reception processing 108 or the post-reception processing circuit 109 simultaneously access the FIFO 110, the pre-reception processing 108 or the post-reception processing is performed. FIFO1 of circuit 109
The arbitration signal S1 that arbitrates the access process to the S.10 so that the access process is performed prior to the access process to the FIFO 110 of the pre-transmission processing 106 or the post-transmission processing circuit 107
12 is output to the selector 1113.

A specific example will be described with reference to the timing chart of FIG. At the timing shown in FIG.
The stored information signal S106 by the pre-transmission processing circuit 106 or the read control signal S107 by the post-transmission processing circuit 107
Since only the active signal is active and the stored information signal S108 by the pre-reception processing circuit 108 or the read control signal S1094 by the post-reception processing circuit 109 is inactive, the FIFO 110 is accessed as a transmission process without arbitration.

At the timing shown in FIG. 4, the stored information signal S106 by the pre-transmission processing circuit 106, the read control signal S107 by the post-transmission processing circuit 107 and the stored information signal S108 by the pre-reception processing circuit 108, or the post-reception processing circuit 109 Are both active, the FIFO1 of the transmission process and the reception process
Since the ten access operations will collide, arbitration is required. In this case, as shown in FIG. 4B, the storage information signal S106 by the pre-transmission processing circuit 106 or the read control signal S107 by the post-transmission processing circuit 107 is set to 1
Arbitration is performed such that the cycle (one clock) is delayed and the FIFO 110 is accessed as transmission processing at the timing indicated by.

Also at the timing shown in FIG. 4, the stored information signal S 10
6, or the read control signal S by the post-transmission processing circuit 107
107 and the storage information signal S1 by the reception pre-processing circuit 108
08 or the read control signal S109 by the post-reception processing circuit 109 is active, so that the access operation of the FIFO 110 in the transmission processing and the reception processing will collide, and therefore arbitration is necessary. In this case, as shown in FIG. 4B, the stored information signal S
Arbitration is performed such that the read control signal S107 by the post-transmission processing circuit 107 is delayed by two cycles (two clocks), and the FIFO 110 is accessed as transmission processing at the timing shown by.

Next, the IEEE 1394 serial bus BS
The transmission and reception operation of the asynchronous communication packet transmitted through the communication device will be described. Note that the operation of the post-reception processing circuit 109 is mainly based on a specific comparison operation of the comparison circuit 1092.
This will be described with reference to the flowchart of FIG.

When transmitting an isochronous communication packet to the IEEE 1394 serial bus BS, the CPU 30 transmits the isochronous communication packet SP, for example.
The time stamp delay time Txdelay set in H (source packet header) is set in the CFR 111 through the host interface 102.

Then, in the transmission pre-processing circuit 106, the MPE
Upon receiving the MPEG transport stream data by the G transporter 40, the data length is adjusted in quadlets (4 bytes) for isochronous communication according to the IEEE 1394 standard. At this time, the latch circuit 106
The value of the time stamp is set using the delay time Txdelay latched at 1, and a 4-byte source packet header (SPH) is added and stored in the FIFO 110. Then, a storage information signal S 106 such as a FIFO write pointer is output to the post-transmission processing circuit 107 and the FIFO access arbitration circuit 112.

The post-transmission processing circuit 107 receives the storage information signal S106 from the FIFO access control circuit 1062 of the pre-transmission processing circuit 106, and applies 13 bits to the data including the source packet header stored in the FIFO 110.
A 94 header and CIP headers 1 and 2 are added and output to the transmission circuit of the link core 101, and transmitted as an isochronous communication packet to the IEEE 1394 serial bus BS via the physical layer circuit 20.

The isochronous communication packet transmitted on the IEEE 1394 serial bus BS is input to the reception pre-processing circuit 108 via the link core 101.
The pre-reception processing circuit 108 analyzes the contents of the received packet such as the 1394 header, CIP headers 1 and 2, and restores the data.
Written to 110. The storage information signal S1 indicating that data has been written to the FIFO 110
08 is output to the post-reception processing circuit 109 and the FIFO access arbitration circuit 112 every time a packet is written.

In the post-reception processing circuit 109, as shown in FIG. 5, upon receiving the signal S108, the time stamp is read from the FIFO 110 to the internal register 1091, and the cycle time (CT) at that time is read.
[25], that is, the second digit of the current time is stored in the internal register 1
091 (S1).

Then, the comparison circuit 1092 compares the time stamp data TS read into the internal register 1091 with the cycle time (CT) of the cycle timer in the link core 101, that is, the current time CT (S2). . At this time, the time TS of the time stamp
It is checked whether or not is sandwiching the position of 0 seconds. This is because simple magnitude comparison cannot be performed if 0 seconds is interposed.

If it is determined in step S2 that TS is smaller than CT, it is determined in step S3 that the time obtained by subtracting the time TS indicated by the time stamp from the current time CT is equal to or greater than the value obtained by subtracting 64 from 8000. It is determined whether or not it is. That is, it is checked whether or not the current time CT is actually passing while the TS waits for 0 seconds. The cycle time is composed of 25 bits, and the upper 13 bits are used for the cycle count (cyc
le-count) area, lower 12 bits cycle offset
(cycle-offset) area. On the transmitting side, the timestamp cycle count is the delay value tx
The delay is added only up to 63 bits. The cycle count of the cycle time loops from 0 to 7999. Therefore, if a positive determination result is obtained in step S3, it is determined that the time stamp is valid and the cycle time has not passed, and the process proceeds to step S4. If a negative determination result is obtained in step S3, it is determined that the cycle time has passed the time indicated by the time stamp, and the process proceeds to step S8.

In step S4, CT> TS and 0
A simple comparison with CT cannot be made since the user waits for TS between seconds. Here, the second digit CT [25] of the current time read into the register in step S1 is the current CT.
[25] Wait until it does not match (Refsec). If they do not match, it is determined that the seconds digits of TS and CT are the same (the TS cannot wait for more than one second).

If the condition of step S4 is satisfied, it is determined in step S5 whether or not TS ≦ CT (simple comparison is performed). Then, when TS ≦ CT, reading of the packet (data) from the FIFO 110 is started.

On the other hand, in step S2, TS
When it is determined that the value is greater than the value (TS> CT), a simple comparison can be performed. First, in step S6, a check is performed to determine whether the TS is valid. Specifically, since TS is a value obtained by adding a maximum of 63 to CT, the time obtained by subtracting the current time CT from the time TS indicated by the time stamp should be smaller than 64.
Is determined. When a negative determination result is obtained, the process proceeds to step S8,
Since T has already passed TS, FI
A packet is read from the FO 110 and output.

If a positive determination result is obtained in step S6, the process waits for a TS because the TS is valid. Here, TS is valid and the second digit is CT [25].
Although there is no discrepancy, it is determined in step S7 whether or not there is a discrepancy. If the discrepancy does occur, the packet is forcibly read from the FIFO 110 and output.

In the above-mentioned post-reception processing circuit 109, FI
When accessing the FO 110, the read information signal S
109 is output to the FIFO access arbitration circuit 112.

In the above-described transmission processing for transmitting data to the serial interface bus and reception processing for outputting received data to the application side, the FIFO access arbitration circuit 112 receives the stored information signal S106 from the transmission preprocessing circuit 106, A read control signal S107 from the processing circuit 107, a stored information signal S108 from the pre-reception processing circuit 108, and a read control signal S109 from the post-reception processing circuit 109 are input. When a timing occurs in which the pre-transmission processing 106 or the post-transmission processing circuit 107 and the pre-reception processing 108 or the post-reception processing circuit 109 simultaneously access the FIFO 110, the access processing of the pre-reception processing 108 or the post-reception processing circuit 109 is performed. Are arbitrated by the arbitration signal S112 so as to be performed prior to the access processing of the pre-transmission processing 106 or the post-transmission processing circuit 107. Thereby, the receiving process is performed prior to the transmitting process.

As described above, according to the present embodiment, in the transmission processing for transmitting data to the serial interface bus and the reception processing for outputting received data to the application side, the timing of simultaneous access to the FIFO 110 occurs. Has a FIFO access arbitration circuit 112 that performs arbitration so that the reception processing is performed prior to the transmission processing, so that when the transmission processing request and the reception processing request occur at the same time, the two processing can be arbitrated accurately. There is an advantage that smooth data transfer can be realized.

In this embodiment, the data TS of the time stamp added to the received packet is compared with the cycle time CT by the internal cycle counter, and if the cycle time CT is larger than the time stamp data TS (CT > TS), the received data stored in the FIFO 110 is output.
Asynchronous communication packets transmitted through the 94 serial bus BS can be reliably output to the MPEG transporter 40 (application) at a specified time.

[0062]

As described above, according to the present invention,
When a request for a transmission process and a request for a reception process occur simultaneously, both processes can be arbitrated accurately and smooth data transfer can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an MPEG signal processing circuit according to the present invention applied to an IEEE 1394 serial interface.

FIG. 2 is a diagram illustrating a specific configuration of a time stamp.

FIG. 3 is a block diagram illustrating a configuration example of a time stamp processing circuit of the isochronous communication system reception processing circuit according to the present invention.

FIG. 4 is a timing chart for explaining the operation of the FIFO access arbitration circuit according to the present invention.

FIG. 5 is a diagram for explaining the operation of the isochronous communication system reception processing circuit according to the present invention.

6A and 6B are diagrams showing the byte size of one source packet in isochronous communication, wherein FIG. 6A is a diagram showing a packet size under DVB specifications, and FIG. 6B is a diagram showing a packet size under DSS specifications.

FIG. 7 is a diagram illustrating an example of a correspondence relationship between original data and data to be actually transmitted when data is transmitted by isochronous communication of the IEEE1394 standard.

FIG. 8 is a diagram showing a format of a source packet header.

FIG. 9 is a diagram illustrating a basic configuration example of an isochronous communication packet.

[Explanation of symbols]

10: link layer circuit, 101: link core, 10
2 Host interface circuit 103 Application interface circuit 104 FIFO for asynchronous communication 104a Transmission FIFO (AT-FIFO), 1
04b: FIFO for reception (AR-FIFO), 105: Self-I
Resolver for D, 106: transmission preprocessing circuit for isochronous communication, 107: transmission postprocessing circuit for isochronous communication, 108: reception preprocessing circuit for isochronous communication, 109: reception postprocessing circuit for isochronous communication,
1091: internal register, 1092: comparison circuit, 109
3: Data read control circuit 110: FIFO (I-FIFO) for isochronous communication, 111: Configuration register, 112: FIFO access arbitration circuit, 20: Physical layer circuit, 30: CPU, 40: MPEG
Transporter.

Claims (6)

[Claims] A transmission circuit for receiving transmission data from an application side and transmitting the transmission data to a serial interface bus in a predetermined time cycle; and a reception circuit for receiving data transmitted through the serial interface bus and outputting the data to the application side. Circuit, when the reception of the transmission data and the reception of the data transmitted through the serial interface bus are performed simultaneously, the processing of one of the processing of the transmission circuit and the processing of the reception circuit is performed first. A signal processing circuit having an arbitration circuit for performing the arbitration. 2. A transmission circuit, wherein the transmission circuit stores received transmission data in a predetermined format in the storage unit, reads out the stored data from the storage unit, and sends the data to the serial interface bus. The receiving circuit restores the received data and stores it in the storage means, reads out the stored data at a predetermined timing, and outputs the read data to the application side, and the arbitration circuit accesses the storage means of the transmission circuit and the reception circuit to the storage means. 2. The signal processing circuit according to claim 1, wherein the signal processing circuit arbitrates. 3. The transmitting circuit includes a measuring unit for measuring time, wherein the transmitting circuit adds, to the transmitting data received from the application side, time information for outputting the received data to the application side on the receiving side. The reception circuit extracts the time information from the packet data transmitted through the serial interface bus,
3. The signal processing circuit according to claim 2, further comprising: when the time value measured by said measuring means is larger than the time information value, reading the received data from said storage means and outputting it to said application side. 4. The signal processing circuit according to claim 1, wherein said arbitration circuit precedes processing of said reception circuit. 5. The signal processing circuit according to claim 2, wherein the arbitration circuit precedes the processing of the reception circuit. 6. The signal processing circuit according to claim 3, wherein the arbitration circuit precedes the processing of the reception circuit.