JPH10285241A - Signal processing circuit - Google Patents

Abstract

(57) Abstract: A signal processing circuit capable of inserting a control packet into a normal transport stream and transmitting the same. A control packet FIFO (104c) is provided as a storage device of an asynchronous communication system, control data is arbitrarily set from a CPU (30), and under control of the CPU (30).
The pre-transmission processing circuit 106 and the post-transmission processing circuit 107 are configured to insert control packets between normal MPEG transport streams. As a result, a control packet can be arbitrarily transmitted as an isochronous packet in addition to a packet composed of a normal transport stream.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit used for a digital serial interface.

[0002]

2. Description of the Related Art In recent years, as an interface for multimedia data transfer, the IEEE (The Institute of Ele) has realized high-speed data transfer and real-time transfer.
ctrical and Electronic Engineers) 1394, Hig
hPerformanceSerial Bus has been standardized.

The data transfer of the IEEE 1394 serial interface includes a conventional request of request and acknowledge, a conventional asynchronous transfer for confirming reception, and an isochronous transfer in which data is always transmitted from a certain node once every 125 μs. is there.

As described above, an I having two transfer modes
The data in the EEE1394 serial interface is
Transfer is performed in packet units.

FIG. 3 is a diagram showing the byte size of one source packet in isochronous communication. FIG.
FIG. 3A shows the packet size under DVB (Digital Video Broadcast) specifications, and FIG. 3B shows the packet size under DSS (Digital Satelite System) specifications.

[0006] The source packet size in the DVB specification is
As shown in FIG. 3A, it is 192 bytes of a 4-byte source packet header (SPH; Source Packet Header) and 188 bytes of data.

On the other hand, the source packet size in the DSS specification is, as shown in FIG. 3B, 144 bytes of a 4-byte source packet header (SPH), 10-byte additional data, and 130-byte data. Bytes. Additional bytes are inserted between the source packet header and the data. In the IEEE 1394 standard, the minimum data unit handled is one quadlet (=
(4 bytes = 32 bits), it is necessary that the total of the transport stream data and the additional data be set in a 32-bit unit. However, it is set without additional bytes by default.

FIG. 4 shows original data when data is transmitted by isochronous communication of the IEEE 1394 standard,
FIG. 6 is a diagram illustrating an example of a correspondence relationship with a packet to be actually transmitted.

As shown in FIG. 4, a source packet which is original data is divided into a predetermined number of data blocks after adding a 4-byte source packet header and padding data for adjusting a data length. Is done. Since the unit of data when transferring a packet is one quadlet (4 bytes), the byte lengths of data blocks and various headers are all set to multiples of four.

FIG. 5 is a diagram showing a format of a source packet header. As shown in FIG. 5, 25 bits of the source packet header include, for example, the D
M used in digital satellite broadcasting such as VB system
PEG (Moving Picture Experts Group)-TS (Transpo
(rt Stream) Time stamp used to suppress jitter when transmitting data by isochronous communication
(TimeStamp) is written.

Then, such a packet header or CI
Data such as P (Common Isochronous Packet) header
A packet is generated by being added to a predetermined number of data blocks.

FIG. 6 is a diagram showing a basic configuration example of an isochronous communication packet. As shown in FIG. 6, the packet of the isochronous communication has a first quadlet of 1394.
Header (Header), the second quadlet is the header CRC (Hea
der-CRC), the third quadlet is CIP header 1 (CIP-He
ader1), the fourth quadlet is CIP header 2 (CIP-Head
er2), the fifth quadlet is the source packet header (SP
In H), the data area is the sixth and subsequent quadlets. The last quadlet is a data CRC (Data-CRC).

The 1394 header has a data-l representing a data length.
engt, the number of the channel to which this packet is transferred (0-6)
3), channel indicating processing, and tc indicating processing code
ode and a synchronization code sy defined by each application. The header CRC is an error detection code of the packet header.

The CIP header 1 includes an SID (Source node ID) area for a transmission node number, a DBS (Data Block Size) area for a data block length, and an FN (FN) for a data division number in packetization. Fraction Number)
QPC for the number of quadlets in area and padding data
(Quadlet Padding Count) area, SPH area for a flag indicating the presence or absence of a source packet header, and DBC (Da) for a counter for detecting the number of isochronous packets.
ta Block Continuty Counter) area. Note that the DBS area indicates the number of quadlets transferred in one isochronous packet.

The CIP header 2 has an FMT area for a signal format indicating the type of data to be transferred, and an FDF (Format) used corresponding to the signal format.
Dependent Field) area.

The SPH header has a time stamp area in which a value obtained by adding a fixed delay value to the axis on which the transport stream packet has arrived is set. The data CRC is an error detection code of the data field.

The signal processing circuit of the IEEE 1394 serial interface for transmitting and receiving packets having the above-described configuration is mainly composed of a physical layer circuit for directly driving the IEEE 1394 serial bus, and a link for controlling data transfer of the physical layer circuit.
And a layer circuit.

[0018]

SUMMARY OF THE INVENTION The above-mentioned IEEE13
In the isochronous communication system of the 94 serial interface, for example, as shown in FIG. 7, a link layer circuit 2 is connected to a side MPEG transporter (Transporter) 1 which is an application, and the link layer circuit 2 includes a physical layer circuit 3. Connected to the serial interface bus BS. IEEE 1394
In the data transfer of the serial interface, the transmission data and the reception data are temporarily stored in a storage device such as a FIFO (First-In First-Out) memory (hereinafter simply referred to as FIFO) provided in the link layer circuit 2. Actually, the asynchronous packet FIFO and the isochronous packet FIFO are provided separately.

By the way, as shown in FIG.
A control packet (hereinafter, insert packet; Insert P) between transport stream data TSD of EG
acket) Sometimes it is necessary to insert data. For example, a PAT (Program Allocation Table) for streaming an MPEG transport stream is written, and it is necessary to assign what to this channel of this transporter or to select and stream a channel.

However, in the current signal processing circuit of the IEEE 1394 serial interface, the configuration for arbitrarily transmitting the control insert packet between the MPEG source packets as an isochronous packet has not yet been realized.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a signal processing circuit capable of inserting a control packet into a normal transport stream and transmitting the signal.

[0022]

According to the present invention, there is provided a signal processing circuit for receiving transmission stream packet data from an application side and transmitting the transmission stream packet data to a serial interface bus in a predetermined time cycle. And control means for generating control data, inserting the control data between the transmission stream packets as a control packet, and transmitting the control data as a transmission stream packet to the serial interface bus.

Also, the present invention is a signal processing circuit for receiving transmission stream packet data from an application side and transmitting the transmission stream packet data to a serial interface bus in a predetermined time cycle, comprising: a first storage means;
When it is necessary to transmit control data, the control data is written into the first storage means,
Control means for setting control data indicating that control data is to be transmitted, and a source for setting data indicating that control data is not to be transmitted to the received transmission stream packet data if the control data is not set A packet header is added and stored in a predetermined format in the second storage means. If the control data is set, a source packet header in which data indicating that a control packet is to be transmitted is generated. When the first transmission circuit stored in the second storage means and the data indicating that control data is not transmitted are set in the source packet header stored in the second storage means, Sending the data stored in the second storage means as a transmission stream packet to the serial interface bus, When data indicating that control data is to be transmitted is set in the source packet header stored in the storage means, the control data stored in the first storage means is transmitted to the serial interface bus as a control packet. And a second transmitting circuit.

According to the signal processing circuit of the present invention, during transmission of a transmission stream packet from the application side,
When it becomes necessary to transmit control data, control data is generated by the transmission control means, and the control data is inserted as a control packet between transmission stream packets and transmitted to the serial interface bus as a transmission stream packet. .

According to the present invention, when it becomes necessary to transmit control data during transmission of a transmission stream packet from the application, the control data is written into the first storage means by the control means. In addition, control data indicating that the control data is to be transmitted is set. Here, when the control data is not set, a source packet header in which data indicating that control data is not transmitted is added to the transmission stream packet data by the first transmission circuit, and the transmission packet data is transmitted in a predetermined format. It is stored in the second storage means. In the second transmission processing circuit, since data indicating that control data is not to be transmitted is set in the source packet header stored in the second storage means, the data is stored in the second storage means. The data is transmitted to the serial interface bus as a transmission stream packet. On the other hand, when the control data is set, data indicating that the control packet is to be transmitted is set by the first transmission circuit, and a source packet header is generated and stored in the second storage means. In the second transmission circuit, since data indicating that control data is to be transmitted is set in the source packet header stored in the second storage means, the control data stored in the first storage means is stored. The data is sent out as a control packet to the serial interface bus.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing an embodiment of an MPEG signal processing circuit according to the present invention applied to an IEEE 1394 serial interface.

This signal processing circuit comprises a link layer circuit 10, a physical layer circuit 20, and a CPU 30 as a host computer. Also, 4
0 indicates an MPEG transporter.

The link layer circuit 10 controls the asynchronous transfer and the isochronous transfer under the control of the CPU 30, and controls the physical layer circuit 20. Specifically, as shown in FIG. 1, the link core (L
ink Core)) 101, host interface circuit (Host I
/ F) 102, application interface circuit (AP
I / F) 103, a transmission FIFO (AT-FIFO) 104a, a reception FIFO (AR-FIFO) 104b, an insert packet FIFO (INS-FIFO) 104c comprising an asynchronous communication and control packet FIFO 104, and a self-I.
D resolver 105, transmission preprocessing circuit for isochronous communication (TXOPRE) 106, transmission post-processing circuit for isochronous communication (TXOPRO) 107, reception preprocessing circuit for isochronous communication (TXIPRE) 108, reception preprocessing for isochronous communication It comprises a circuit (TXIPRO) 109, a FIFO (I-FIFO) 110 for isochronous communication, and a configuration register (CFR).

In the circuit shown in FIG. 1, a host interface circuit 102, a transmission FIFO 104a, a reception FIFO 104b for asynchronous communication, and a link core 101
Constitutes an asynchronous communication system circuit. The application interface circuit 103, the pre-transmission processing circuit 106, the post-transmission processing circuit 107, the pre-reception processing circuit 108, the pre-reception processing circuit 109, the FIFO 110, and the link core 101 constitute an isochronous communication system circuit.

The link core 101 includes a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets, an interface circuit for the packets with the physical layer circuit 20 that directly drives the IEEE1394 serial bus BS, and is reset every 125 μs. It comprises a cycle timer, a cycle monitor and a CRC circuit. Then, time data such as a cycle timer is supplied to the isochronous communication processing circuit through the CFR 111.

The host interface circuit 102 mainly includes a CPU 30 as a host computer and a transmission F
Arbitration of writing and reading of asynchronous communication packets with the FIFO 104a and the receiving FIFO 104b,
Arbitration of writing of the insert packet between the CPU 30 and the FIFO for insert packet 104c, and CP
Arbitration of transmission and reception of various data between the U30 and the CFR 111 is performed. For example, the CPU 30 sets the time stamp delay time Txdelay set in the SPH (source packet header) of the isochronous communication packet in the CFR 111 through the host interface 102.
When it becomes necessary for the CPU 30 to insert a control packet or insert packet data during the normal MPEG transport stream data TSD, the logic “1” is set in the register IPTxGo of the CFR 111.

The transmission FIFO 104a has IEEE1
The asynchronous communication packet transmitted by the 394 serial bus BS is stored, and the asynchronous communication packet transmitted by the IEEE 1394 serial bus BS is stored in the reception FIFO 104b.

Control packet data is written from the CPU 30 to the insert packet FIFO 104c. The capacity of the FIFO 104c is, for example, 188 bytes, and data up to 188 bytes is valid, and data exceeding this capacity is not transmitted. If the data to be transmitted is 188 bytes or less, data other than the written data is set to "1" and transmitted. The insert packet FIFO 104c has a width of, for example, 33 bits, and its MSB is set to "1" in the final quadlet. When the MSB outputs data of 1 and further receives a read pulse signal INS-RD from the post-transmission processing circuit 107 described later, “0xFF
FFFFFF (all bits 1) "is output. The data once written is retained after transmission, and when transmitting the same data continuously, after confirming that the above-mentioned register IPTxGo has become “0”, this register IPTxGo is set to “1”. This is done by setting.

Application interface circuit 10
Reference numeral 3 arbitrates the transmission and reception of MPEG transport stream data including a clock signal, a control signal, and the like between the MPEG transporter 40 and the transmission preprocessing circuit 106 for isochronous communication and the reception preprocessing circuit 109 for isochronous communication.

The resolver 105 analyzes the self ID packet transmitted through the IEEE 1394 serial bus BS and stores the packet in the CFR 111.

The pre-transmission processing circuit 106 checks the setting of the register IPTxGo of the CFR 111, and performs different processing depending on whether the setting is "0" or "1". When the setting of the register IPTxGo is “0”, the MPEG transport stream data is received by the MPEG transporter 40 via the application interface circuit 103, and the data length in quadlets (4 bytes) is used for isochronous communication according to the IEEE 1394 standard. And a time stamp value is set using the delay time Txdelay set in the CFR 111, and a 4-byte source packet header (SPH) is added to the FI
It is stored in the FO 110.

When a source packet header is added, a time stamp for determining the data output time on the receiving side is set. This setting is performed as follows. First, the value of the internal cycle register is latched at the timing when the final data of the packet is received from the MPEG transporter 40. Next, the delay time Txdelay set in the CFR 111 from the CPU 30 via the host interface 102 is added to the value of the cycle register. Then, the added value is inserted into the source packet header of the received packet as a time stamp (setting).
I do.

FIG. 2 is a diagram for explaining a specific configuration of the time stamp. As shown in FIG. 2, the time stamp for determining the data output time on the receiving side is 2
The current time is represented by 5 bits. That is, the time stamp is composed of 25 bits, the lower 12 bits are allocated as a cycle offset CO (cycle-offset) area, and the upper 13 bits are allocated as a cycle count CC (cycle-count) area. The cycle offset is 0-3071 (12b
(111111111111) is counted (clock CLK = 24.576 MHz), and the cycle count is 0 to 7999 (13b 111110011).
1111) is counted for one second. Therefore, in principle, the lower 12 bits of the time stamp are 3
072 or more, and the upper 13 bits are 800
It does not indicate 0 or more.

Further, the transmission pre-processing circuit 106 has a CFR1
When the setting of the register IPTxGo of No. 11 is “1”, for example, a source packet header is generated at the fall of the packet gap (Packet Gap) and written to the FIFO 110. At this time, as shown in FIG. 2, 29 bits designated for the insert packet mark IPM are set to "1".
To indicate that the source packet header written in the FIFO 110 is for an insert packet. Note that the IPM bit 29 is always held at “0” when a normal source packet header is generated when the setting of the register IPTxGo is “0”. Then, move the FIFO write pointer to the beginning of the next packet. The amount S of shifting the pointer is given by the following equation, where the packet size is PS.

[0040]

S = (PS-4) / 4 (quadlet)

For example, the amount S of moving the pointer is DV
In the case of the B system, it is 47 in 188/4, and in the case of the DSS system, it is 35 in 140/4. After that, register IPTxG
The source packet header for the insert packet is not generated until the setting of o returns to “0”.

The post-transmission processing circuit 107 includes a FIFO 110
Is read, and for each head of the source packet header, whether 29 bits designated for the insert packet mark IPM of the source packet header is "0" or "1", and the setting is performed. Perform different processing depending on the value. When the insert packet mark IPM is “0”, the data including the source packet header stored in the FIFO 110 is read out, and as shown in FIG. Output to the transmission circuit.

When the insert packet mark IPM is "1", the post-transmission processing circuit 107 performs an insert packet transmission process. When the insert packet mark IPM is confirmed, the above 7 bits of the source packet header are stored in the register SPH-RSV of the CFR 111.
And sends it to the link core 101. Specifically, when the insert packet mark IPM is “1”, the read pulse signal INS-RD is necessary to use the data written by the CPU 30 in the insert packet FIFO 104 c as data after the source packet header. FIFO10 for a large number of data
4c, and sequentially reads out necessary data, and outputs an insert packet to the link core 101 by adding, for example, the above-mentioned predetermined header.

The post-transmission processing circuit 107 sets the signal INS-MK to logic "1" during the insert packet transmission process. This signal INS-MK is actually a signal obtained by latching the IPM of the source packet header.
The setting of the signal INS-MK is performed even if the source packet header of the insert packet is not transmitted due to the LATE determination. The signal INS-MK is used to reset the register IPTxGo to “0”, and the CPU 30 confirms that the register IPTxGo has become “0”, and knows that the insert packet transmission processing has ended. Then, when processing the source packet header of the next isochronous packet, the post-transmission processing circuit 107 sets the signal INS-MK to “0”.

The pre-reception processing circuit 108
1 receives an isochronous communication packet transmitted on the IEEE 1394 serial bus BS via the IEEE 1394, analyzes the contents of the 1394 header, CIP headers 1, 2 and the like of the received packet, restores the data, and extracts the source packet header and data. The data is stored in the FIFO 110.

The post-reception processing circuit 109 reads the time data of the time stamp of the source packet header stored in the FIFO 110 into the internal register, and reads the read time stamp data (TS) and the cycle time by the cycle timer in the link core 101. When the cycle time CT is larger than the time stamp data TS, the data except for the source packet header stored in the FIFO 110 is read out via the application interface circuit 103 and is transmitted as MPEG transport stream data. Output to the transporter 40.

The CPU 30 controls the entire system. Also, as described above, the time stamp delay time Txdelay for setting the SPH (source packet header) of the isochronous communication packet is set in the CFR 111 through the host interface 102. Furthermore, when it becomes necessary to insert insert packet data, which is a control packet, between normal MPEG transport stream data TSD, "1" is set to the register IPTxGo of the CFR 111. Then, when this register IPTxGo switches to “0”, it recognizes that the insert packet has been completed.

Next, the IEEE 1394 serial bus BS
The operation of transmitting an isochronous communication packet transmitted over the network will be described.

When transmitting an asynchronous communication packet to the IEEE 1394 serial bus BS, for example, the CPU 30 sends the SP of the isochronous communication packet.
The time stamp delay time Txdelay set in H (source packet header) is set in the CFR 111 through the host interface 102. Also, normal MP
During normal processing in which it is not necessary to insert insert packet data, which is a control packet, between EG transport stream data TSD, the register IPTxGo of the CFR 111 is kept at “0”.

In the normal transmission processing, the pre-transmission processing circuit 106 executes the application interface circuit 10
3 via MPEG transporter 40
Upon receiving the transport stream data, the IEEE1
The data length is adjusted in quadlets (4 bytes) for isochronous communication according to the 394 standard. At this time,
The value of the time stamp is set using the delay time Txdelay set in the CR 111, and a 4-byte source packet header (SPH) is added and stored in the FIFO 110. When a normal source packet header is generated when the setting of the register IPTxGo is “0”, the 29-bit insert packet mark IPM bit 29 is held at “0”.

In this case, in the post-transmission processing circuit 107, the FIOF access control circuit 106 of the pre-transmission processing circuit 106
Receiving the storage information signal S106 by the
1394 header and CIP headers 1 and 2 are added to the data including the source packet header stored in 0, output to the transmission circuit of the link core 101, and transmitted to the IEEE 1394 serial bus BS via the physical layer circuit 20. The packet is transmitted as an asynchronous communication packet.

Here, when it becomes necessary to insert the insert packet data as the control packet between the normal MPEG transport stream data TSD, the control packet data is first written from the CPU 30 into the insert packet FIFO 104c. It is. Also,
The CPU 30 registers the register IPTxGo of the CFR 111.
Is set to "1".

Then, in the transmission pre-processing circuit 106, CF
When it is confirmed that the register IPTxGo of R111 is set to “1”, a source packet header is generated at the fall of the packet gap, and writing to the FIFO 110 is performed. At this time, the 29 bits specified for the insert packet mark IPM are set to “1”, indicating that the source packet header written in the FIFO 110 is for the insert packet. Then the FIFO write pointer is moved to the beginning of the next packet.

Next, in the post-transmission processing circuit 107, F
When the source packet data stored in the IFO 110 is read and it is confirmed that the insert packet mark IPM is set to “1”, an insert packet transmission process is performed. Insert packet mark IPM
Is confirmed to be “1”, the data after the source packet header is used as the data for the insert packet FIF.
In order to use the data written by the CPU 30 in O104c, the read pulse signals INS-RD are output to the FIFO 104c by the required number of data. As a result, necessary control packet data is sequentially read, and for example, a predetermined header is added, and insert packet data is output to the link core 101.

In the post-transmission processing circuit 107, the signal INS-MK is "1" during the insert packet transmission process.
Is set to Then, in the post-transmission processing circuit 107, the signal INS-MK is set to “0” when the transmission of the insert packet is completed and the source packet header of the next isochronous packet is processed. And CP
In U30, by confirming that the register IPTxGo has become “0”, it is recognized that the insert packet transmission processing has been completed.

As described above, according to the present embodiment, the control packet FIFO 104c is provided as a storage device of the asynchronous communication system, control data is arbitrarily set by the CPU 30, and the transmission pre-processing is performed under the control of the CPU 30. Circuit 106 and post-transmission processing circuit 107
Since the control packets are inserted between the PEG transport streams, control packets can be arbitrarily transmitted as isochronous packets in addition to normal transport stream packets.

[0057]

As described above, according to the present invention,
The control packet can be inserted into a normal transport stream and transmitted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an MPEG signal processing circuit according to the present invention applied to an IEEE 1394 serial interface.

FIG. 2 is a diagram illustrating a specific configuration of a time stamp.

3A and 3B are diagrams illustrating a byte size of one source packet in isochronous communication, where FIG. 3A is a diagram illustrating a packet size according to the DVB specification, and FIG.

FIG. 4 is a diagram illustrating an example of a correspondence relationship between original data and data to be actually transmitted when data is transmitted by isochronous communication of the IEEE1394 standard.

FIG. 5 is a diagram showing a format of a source packet header.

FIG. 6 is a diagram illustrating a basic configuration example of an isochronous communication packet.

FIG. 7 is a block diagram showing a basic configuration of an isochronous communication system circuit in the IEEE 1394 serial interface.

FIG. 8 is an explanatory diagram in a case where it is necessary to insert control packet data between normal MPEG transport stream data TSD.

[Explanation of symbols]

10: link layer circuit, 101: link core (Link
Core)), 102: Host interface circuit (Host I /
F), 1032: application interface circuit (AP I / F), 104: FIFO for asynchronous communication and control packets, 104a: FIFO for transmission (AT-FIF)
O), 104b ... Reception FIFO (AR-FIFO), 104c ...
FIFO for Insert Packet (Control Packet) (INS-
FIFO), 105 ... Resolver for self ID, 1
06 ... Transmission preprocessing circuit for isochronous communication (TXOut1)
107: Transmission post-processing circuit for isochronous communication (TXOut
2), 108 ... Reception preprocessing circuit for isochronous communication (TXI
n1), 109 ... isochronous communication reception preprocessing circuit (T
XIn2), 110 ... FIFO for isochronous communication (I-FIF
O), 111... Configuration register (CF
R), 20: physical layer circuit, 30: CPU,
40 ... MPEG transporter.

Claims (3)

[Claims] 1. A signal processing circuit for receiving transmission stream packet data from an application side and transmitting the transmission stream packet data to a serial interface bus in a predetermined time cycle, wherein control signal data is generated and A signal processing circuit having control means for inserting the control packet into the serial interface bus as a control packet and transmitting the transmission stream packet to the serial interface bus. 2. A signal processing circuit for receiving transmission stream packet data from an application side and sending out the transmission stream packet data to a serial interface bus in a predetermined time cycle, comprising: a first storage unit; a second storage unit; When it is necessary to transmit data, the control data is written in the first storage means, and control means for setting control data indicating that the control data is to be transmitted, and the control data is not set In this case, a source packet header in which data indicating that control data is not transmitted is added to the received transmission stream packet data and stored in the second storage means in a predetermined format, and the control data is set. The source packet header with data indicating that a control packet should be sent. A first transmitting circuit configured and stored in the second storage means; and a data indicating that control data is not transmitted is set in a source packet header stored in the second storage means. The data stored in the second storage means is transmitted as a transmission stream packet to the digital serial interface bus, and data indicating that control data is to be transmitted to a source packet header stored in the second storage means is transmitted. And a second transmission circuit for transmitting control data stored in the first storage means as a control packet to the digital serial interface bus when set. 3. The signal processing circuit according to claim 2, wherein the second transmission circuit resets the control data set by the control means when the transmission of the control packet ends.