JPH10312337A - Testing circuit for storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a testing circuit for a storage device such as a RAM (random access memory) which has an error correcting function. SOLUTION: This testing circuit is equipped with a test bit decoder 105 which specifies data to be tested and the bit position of an error correction code from an address for the RAM, an error correction code generating means 104 which generates the error correction code from write data, a bit inverting circuit 106 which inverts the value at the bit position of the above-mentioned error correction code, an error correcting means 108 which detects and corrects error bits of output data of the RAM and the error correction code, and a data check circuit which confirms the error detection and correction, and conducts a test for a 1-bit error of the RAM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for a storage device having an error correction function of an information processing apparatus, and more particularly to a diagnosis of an error correction function.

[0002]

2. Description of the Related Art In the prior art, as a test method for a RAM (read / write memory) having an error correction function, an error correction code is generated for an appropriate test pattern by using a normal memory access processing function, and the error correction code is generated.
A method is adopted in which the data is written to the AM and then read to detect an error correction code (1.
63391,2. Public number / Japanese Patent Laid-Open No. 01-10943
No. 9, 3. Publication No./JP-A-64-001198). At this time, as a means for covering the test of the RAM, by writing “0” to all the bits of the RAM and reading it correctly and by writing “1” and reading it correctly, it is possible to shorten the time. And enables efficient RAM testing. On the other hand, as a test method of the error correction function of the RAM, there is a method in which test patterns having an appropriate 1-bit error are prepared in advance for the number of data bits, written into the RAM, and then read to test. One is to generate an error correction code for an appropriate test pattern in advance, write it to the RAM, and then invert any one bit at the reading stage to pseudo-create data with a one-bit error. There is a method in which an expected error correction result is created in advance, and the result is compared with the result of performing an error correction test.

[0003]

In the prior art,
As a test method of RAM having an error correction function, RAM
By writing “0” to all the bits of the memory and reading it correctly and writing “1” to read it correctly, the RAM test can be performed efficiently in a short time while error correction is performed. In the function test, first, if test patterns having an appropriate 1-bit error are prepared in advance for the number of data bits, a plurality of test patterns are required and the error correction function test can be performed in a short time. There is a problem that it cannot be implemented. Second, an error correction code is generated for an appropriate test pattern in advance, and after writing this in a RAM, any one bit is inverted at a reading stage to pseudo-create data having a one-bit error. In addition, when the expected error correction result is created in advance and compared with the result of the error correction test, the test pattern to be prepared can be reduced, but the error correction function test is not exhaustive and dedicated hardware There is a problem that wear must be prepared.

[0004] The present invention has been made in view of such circumstances, and has a short-time and efficient RAM having an error correction function.
By using the test method, a high-speed and comprehensive error correction function test can be realized with a small hardware investment.

[0005]

According to the first aspect of the present invention,
A readable / writable storage device, an address register for supplying an address to the storage device, a write data register holding data to be written to the storage device, and an output of the write data register are supplied. An error correction code generation means for setting the error correction code to all bits "0" when the bit is "0", and setting the error correction code to all bits "1" when the output is all bits "1"; An error correction code output from the code generation means is supplied,
A bit inverting circuit for controlling on / off by a control signal, inverting a bit position to be inverted, of one bit of write data and an error correction code specified from the outside, and writing the same to the storage device; The read data and the error correction code read from the storage device are supplied, error correction means for detecting and correcting these errors, and the read data corrected by the error correction means are supplied. All bits "0" or all bits "
A test circuit for a storage device, comprising: a data check circuit for confirming that it is 1 ". The invention according to claim 2 is the test circuit for a storage device according to claim 1, wherein the output of the address register is supplied. And a test bit decoder for designating an arbitrary one-bit position of each of data and an error correction code to be decoded and written in the storage device, whereby the bit inversion position in the bit inversion circuit is determined. It is characterized by.

According to a third aspect of the present invention, there is provided a readable / writable storage device, an address register for supplying an address to the storage device, a write data register for holding data to be written to the storage device, The output of the register is supplied. When the output is all "0", the error correction code is set to "0". When the output is all "1", the error correction code is set to "1". And an output of the storage device, the ON / OFF of which is controlled by a control signal, and the bit position to be inverted is one bit of the write data and the error correction code designated from outside. A bit inverting circuit for inverting the value of the bit inversion and writing the same in the storage device, an output of the bit inversion circuit and an error correction code are supplied, and these errors are detected and corrected. And a data check circuit to which read data corrected by the error correction means is supplied and which confirms that this value is all bits "0" or all bits "1". This is the test circuit of the device. According to a fourth aspect of the present invention, in the test circuit of the storage device according to the third aspect, an output of the address register is supplied, and any one of data and an error correction code to be decoded and written to the storage device is provided. A test bit decoder for designating a bit position is provided, whereby a bit inversion position in the bit inversion circuit is determined.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the first embodiment.
It is a RAM that can be corrected. Reference numeral 102 denotes the RAM
This is an address register that holds a write / read address to / from the address 101. Reference numeral 103 denotes the RAM 101
This is a write data register that holds write data to the memory. Reference numeral 104 denotes the write data register 1
When the values of 03 are all “0”, all error correction codes are “
This is an error correction code generation means that can set all the error correction codes to "1" when the value of the write data register 103 is "1".
Is a test bit decoder that decodes the output of the address register 102 and specifies any one bit of the write data and the error correction code with respect to the number of data bits.

Reference numeral 106 denotes a bit inversion circuit that inverts any one bit of the write data and the error correction code specified by the test bit decoder 105. Reference numeral 107 denotes an inversion control flag for controlling the bit inversion circuit 106. Reference numeral 108 denotes the RA
Error correction means for detecting and correcting a 1-bit error in the read data and error correction code read from M101. The code 109 indicates that the read data corrected by the error correction means 108 is all bits "0" or all bits "0".
This is a data check circuit for checking that the inversion control flag 107 is "1".
When the value is “0”, the bit inversion circuit 106 is invalidated, and the value becomes “
When "1", the bit inversion circuit 106 is enabled to invert any one bit specified by the test bit decoder 105. The test bit decoder 105 specifies all bits of data to be written to the RAM 101 by the value of the address register 102. Shall be covered.

Next, the operation of the present invention will be
A test of the error correction function for a data bit number of 24 bits in which the number of data bits given to the data register 103 is 18 bits and the number of error correction codes generated by the error correction code generation means 14 is 6 bits is performed.
An example in which data of "0" is used will be described.
3 shows an error correction code table used by the error correction code generation means 104. According to the error correction code table of FIG. 3, the error correction code C0 is "1" in the row to which C0 is assigned.
Is generated by the exclusive OR of the data D00 and D08, and if all the data D00 and D17 are "0", C
The value of 0 is "0". Similarly, the value of C1 to C5 is also 0, so that all 24 bits written to the RAM 101 can be set to "0". In the test of the RAM 101 in the related art, the inversion control flag 107 is set to “
0 "and the address register 102 is stored in the RAM 101
The test is performed by writing all 24-bit data of all 0s generated as described above to all the addresses of the RAM 101 by incrementing from the first address to the last address of the RAM 101 and reading all the data of "0" correctly. carry out. At this time, the error correction unit 108 does not perform a correction operation because the read data is correct.

On the other hand, when the inversion control flag 107 is set to 1 to enable the bit inversion circuit 106 to test the error correction means 108, the test bit decoder out of all "0" data generated as described above is used. 105
Any one bit designated by (1) is inverted to 1 by the bit inverting circuit 106, and only one bit has an error.
Data of "0" is generated. The data of all "0" having a 1-bit error generated in this manner covers the bit position of the 1-bit error for all bits according to the value of the address register 102. , Address register 102
Is incremented from the first address to the last address, so that all bits having only one bit error with respect to all the 18-bit data positions of the RAM 101 "
Then, the address register 102 is incremented from the first address to the last address, and the data of all bits "0" having only one bit error is read from the RAM 101. At this time, the error correction means 108 Performs 1-bit error detection and correction according to the error correction code table of FIG.

The detection and correction of a 1-bit error by the error correction means 108 is performed by obtaining error correction information S0-S5, and the bit position of an I-bit error is detected and corrected by the bit pattern of S0-S5. For example, when D00 is a one-bit error, the value of S0 is generated by the exclusive OR of D00-D08 and the error correction code C0, which become "1" in the row assigned to S0 in the error correction code table of FIG. When D00 is a one-bit error, the value of S0 is "
1 ". Similarly, S1 to S5 are generated, and
Although the value 110100 of 0-S5 is obtained, since this bit pattern corresponds to the column of D00, it is detected that D00 is a 1-bit error, and the value of D00 is corrected to the correct value "0" by inverting the value of D00. . The data check circuit 109 checks all the bits “0” of all the bits “0” data correctly corrected by the error correction means 108 to confirm that the error correction function operates normally. If error correction is not performed correctly, the data check circuit 109 detects that the error correction function did not operate normally by checking all bits “0”.

Next, the following description will be given with reference to FIG. 2 which is a block diagram of a second embodiment of the present invention. In the configuration of FIG. 2, components denoted by the same reference numerals as those in FIG. 1 are the same as those in FIG.
Referring to FIG. 2, the operation of the second embodiment will be described in the case where the number of data bits given to data register 103 is 18 bits and the number of bits of the error correction code generated by error correction code generation means 104 is 6 bits in this configuration. Test for error correction function for a total of 24 data bits
An example in which the data of "1" is used will be described.
4 shows an error correction code table used by the correction code generation means 104. According to the error correction code table of FIG. 3, the error correction code C0 is "1" in the row to which C0 is assigned.
Is generated by an exclusive OR of the data D00 to D08. If all the data D00 to D17 are "1", C is generated.
The value of 0 is "1". Similarly, since the value of C1 to C5 is also "1", all 24 bits written to the RAM 101 can be all set to "1". In the test of the RAM 101 in the conventional technology, the address register 10
2 is incremented from the first address to the last address of the RAM 101, and the data of all bits “1” of all 24 bits generated as described above are stored in the RAM 1
01 for all addresses, and inversion control flag 1
07 is set to “0”, and a test is performed by correctly reading data of all bits “1” from the RAM 101. At this time, the error correction unit 108 does not perform a correction operation because the read data is correct.

On the other hand, in order to test the error correction means 108, the data of all bits “1” is written to all the addresses of the RAM 101 by incrementing the address register 102 from the first address to the last address. After that, the inversion control flag 107 is set to “1” to enable the bit inversion circuit 106, the address register 102 is incremented from the start address to the last address, and when all the data “1” is read from the RAM 101, Of the data of "1", any one bit designated by the test bit decoder 105 inverts the value to "0" by the bit inversion circuit 106,
The data is read out as data of all bits “1” having only one bit error. The test bit decoder 105 covers the bit position of the 1-bit error for all bits according to the value of the address register 102. In this manner, data of all bits "1" having a one-bit error is read from the RAM 101 via the bit inversion circuit 106. At this time, the error correction means 108 detects the one-bit error according to the error correction code table shown in FIG.・ Make corrections. 1 by the error correction means 108
The detection and correction of the bit error is exactly the same as that described in the first embodiment, and the description is omitted.

As described above, as a test method of a RAM having an error correction function, "0" can be written and read correctly for all bits of the RAM, and "1" can be correctly read and written for all bits of the RAM. In the test of the error correction function, in the embodiment based on claim 1, the value “0” or “0” is set for all the bits of the RAM. RAM
When writing the value "1" for all bits of the bit, the bit position information that can cover all the bit positions is obtained from the address of the RAM, so that any one bit is inverted and then written to the RAM and the bit is inverted when read. Is correctly corrected by the error correction function. For this reason, by using a short and exhaustive RAM test method of a RAM having an error correction function, an efficient and exhaustive error correction function test can be realized with a small investment of hardware. Similarly, in the second embodiment, “0” is set for all bits of the RAM, or “1” is set for all bits of the RAM.
When writing to and reading from the RAM, the bit position information that can cover all the bit positions is obtained from the address of the RAM, so that any one bit is inverted and read, and that the inverted bit is correctly corrected by the error correction function. Testing. For this reason, by using a short and exhaustive RAM test method of a RAM having an error correction function, an efficient and exhaustive error correction function test can be realized with a small investment of hardware.

Thus, when preparing test patterns having an appropriate one-bit error in advance by the number of data bits, which is the first problem presented above, a plurality of test patterns are required. After solving the problem that the test of the error correction function cannot be performed in a short time, the second problem, which is to generate an error correction code for an appropriate test pattern in advance and write it to the RAM, When inverting an arbitrary one bit at the reading stage to pseudo-create data having a one-bit error and generating an expected error correction result in advance and comparing the result with the result of the error correction test, Although the test patterns to be prepared can be reduced, the problem that the test of the error correction function is not exhaustive and that dedicated hardware must be invested. It is possible to attain.

In the above description of the embodiment, the bit inversion position in the bit inversion circuit 106 is determined by the test bit decoder 105, but this is not necessarily determined by the test bit decoder but by other means or circuits. It does not matter.

[0017]

As described above, as a test method for a RAM having an error correction function, "0" is written and read correctly for all bits of the RAM, and "1" is written and read correctly in a short time. By using an exhaustive RAM test method, with a small hardware investment,
An effect that an efficient and comprehensive test of the error correction function can be realized can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a test circuit of a storage device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a test circuit of a storage device according to a second embodiment of the present invention.

FIG. 3 is an error correction code table for generating an error correction code and detecting a bit position to be corrected.

[Explanation of symbols]

 101: RAM, 102: Address register, 103: Write data register, 104: Error correction code generation means, 105: Test bit decoder, 106: Bit inversion circuit, 107: Inversion control flag, 108: Error detection / correction means, 109 … Data check circuit

Claims (4)

[Claims] 1. A read / write storage device, an address register for supplying an address to the storage device, a write data register holding data to be written to the storage device, and an output of the write data register When the output is all bits "0", the error correction code is changed to all bits "0".
An error correction code generating means for setting the error correction code to all bits "1" when the output is all bits "1"; and an error correction code output from the error correction code generating means. ON / OFF control by
A bit inverting circuit for inverting the value of one bit of write data and an error correction code whose bit position to be inverted is specified from the outside, and writing the inverted value to the storage device; read data read from the storage device; And error correction code, and error correction means for detecting and correcting these errors, and read data corrected by the error correction means are supplied, and this value is set to all bits "0" or all bits "1".
A test circuit for a storage device, comprising: a data check circuit for confirming that And a test bit decoder which receives an output of the address register, decodes the output, and specifies an arbitrary one-bit position of each of data to be written to the storage device and an error correction code. 2. The test circuit according to claim 1, wherein the bit inversion position in the bit inversion circuit is determined. 3. A readable and writable storage device, an address register for supplying an address to the storage device, a write data register holding data to be written to the storage device, and an output of the write data register. When the output is all bits "0", the error correction code is changed to all bits "0".
When the output is all bits "1", an error correction code generating means for setting the error correction code to all bits "1", and the output of the storage device are supplied, and on / off control is performed by a control signal. A bit inversion circuit for inverting the value of one bit of the write data and the error correction code whose bit position to be inverted is specified from outside, and writing the inverted value to the storage device; A code is supplied, error correction means for detecting and correcting these errors, and read data corrected by the error correction means are supplied, and this value is all bits "0" or all bits "1".
A test circuit for a storage device, comprising: a data check circuit for confirming that 4. An apparatus according to claim 1, further comprising a test bit decoder which receives an output of said address register, decodes the data, and specifies an arbitrary one-bit position of each of data to be written to said storage device and an error correction code. 4. The test circuit according to claim 3, wherein a bit inversion position in the bit inversion circuit is determined.