JPH10321954A - Group III nitride semiconductor device and method of manufacturing the same - Google Patents

Group III nitride semiconductor device and method of manufacturing the same

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Publication number
JPH10321954A
JPH10321954A JP12523897A JP12523897A JPH10321954A JP H10321954 A JPH10321954 A JP H10321954A JP 12523897 A JP12523897 A JP 12523897A JP 12523897 A JP12523897 A JP 12523897A JP H10321954 A JPH10321954 A JP H10321954A
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JP
Japan
Prior art keywords
group iii
iii nitride
nitride semiconductor
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP12523897A
Other languages
Japanese (ja)
Inventor
Takeshi Suzuki
健 鈴木
Toshiyuki Matsui
俊之 松井
Akihiko Oi
明彦 大井
Hiroshi Kamijo
洋 上條
Hideaki Matsuyama
秀昭 松山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Filing date
Publication date
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Priority to JP12523897A priority Critical patent/JPH10321954A/en
Publication of JPH10321954A publication Critical patent/JPH10321954A/en
Withdrawn legal-status Critical Current

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Abstract

(57)【要約】 【課題】電流路に高抵抗部分がなく、動作時に発熱の少
ないAlx Gay In1-x- y N からなるIII 族窒化物半導体素
子とその製造方法を提供する。 【解決手段】半導体基板上1sにAlx Gay In1-x-y N (0
≦x、y、かつx+y≦1)からなるIII 族窒化物半導
体薄膜 3〜7 が積層されてなり、最終のIII族窒化物半
導体薄膜の上に電極層8aが形成されているIII 族窒化物
半導体素子において、前記基板と前記III 族窒化物半導
体薄膜の間には、金属導電性を示し、岩塩型または六方
晶系の結晶構造である遷移金属窒化物からなるバッファ
層2cを介在させる。
(57) Abstract: current path without the high-resistance portion, provides little heat during operation Al x Ga y In 1-x- y N Group III nitride semiconductor device and its manufacturing method. SOLUTION: Al x Ga y In 1-xy N (0
≦ x, y, and x + y ≦ 1). A group III nitride in which an electrode layer 8a is formed on a final group III nitride semiconductor thin film 3 to 7 In the semiconductor element, a buffer layer 2c made of a transition metal nitride exhibiting metal conductivity and having a rock salt type or hexagonal crystal structure is interposed between the substrate and the group III nitride semiconductor thin film.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】Alx Gay In1-x-y N 膜を用い
たレーザーダイオードや発光ダイオードなどのIII 族窒
化物半導体素子に関し、特に、それらの抵抗の低い電極
を有するIII 族窒化物半導体素子に関する。
Relates III nitride semiconductor device, such as a BACKGROUND OF THE INVENTION The Al x Ga y In 1-xy N film laser diode or a light emitting diode using, in particular, III-nitride semiconductor having a low electrode of their resistance Related to the element.

【0002】[0002]

【従来の技術】現在、GaN あるいはAlN の大きい単結晶
は得られていないので、Alx Gay In1- x-y N 膜を用いた
レーザーダイオード(以下、LDと記す)または発光ダ
イオード(以下、LEDと記す)などのIII 族窒化物半
導体素子は、例えば、サファイア(Al2 O3) 、スピネル
(MgAl2O4) 、ケイ素(Si)、炭化ケイ素(SiC) 等の他の材
料からなる単結晶基板上に形成されている。通常は、格
子不整合による歪みを緩和するために、基板面にAlN バ
ッファー層またはGaN 低温バッファー層を形成し、その
上に種々のAlx Gay In1-x-y N 膜の成膜を行っている。
2. Description of the Related Art At present, single crystals of GaN or AlN having a large size have not been obtained. Therefore, a laser diode (hereinafter referred to as LD) or a light emitting diode (hereinafter referred to as LED) using an Al x Ga y In 1- xy N film. Group III nitride semiconductor devices such as sapphire (Al 2 O 3 ), spinel
It is formed on a single crystal substrate made of another material such as (MgAl 2 O 4 ), silicon (Si), and silicon carbide (SiC). Usually, an AlN buffer layer or a GaN low-temperature buffer layer is formed on the substrate surface, and various Al x Ga y In 1-xy N films are formed on the substrate surface in order to alleviate distortion due to lattice mismatch. I have.

【0003】このような従来実用化されているAlx Gay
In1-x-y N 膜を用いたLEDなどの半導体素子において
は、絶縁材料である基板を電流路としては利用できない
ので、次のような構造とせざるを得なかった。図5は従
来のサファイア基板に形成された発光ダイオードの断面
図である。サファイア基板1iにAlN バッファ層2、n
型 GaNからなる第1のコンタクト層3、n型AlGaN から
なる第1のクラッド層層4、 GaN活性層5、p型 AlGaN
からなる第2のクラッド層6、 p型 GaNからなる第2の
コンタクト層7、 Al/Tiからなるエピタキシャル層側電
極層8a(以降エピ側電極層と略記する)が積層されて
おり、III 族窒化物半導体層4〜7をエッチング除去
し、残したn型 GaNのコンタクト層3にAu/Cr よりなる
基板側電極8bを形成していた。すなわち、n型 GaNの
コンタクト層3を導電性のリード部材として利用してお
り、電流路の断面はコンタクト層3の厚さと幅(図5紙
面に垂直方向)の積であり極めて小さく、ドーピングに
よりGaN コンタクト層の抵抗値を小さくしてもリード部
は高抵抗となりやすい。
[0003] Such Al x Ga y which has been put to practical use in the past.
In a semiconductor device such as an LED using an In 1-xy N film, a substrate, which is an insulating material, cannot be used as a current path, so that the following structure must be used. FIG. 5 is a sectional view of a light emitting diode formed on a conventional sapphire substrate. AlN buffer layer 2, n on sapphire substrate 1i
Contact layer 3 of n-type GaN, first cladding layer layer 4 of n-type AlGaN, GaN active layer 5, p-type AlGaN
A second contact layer 7 made of p-type GaN, an epitaxial layer side electrode layer 8a made of Al / Ti (hereinafter abbreviated as epi side electrode layer), and The nitride semiconductor layers 4 to 7 were removed by etching, and the substrate-side electrode 8b made of Au / Cr was formed on the remaining n-type GaN contact layer 3. That is, the contact layer 3 of n-type GaN is used as a conductive lead member, and the cross section of the current path is the product of the thickness and the width of the contact layer 3 (in the direction perpendicular to the plane of FIG. 5). Even if the resistance of the GaN contact layer is reduced, the lead tends to have high resistance.

【0004】しかし、低抵抗の半導体材料からなる基板
を用いることができれば、基板側電極を基板裏に形成し
基板を通した電流路を構成できる。図6は従来の半導体
基板上に形成された発光ダイオードの断面図である。半
導体基板はSiである。基板側電極8bは基板裏側に形
成されており、基板と素子とは同じ面積である点を除
き、III 族窒化物半導体層の層構成は図5と同じなの
で、層構成の説明を省略する。n側電極8bが基板1の
裏側に形成されているため、電流路の断面は素子面積と
なるため電流路の抵抗は低くなることが期待できる。ま
た、材料の有効面積比は大きくなり、またIII 族窒化物
半導体層のエッチング除去が不要となり、製造工程が少
なくなり、量産に適している。
However, if a substrate made of a low-resistance semiconductor material can be used, a substrate-side electrode can be formed on the back of the substrate to form a current path through the substrate. FIG. 6 is a cross-sectional view of a conventional light emitting diode formed on a semiconductor substrate. The semiconductor substrate is Si. The substrate-side electrode 8b is formed on the back side of the substrate, and the layer configuration of the group III nitride semiconductor layer is the same as that of FIG. 5 except that the substrate and the element have the same area, and thus the description of the layer configuration is omitted. Since the n-side electrode 8b is formed on the back side of the substrate 1, the cross section of the current path becomes the element area, so that the resistance of the current path can be expected to be low. Further, the effective area ratio of the material is increased, and the removal of the group III nitride semiconductor layer by etching is not required, and the number of manufacturing steps is reduced, which is suitable for mass production.

【0005】[0005]

【発明が解決しようとする課題】しかし、半導体基板上
へのIII 族窒化物半導体層成膜において、従来用いられ
るAlN またはGaN バッファー層は、AlN は絶縁体であ
り、GaN の抵抗もあまり低くできないため、バッファー
層はまだ素子抵抗を高くしている要因である。また、p
型のAlx Gay In1-x-y N に形成される電極としては、従
来はAu/Cr 電極を用いているが、接触抵抗が大きく、こ
れもまた、素子抵抗を増加させる要因となっていた。
However, in forming a group III nitride semiconductor layer on a semiconductor substrate, the AlN or GaN buffer layer conventionally used is an AlN insulator, and the resistance of GaN cannot be reduced too much. Therefore, the buffer layer is a factor that still increases the element resistance. Also, p
Conventionally, Au / Cr electrodes were used as the electrodes formed on the Al x Ga y In 1-xy N type, but the contact resistance was large, which also caused an increase in the element resistance. .

【0006】これらの素子抵抗を増加させている部分
は、ジュール発熱部になってしまい、素子の特性や信頼
性を損なう原因となっていた。本発明の目的は、電流路
に高抵抗部分がなく、動作時に発熱の少ないAlx GayIn
1-x-y N からなるIII 族窒化物半導体素子を提供するこ
とにある。
[0006] The portion where the element resistance is increased becomes a Joule heat generating portion, which is a cause of deteriorating the characteristics and reliability of the element. SUMMARY OF THE INVENTION It is an object of the present invention to provide an Al x Ga y In which has no high resistance portion in a current path and generates less heat during operation.
An object of the present invention is to provide a group III nitride semiconductor device made of 1-xyN .

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
めに、半導体基板上にAlx Gay In1-x-y N (0≦x、
y、かつx+y≦1)からなるIII 族窒化物半導体薄膜
が積層されてなり、最終のIII 族窒化物半導体薄膜の上
に電極層が形成されているIII 族窒化物半導体素子にお
いて、前記基板と前記III 族窒化物半導体薄膜の間に
は、金属導電性を示し、岩塩型または六方晶系の結晶構
造である遷移金属窒化物からなるバッファ層を介在させ
ることとする。
In order to achieve the above object, Al x Ga y In 1-xy N (0 ≦ x,
y, and x + y ≦ 1). In a group III nitride semiconductor device in which an electrode layer is formed on a final group III nitride semiconductor thin film composed of A buffer layer made of a transition metal nitride exhibiting metal conductivity and having a rock salt type or hexagonal crystal structure is interposed between the group III nitride semiconductor thin films.

【0008】前記遷移金属窒化物は窒化チタン(TiN
)、窒化バナジウム(VN)、窒化ジルコニウム(ZrN
)、窒化ニオブ(NbN )または窒化ハフニウム(HfN
)のうちのいずれかまたはこれらのうちの2つからな
る混晶、または窒化タンタル(TaN )であると良い。前
記半導体基板はケイ素、炭化ケイ素、燐化ガリウム、ヒ
化ガリウムであると良い。
[0008] The transition metal nitride is titanium nitride (TiN).
), Vanadium nitride (VN), zirconium nitride (ZrN
), Niobium nitride (NbN) or hafnium nitride (HfN
), Or a mixed crystal composed of two of them, or tantalum nitride (TaN). The semiconductor substrate is preferably silicon, silicon carbide, gallium phosphide, or gallium arsenide.

【0009】前記バッファ層と前記III 族窒化物半導体
薄膜の間に第2のバッファ層を介在させ、さらに格子不
整合緩和を行うと良い。前記第2のバッファ層は前記II
I 族窒化物半導体薄膜と同じ組成であり、かつ前記III
族窒化物半導体薄膜の成膜時の基板温度より低い基板温
度で成膜された低温成膜層であると良い。
Preferably, a second buffer layer is interposed between the buffer layer and the group III nitride semiconductor thin film to further reduce lattice mismatch. The second buffer layer is formed of the II
The same composition as the group I nitride semiconductor thin film, and
It is preferable that the low-temperature film formation layer is formed at a substrate temperature lower than the substrate temperature at the time of forming the group III nitride semiconductor thin film.

【0010】前記低温成膜層の基板温度は25℃以上5
00℃以下であると良い。前記第2のバッファ層は前記
III 族窒化物半導体薄膜と同じ組成の薄膜、と前記バッ
ファ層からなる2重層の複数積層である超格子層である
と良い。前記2重層の厚さは50nm以下であると良い。
また、半導体基板上にAlx Gay In1-x-y N (0≦x、
y、かつx+y≦1)からなるIII 族窒化物半導体薄膜
が積層されてなり、最終のIII 族窒化物半導体薄膜の上
に電極層が形成されているIII 族窒化物半導体素子にお
いて、前記電極層は金属導電性を示し、岩塩型または六
方晶系の結晶構造である遷移金属窒化物からなる薄膜か
らなることとする。
[0010] The substrate temperature of the low-temperature film-forming layer is at least 25 ° C and 5
The temperature is preferably not higher than 00 ° C. The second buffer layer is
It is preferable that the superlattice layer be a thin film having the same composition as the group III nitride semiconductor thin film and a plurality of double layers including the buffer layer. The thickness of the double layer is preferably 50 nm or less.
In addition, Al x Ga y In 1-xy N (0 ≦ x,
y, and x + y ≦ 1). In the group III nitride semiconductor device in which an electrode layer is formed on a final group III nitride semiconductor thin film, the group consisting of: Is a thin film made of a transition metal nitride having a metal salt conductivity and a rock salt type or hexagonal crystal structure.

【0011】前記遷移金属窒化物は窒化チタン(TiN
)、窒化バナジウム(VN)、窒化ジルコニウム(ZrN
)、窒化ニオブ(NbN )、窒化ハフニウム(HfN )の
うちのいずれかまたはこれらのうちの2つからなる混
晶、または窒化タンタル(TaN )であると良い。上記の
III 族窒化物半導体素子の製造方法において、前記遷移
金属窒化物からなる層はは分子線エピタキシーにより成
膜されると良い。
The transition metal nitride is titanium nitride (TiN).
), Vanadium nitride (VN), zirconium nitride (ZrN
), Niobium nitride (NbN), hafnium nitride (HfN), a mixed crystal composed of two of them, or tantalum nitride (TaN). above
In the method for manufacturing a group III nitride semiconductor device, the layer made of the transition metal nitride may be formed by molecular beam epitaxy.

【0012】[0012]

【発明の実施の形態】発明者らは、遷移金属窒化物のい
くつかとそれらの混晶の薄膜をケイ素(Si)、ゲルマニ
ウム(Ge)、炭化ケイ素(SiC )、燐化ガリウム(GaP
)、ヒ化ガリウム(GaAs)などの半導体基板上にエピ
タキシャル成長させることができ、またエピタキシャル
成長層を基板とIII 族窒化物積層の間にバッファ層とし
て介在させることにより、Alx Gay In1-x-y N 膜に対す
る格子マッチングが良く、良質のAlx Gay In1-x-y N 膜
を容易にエピタキシャル成膜可能であることを見いだし
た。これらの遷移金属窒化物の結晶型と格子定数等を表
1に示す。
DETAILED DESCRIPTION OF THE INVENTION The present inventors have developed thin films of some of transition metal nitrides and their mixed crystals into silicon (Si), germanium (Ge), silicon carbide (SiC), gallium phosphide (GaP).
), Epitaxial growth on a semiconductor substrate such as gallium arsenide (GaAs), and an Al x Ga y In 1-xy It has been found that the lattice matching with the N film is good, and that a high-quality Al x Ga y In 1-xy N film can be easily epitaxially formed. Table 1 shows the crystal types and lattice constants of these transition metal nitrides.

【0013】[0013]

【表1】 表1に挙げた金属窒化物は、Si、Ge、SiC 、GaAs、GaP
等の半導体基板上へのエピタキシャル成長が可能であ
り、さらに、そのエピタキシャル層へAlx Gay In 1-x-y
N 膜がエピタキシャル成長が可能であった。また、TaN
を除いて、岩塩型の結晶でありこれらの2種の遷移金属
窒化物は格子定数のみが変わる混晶を形成できる。従っ
て、格子定数を適当に選択することによってことにより
Alx GayIn1-x-y N における任意のx、yに対応して
格子不整合を緩和できるバッファ層とすることができ
る。またTaN は六方晶であるが、同様に格子不整合を緩
和できるバッファ層とすることができる。
[Table 1]The metal nitrides listed in Table 1 are Si, Ge, SiC, GaAs, GaP
Epitaxial growth on semiconductor substrates such as
To the epitaxial layer.xGayIn 1-xy
The N film could be grown epitaxially. Also, TaN
With the exception of these, these are two types of transition metals
Nitride can form a mixed crystal in which only the lattice constant changes. Follow
And by choosing the lattice constant appropriately
 AlxGayIn1-xyFor any x and y in N
A buffer layer that can mitigate lattice mismatch
You. Although TaN is hexagonal, it also reduces lattice mismatch.
It can be a buffer layer that can be integrated.

【0014】また、これら材料は金属導電性を示し、半
導体との接触抵抗も低いので、III族窒化物積層の半導
体素子と基板との間の抵抗を増加させることはない。ま
た、同じ理由により、n型半導体基板への電極とする場
合は抵抗増加の要因にならない。一方、p型のAlx Gay
In1-x-y N に対しても接触抵抗は非常に低く、電極材料
として有用である。
Further, since these materials exhibit metal conductivity and low contact resistance with a semiconductor, they do not increase the resistance between the semiconductor element of the group III nitride laminate and the substrate. Further, for the same reason, when an electrode is formed on an n-type semiconductor substrate, it does not cause an increase in resistance. On the other hand, p-type Al x Ga y
The contact resistance is very low even for In 1-xy N and is useful as an electrode material.

【0015】上記の遷移金属窒化物バッファ層を用いて
も格子不整合による歪みは生じているが、第2のバッフ
ァ層を追加することによりこの歪みをさらに緩和でき
る。第2のバッファ層には以降のIII 族窒化物半導体層
と同じ組成の薄膜を含むことが重要であり、この薄膜が
存在することによって格子定数の変化が滑らかにされて
いる。 実施例1 図1は本発明に係る遷移金属窒化物のバッファ層を有す
るIII 族窒化物半導体素子の断面図である。製造工程に
従って構造を説明する。n型Siの基板1s(基板面は(1
11) 面)を酸で表面洗浄し、分子線エピタキシー装置を
用いて、TiN を成膜し、厚さ50nmのバッファ層2cを形
成した。成膜時の基板温度を650 ℃とし、Tiは電子ビー
ム照射により蒸発させ、窒素はrf放電を利用した原子状
窒素源により供給した。この薄膜は(111) 配向してお
り、基板と膜の<111> 軸が互いに平行なエピタキシャル
成長膜であった。
Although the above-mentioned transition metal nitride buffer layer causes distortion due to lattice mismatch, the distortion can be further reduced by adding a second buffer layer. It is important that the second buffer layer includes a thin film having the same composition as the subsequent group III nitride semiconductor layer, and the presence of this thin film makes the change in lattice constant smooth. Example 1 FIG. 1 is a cross-sectional view of a group III nitride semiconductor device having a transition metal nitride buffer layer according to the present invention. The structure will be described according to the manufacturing process. n-type Si substrate 1s (substrate surface is (1
11) The surface was washed with an acid, and a TiN film was formed using a molecular beam epitaxy apparatus to form a buffer layer 2c having a thickness of 50 nm. The substrate temperature during film formation was 650 ° C., Ti was evaporated by electron beam irradiation, and nitrogen was supplied from an atomic nitrogen source utilizing rf discharge. This thin film was (111) oriented, and was an epitaxially grown film in which the <111> axes of the substrate and the film were parallel to each other.

【0016】次いで、基板温度を800 ℃とし、n型GaN
からなる厚さ300nm のコンタクト層3を成膜した。以
下、基板温度800 ℃で、n型Alx Ga1-x N (x=0.15)から
なる厚さ500nm のクラッド層4、GaN からなる厚さ50nm
の活性層5、p型Alx Ga1-x N(x=0.15)からなる厚さ500
nm のクラッド層6、p型GaN からなる厚さ300nm のキ
ャップ層7を順次成膜した。最後に、基板温度650 ℃と
し、分子線エピタキシーにより厚さ50nmのTiN 薄膜をp
側電極8aとして形成し、Si基板1の裏面にはAlからな
るn側電極8bを形成した。
Next, the substrate temperature is set to 800 ° C. and n-type GaN
A contact layer 3 having a thickness of 300 nm was formed. Hereinafter, at a substrate temperature of 800 ° C., a cladding layer 4 of n-type Al x Ga 1-x N (x = 0.15) having a thickness of 500 nm and a thickness of 50 nm of GaN
Active layer 5 of p-type Al x Ga 1 -xN (x = 0.15) with a thickness of 500
A cladding layer 6 of nm and a cap layer 7 of p-type GaN having a thickness of 300 nm were sequentially formed. Finally, at a substrate temperature of 650 ° C., a 50 nm-thick TiN thin film is formed by molecular beam epitaxy.
An n-side electrode 8 b made of Al was formed on the back surface of the Si substrate 1.

【0017】上記の基板を、活性層の面積が0.3mm2のダ
イに切断し、両電極にはAuのワイヤをボンディングして
LED素子を作製した。この素子の順方向の電圧電流特
性を測定したところ、印加電圧3Vで、200mA の順方向電
流が得られた。比較のため、従来のバッファー層として
AlN を用いた以外は、同じ層構成のLED素子を作製し
電圧電流特性を測定したところ、順方向の電圧電流特性
は、印加電圧3Vで50mAの順方向電流だった。
The above substrate was cut into a die having an active layer area of 0.3 mm 2 , and Au electrodes were bonded to both electrodes to produce an LED element. When the forward voltage-current characteristics of the device were measured, a forward current of 200 mA was obtained at an applied voltage of 3 V. For comparison, as a conventional buffer layer
Except for using AlN, an LED element having the same layer structure was prepared and the voltage-current characteristics were measured. The forward voltage-current characteristics were 50 mA forward current at an applied voltage of 3 V.

【0018】また、バッファー層にAlN 、p側電極とし
てAu/Cr 電極を用いた以外は同様の層構成の従来のLE
D素子を作製したところ、印加電圧3Vで10mAの順方向電
流だった。このことから、TiN 層は抵抗の低いバッファ
ー層を実現し、p側電極としてはやはり抵抗の低減をも
たらしたことが判る。 実施例2 実施例1では、バッファ層に用いたTiN とGaN との格子
不整合は6% あり( 表1参照)、TiN 層はまだGaN 層に
歪みを生じさせており、GaN 層上に成長されるAlx Ga
1-X N (X=0.15)にも歪みを伝えている。しかし、バッフ
ァ層に用いた遷移金属窒化物を混晶として、Alx Ga1-x
N (x=0.15)との格子不整合を小さくすることができ、Ga
N のコンタクト層を省略すること可能となる。
A conventional LE having the same layer structure except that AlN was used for the buffer layer and Au / Cr electrode was used for the p-side electrode.
When a D element was manufactured, the forward current was 10 mA at an applied voltage of 3 V. From this, it is understood that the TiN layer realized a buffer layer having low resistance, and also reduced the resistance as the p-side electrode. Example 2 In Example 1, the lattice mismatch between TiN and GaN used for the buffer layer was 6% (see Table 1), and the TiN layer still caused strain in the GaN layer and was grown on the GaN layer. Al x Ga
1-X N (X = 0.15) is also distorted. However, the transition metal nitride used for the buffer layer was mixed with Al x Ga 1-x
The lattice mismatch with N (x = 0.15) can be reduced, and Ga
It is possible to omit the N contact layer.

【0019】図2は本発明に係る混晶バッファ層を有す
るIII 族窒化物半導体素子の断面図である。製造工程に
従って構造を説明する。n型のSi(111) 基板1sを酸で
表面洗浄し、基板温度650 ℃で分子線エピタキシー装置
を用いて厚さ50nmのV0.29Zr0.71N薄膜からなる導電性の
バッファ層2cを成膜した。このとき、Ti、Zrは電子ビ
ームにより蒸発させ、窒素はrf放電を用いた原子状窒素
源により供給した。この薄膜は(111) 配向しており、基
板と膜の<111> 軸が互いに平行なエピタキシャル成長膜
であった。この導電性のバッファー層2cはn型Al0.15
Ga0.85N と格子整合しており、基板温度800 ℃で、n型
Al x Ga1-x N (x=0.15)からなる厚さ500nm のクラッド層
4を直接成膜することができた。
FIG. 2 has a mixed crystal buffer layer according to the present invention.
1 is a cross-sectional view of a group III nitride semiconductor device. In the manufacturing process
Therefore, the structure will be described. n-type Si (111) substrate 1s with acid
Surface cleaning and molecular beam epitaxy at substrate temperature of 650 ° C
50nm thick V using0.29Zr0.71Conductive made of N thin film
The buffer layer 2c was formed. At this time, Ti and Zr
Vaporized by nitrogen and nitrogen is atomic nitrogen using rf discharge
Supplied by source. This thin film is (111) oriented,
Epitaxially grown film with <111> axes of plate and film parallel to each other
Met. This conductive buffer layer 2c is made of n-type Al0.15
Ga0.85Lattice matched with N, n-type at 800 ° C substrate temperature
Al xGa1-x500 nm thick cladding layer made of N (x = 0.15)
4 could be directly formed into a film.

【0020】以下実施例1と同様に、GaN からなる厚さ
50nmの活性層5、p型Alx Ga1-x N(x=0.15)からなる厚
さ500nm のクラッド層6、p型GaN からなる厚さ300nm
のキャップ層7を順次成膜した。最後に、基板温度650
℃で厚さ300nm のZrN 薄膜をエピ側電極8aとして形成
し、Si基板1の裏面にはAlからなる基板側電極8bを形
成した。
In the same manner as in Example 1, the thickness of GaN
Active layer 5 of 50 nm, cladding layer 6 of p - type Al x Ga 1 -xN (x = 0.15) of 500 nm, thickness of 300 nm of p-type GaN
Were sequentially formed. Finally, substrate temperature 650
A 300 nm thick ZrN thin film was formed as an epi-side electrode 8a at a temperature of .degree.

【0021】この基板を活性層の面積が0.3mm2のダイに
切断し、両電極にはAuのワイヤをボンディングしてLE
D素子を作製した。得られたLED素子の順方向の電圧
電流特性を測定したところ、3Vの印加電圧で200mA の電
流であり、実施例1の場合と同様に低抵抗のLED素子
が得られた。
The substrate was cut into dies having an active layer area of 0.3 mm 2 , and Au electrodes were bonded to both electrodes to form an LE.
A D element was produced. When the forward voltage-current characteristics of the obtained LED element were measured, the current was 200 mA at an applied voltage of 3 V, and a low-resistance LED element was obtained as in the case of Example 1.

【0022】このように、VNとZrN の混晶の導電バッフ
ァー層を用いることにより、素子の低抵抗化が実現でき
ると共に格子整合を取ることができ、さらに、コンタク
ト層が不要となり素子構造の簡略化が可能となった。ま
た、製造工程の短縮ができた。 実施例3 遷移金属窒化物のバッファ層の上に、低温で成膜したAl
0.15Ga0.85N からなる第2のバッファ層を挿入すること
により、遷移金属窒化物のバッファー層と第1のクラッ
ド層以降のAl0.15Ga0.85N 層との格子歪みをさらに緩和
することができる。
As described above, by using a conductive buffer layer of a mixed crystal of VN and ZrN, the resistance of the device can be reduced and lattice matching can be achieved. Further, a contact layer is not required and the device structure can be simplified. Has become possible. Further, the manufacturing process can be shortened. Example 3 Al formed at a low temperature on a transition metal nitride buffer layer
By inserting the second buffer layer made of 0.15 Ga 0.85 N, it is possible to further relax the lattice strain of the buffer layer and the first cladding layer and subsequent Al 0.15 Ga 0.85 N layer transition metal nitride.

【0023】図3は本発明に係る低温成膜層を有するII
I 族窒化物半導体素子の断面図である。製造工程に従っ
て構造を説明する。n型のSi(111) 基板1sを酸で表面
洗浄し、基板温度650 ℃で分子線エピタキシー装置を用
いて50nmのNbN 薄膜を成膜しバッファ層2cとした。こ
のとき、Nbは電子ビームにて蒸発させ、窒素はrf放電を
用いた原子状窒素源により供給した。この薄膜は(111)
配向しており、基板と膜の<111> 軸が互いに平行なエピ
タキシャル成長膜であった。
FIG. 3 shows a low-temperature film-forming layer according to the present invention.
FIG. 2 is a sectional view of a group I nitride semiconductor device. The structure will be described according to the manufacturing process. The surface of the n-type Si (111) substrate 1s was washed with an acid, and a 50 nm NbN thin film was formed at a substrate temperature of 650 ° C. using a molecular beam epitaxy apparatus to form a buffer layer 2c. At this time, Nb was evaporated by an electron beam, and nitrogen was supplied by an atomic nitrogen source using rf discharge. This film is (111)
The epitaxial film was oriented and the <111> axes of the substrate and the film were parallel to each other.

【0024】次に、基板温度400 ℃の低温で、10nmのAl
0.15Ga0.85N 層からなる第2のバッファ層として低温成
膜層2tを成膜した。それ以降、基板温度を800 ℃まで
上昇させ、クラッド層4からコンタクト層7までの各II
I 族半導体層を成膜し、図3に示す様なダブルへテロ構
造を形成した。なお、基板温度が室温(25℃)から500
℃の間であれば、低温成膜層2tはアモルファス状であ
り、格子不整合緩和に役立っていることが判った。
Next, at a low substrate temperature of 400 ° C., a 10 nm Al
A low-temperature film formation layer 2t was formed as a second buffer layer composed of a 0.15 Ga 0.85 N layer. Thereafter, the substrate temperature is increased to 800 ° C., and each II from the cladding layer 4 to the contact layer 7 is increased.
A group I semiconductor layer was formed to form a double hetero structure as shown in FIG. In addition, the substrate temperature is changed from room temperature (25 ℃) to 500
When the temperature is between 0 ° C., the low-temperature film-forming layer 2t is in an amorphous state, which has been found to be useful for alleviating lattice mismatch.

【0025】また、電極層8aにはNbN を用いた。この
基板を切断し、上下の電極が0.3mm 角のLEDを作製し
た。この素子の順方向の電圧電流特性を測定した結果、
印加電圧3Vのとき、順方向電流は150mA であり、実施例
1で作製した素子に準じた特性が得られた。 実施例4 遷移金属窒化物のバッファ層の上に、薄いAlx Ga1-x N
層と薄い遷移金属窒化物層を交互に積層した超格子構造
の第2のバッファ層を挿入することにより、これらの層
間に歪みを集中させ、遷移金属窒化物のバッファー層と
第1のクラッド層以降のAl0.15Ga0.85N 層との格子歪み
をさらに緩和することができる。
Further, NbN was used for the electrode layer 8a. This substrate was cut to produce a 0.3 mm square LED with upper and lower electrodes. As a result of measuring the forward voltage-current characteristics of this element,
When the applied voltage was 3 V, the forward current was 150 mA, and characteristics according to the device manufactured in Example 1 were obtained. Example 4 A thin Al x Ga 1-x N layer was formed on a transition metal nitride buffer layer.
By inserting a second buffer layer having a superlattice structure in which layers and thin transition metal nitride layers are alternately stacked, strain is concentrated between these layers, and a transition metal nitride buffer layer and a first cladding layer are formed. Lattice strain with the subsequent Al 0.15 Ga 0.85 N layer can be further reduced.

【0026】図4は本発明に係る超格子層を有するIII
族窒化物半導体素子の断面図である。製造工程に従って
構造を説明する。n型のSi(111) 基板1sを酸で表面洗
浄し、基板温度650 ℃で分子線エピタキシー装置を用い
て50nmのHfN 層を成膜した。このとき、Hfは電子ビーム
により蒸発させ、窒素はrf放電を用いた原子状窒素源に
より供給した。この薄膜は(111)配向しており、基板と
膜の<111> 軸が互いに平行なエピタキシャル成長膜であ
った。
FIG. 4 shows a III having a superlattice layer according to the present invention.
It is sectional drawing of a group nitride semiconductor element. The structure will be described according to the manufacturing process. The surface of the n-type Si (111) substrate 1s was washed with acid, and a 50 nm HfN layer was formed at a substrate temperature of 650 ° C. using a molecular beam epitaxy apparatus. At this time, Hf was evaporated by an electron beam, and nitrogen was supplied by an atomic nitrogen source using rf discharge. This thin film was (111) oriented, and was an epitaxially grown film in which the <111> axes of the substrate and the film were parallel to each other.

【0027】このバッファー層2cの上に、基板温度70
0 ℃で、厚さ10nmのAl0.30Ga0.70N層と厚さ10nmのHfN
層を交互に4回づつ成膜し、超格子構造の第2のバッフ
ァ層2mを形成した。それ以降は基板温度を800 ℃まで
上昇させ、クラッド層4からコンタクト層7までの各II
I 族半導体層を各III 族半導体層を成膜し、図4に示す
様なダブルへテロ構造を形成した。
On the buffer layer 2c, a substrate temperature of 70
At 0 ° C, a 10 nm thick Al 0.30 Ga 0.70 N layer and a 10 nm thick HfN
The layers were alternately formed four times to form a second buffer layer 2m having a superlattice structure. Thereafter, the substrate temperature is raised to 800 ° C., and each II from the cladding layer 4 to the contact layer 7 is heated.
Each group III semiconductor layer was formed as a group I semiconductor layer to form a double heterostructure as shown in FIG.

【0028】また、エピタキシャル層側の電極層8aに
はHfN を用いた。この成膜後の基板を切断し、上下の電
極が0.3mm 角のLEDを作製した。この素子の順方向の
電圧電流特性を測定した結果、印加電圧3Vのとき、順方
向電流は200mA であり、実施例1で作製した素子と同等
の特性が得られた。
HfN was used for the electrode layer 8a on the epitaxial layer side. The substrate after this film formation was cut to produce an LED having upper and lower electrodes of 0.3 mm square. As a result of measuring the forward voltage-current characteristics of the device, when the applied voltage was 3 V, the forward current was 200 mA, and characteristics equivalent to those of the device manufactured in Example 1 were obtained.

【0029】[0029]

【発明の効果】本発明によれば、半導体基板上にAlx Ga
y In1-x-y N (0≦x、y、かつx+y≦1)からなる
III 族窒化物半導体薄膜が積層されてなり、最終のIII
族窒化物半導体薄膜の上に電極層が形成されているIII
族窒化物半導体素子において、前記基板と前記III 族窒
化物半導体薄膜の間には、金属導電性を示し、岩塩型ま
たは六方晶系の結晶構造である遷移金属窒化物からなる
薄膜のバッファ層を介在させたので、基板とAlx Gay In
1-x-y N 膜との間の格子整合が改善され、格子不整合に
よる歪みの緩和を図ることができる。さらにAlx Gay In
1-x-y N 膜を使った半導体レーザーダイオードおよび発
光ダイオードなどの素子抵抗を低減することができる。
According to the present invention, Al x Ga is formed on a semiconductor substrate.
y In 1-xy N (0 ≦ x, y and x + y ≦ 1)
A group III nitride semiconductor thin film is laminated, and the final III
An electrode layer formed on a group III nitride semiconductor thin film III
In the group-III nitride semiconductor device, a thin-film buffer layer made of a transition metal nitride having metal conductivity and having a rock salt type or hexagonal crystal structure is provided between the substrate and the group-III nitride semiconductor thin film. The substrate and Al x Ga y In
Lattice matching with the 1-xy N film is improved, and strain due to lattice mismatch can be reduced. Al x Ga y In
The device resistance of a semiconductor laser diode and a light emitting diode using a 1-xy N film can be reduced.

【0030】また、電極層をTiN 、VN、ZrN 、NbN 、Hf
N または窒化タンタルTaN のうちのいずれかからなる薄
膜、またはこれらのうちの異なる2つからからなる混晶
などの遷移金属窒化物の薄膜としたので、Alx Gay In
1-x-y N 膜を使った半導体レーザーダイオードおよび発
光ダイオードなどの素子抵抗を低減することができる。
The electrode layers are made of TiN, VN, ZrN, NbN, Hf
Since a thin film made of either N or tantalum nitride TaN or a thin film of a transition metal nitride such as a mixed crystal made of two different materials, Al x Ga y In
The device resistance of a semiconductor laser diode and a light emitting diode using a 1-xy N film can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る遷移金属窒化物のバッファ層を有
するIII 族窒化物半導体素子の断面図
FIG. 1 is a cross-sectional view of a group III nitride semiconductor device having a transition metal nitride buffer layer according to the present invention.

【図2】本発明に係る混晶バッファ層を有するIII 族窒
化物半導体素子の断面図
FIG. 2 is a cross-sectional view of a group III nitride semiconductor device having a mixed crystal buffer layer according to the present invention.

【図3】本発明に係る低温成膜層を有するIII 族窒化物
半導体素子の断面図
FIG. 3 is a cross-sectional view of a group III nitride semiconductor device having a low-temperature film formation layer according to the present invention.

【図4】本発明に係る超格子層を有するIII 族窒化物半
導体素子の断面図
FIG. 4 is a sectional view of a group III nitride semiconductor device having a superlattice layer according to the present invention.

【図5】従来のサファイア基板に形成された発光ダイオ
ードの断面図
FIG. 5 is a cross-sectional view of a light emitting diode formed on a conventional sapphire substrate.

【図6】従来のSi基板上に形成された発光ダイオード
の断面図
FIG. 6 is a cross-sectional view of a light emitting diode formed on a conventional Si substrate.

【符号の説明】[Explanation of symbols]

1i サファイア基板 1s 半導体基板 2 バッファ層 2c バッファ層 2t 低温成膜層 2m 超格子層 3 第1のコンタクト層 4 第1のクラッド層 5 活性層 6 第2のクラッド層 7 第2のコンタクト層 8a エピタキシャル層側電極層 8b 基板側電極層 Reference Signs List 1i Sapphire substrate 1s Semiconductor substrate 2 Buffer layer 2c Buffer layer 2t Low-temperature deposition layer 2m Superlattice layer 3 First contact layer 4 First clad layer 5 Active layer 6 Second clad layer 7 Second contact layer 8a Epitaxial Layer side electrode layer 8b Substrate side electrode layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 上條 洋 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式会社内 (72)発明者 松山 秀昭 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Kamijo 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Inventor Hideaki Matsuyama 1st Tanabe Nitta, Kawasaki-ku, Kawasaki, Kanagawa No. 1 Fuji Electric Co., Ltd.

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上にAlx Gay In1-x-y N (0≦
x、y、かつx+y≦1)からなるIII 族窒化物半導体
薄膜が積層されてなり、最終のIII 族窒化物半導体薄膜
の上に電極層が形成されているIII 族窒化物半導体素子
において、前記基板と前記III 族窒化物半導体薄膜の間
には、金属導電性を示し、岩塩型または六方晶系の結晶
構造である遷移金属窒化物からなるバッファ層を介在さ
せることを特徴とするIII 族窒化物半導体半導体素子。
An Al x Ga y In 1 -xy N (0 ≦
x, y, and x + y ≦ 1), wherein the group III nitride semiconductor thin film is formed by laminating, and an electrode layer is formed on the final group III nitride semiconductor thin film. A group III nitride semiconductor layer comprising a buffer layer made of a transition metal nitride exhibiting metal conductivity and having a rock salt type or hexagonal crystal structure is interposed between the substrate and the group III nitride semiconductor thin film. Semiconductor semiconductor device.
【請求項2】前記遷移金属窒化物は窒化チタン(TiN
)、窒化バナジウム(VN)、窒化ジルコニウム(ZrN
)、窒化ニオブ(NbN )または窒化ハフニウム(HfN
)のうちのいずれかまたはこれらのうちの2つからな
る混晶、または窒化タンタル(TaN )であることを特徴
とする請求項1に記載のIII 族窒化物半導体半導体素
子。
2. The transition metal nitride is titanium nitride (TiN).
), Vanadium nitride (VN), zirconium nitride (ZrN
), Niobium nitride (NbN) or hafnium nitride (HfN
3. The group III nitride semiconductor semiconductor device according to claim 1, wherein the group III nitride semiconductor semiconductor device is a mixed crystal composed of any one of the above or two of them, or tantalum nitride (TaN).
【請求項3】前記半導体基板はケイ素、炭化ケイ素、燐
化ガリウム、ヒ化ガリウムであることを特徴とする請求
項1または2に記載のIII 族窒化物半導体素子。
3. The group III nitride semiconductor device according to claim 1, wherein said semiconductor substrate is silicon, silicon carbide, gallium phosphide, or gallium arsenide.
【請求項4】前記バッファ層と前記III 族窒化物半導体
薄膜の間に第2のバッファ層を介在させ、さらに格子不
整合緩和を行うことを特徴とする請求項1ないし3に記
載のIII 族窒化物半導体素子。
4. The group III according to claim 1, wherein a second buffer layer is interposed between the buffer layer and the group III nitride semiconductor thin film, and lattice mismatch is further alleviated. Nitride semiconductor device.
【請求項5】前記第2のバッファ層は前記III 族窒化物
半導体薄膜と同じ組成であり、かつ前記III 族窒化物半
導体薄膜の成膜時の基板温度より低い基板温度で成膜さ
れた低温成膜層であることを特徴とする請求項4に記載
のIII 族窒化物半導体素子。
5. A low-temperature layer formed at a substrate temperature lower than the substrate temperature at the time of forming the group III nitride semiconductor thin film, wherein the second buffer layer has the same composition as the group III nitride semiconductor thin film. The group III nitride semiconductor device according to claim 4, which is a film formation layer.
【請求項6】請求項5に記載のIII 族窒化物半導体素子
の製造方法において、前記低温成膜層の基板温度は25
℃以上500℃以下であることを特徴とするIII 族窒化
物半導体素子の製造方法。
6. The method for manufacturing a group III nitride semiconductor device according to claim 5, wherein the substrate temperature of said low-temperature film formation layer is 25.
A method for producing a group III nitride semiconductor device, wherein the temperature is not lower than 500C and not higher than 500C.
【請求項7】前記第2のバッファ層は前記III 族窒化物
半導体薄膜と同じ組成の薄膜、と前記バッファ層からな
る2重層の複数積層である超格子層であることを特徴と
する請求項4に記載のIII 族窒化物半導体素子。
7. The semiconductor device according to claim 1, wherein said second buffer layer is a superlattice layer comprising a plurality of stacked layers of a thin film having the same composition as said group III nitride semiconductor thin film and said buffer layer. 5. The group III nitride semiconductor device according to item 4.
【請求項8】半導体基板上にAlx Gay In1-x-y N (0≦
x、y、かつx+y≦1)からなるIII 族窒化物半導体
薄膜が積層されてなり、最終のIII 族窒化物半導体薄膜
の上に電極層が形成されているIII 族窒化物半導体素子
において、前記電極層は金属導電性を示し、岩塩型また
は六方晶系の結晶構造である遷移金属窒化物からなるこ
とを特徴とするIII 族窒化物半導体素子。
8. An Al x Ga y In 1-xy N (0 ≦
x, y, and x + y ≦ 1), wherein the group III nitride semiconductor thin film is formed by laminating, and an electrode layer is formed on the final group III nitride semiconductor thin film. A group III nitride semiconductor device, wherein the electrode layer has metal conductivity and is made of a transition metal nitride having a rock salt type or hexagonal crystal structure.
【請求項9】前記遷移金属窒化物は窒化チタン(TiN
)、窒化バナジウム(VN)、窒化ジルコニウム(ZrN
)、窒化ニオブ(NbN )、窒化ハフニウム(HfN)のう
ちのいずれかまたはこれらのうちの2つからなる混晶、
または窒化タンタル(TaN )あることを特徴とする請求
項8に記載のIII 族窒化物半導体素子。
9. The transition metal nitride is titanium nitride (TiN).
), Vanadium nitride (VN), zirconium nitride (ZrN
), Niobium nitride (NbN), hafnium nitride (HfN), or a mixed crystal consisting of two of them;
9. The group III nitride semiconductor device according to claim 8, wherein said device is tantalum nitride (TaN).
【請求項10】請求項1ないし9に記載のIII 族窒化物
半導体素子の製造方法において、前記遷移金属窒化物か
らなる層は分子線エピタキシーにより成膜されることを
特徴とするIII 族窒化物半導体素子の製造方法。
10. The method of manufacturing a group III nitride semiconductor device according to claim 1, wherein the layer made of the transition metal nitride is formed by molecular beam epitaxy. A method for manufacturing a semiconductor device.
JP12523897A 1997-05-15 1997-05-15 Group III nitride semiconductor device and method of manufacturing the same Withdrawn JPH10321954A (en)

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