JPH1032245A - Method for manufacturing semiconductor device - Google Patents

Abstract

[PROBLEMS] To prevent a short circuit with a gate electrode when a contact hole is opened and to prevent a contact failure from occurring. A gate electrode having a laminated structure of a gate oxide film, a polycrystalline silicon film, and a silicon nitride film is formed on a semiconductor substrate, and impurities are introduced using the gate electrodes as a mask. To form a common source region 6 and drain regions 7 and 7. Subsequently, the semiconductor substrate 1 is formed by a difference in the film forming speed on the surface of the silicon nitride film 4 and the surface of the semiconductor substrate 1.
A silicon nitride film 11 is formed around the gate electrodes 5 and 5 with the surface exposed, a sidewall silicon nitride film 8a is formed on the side walls of the gate electrodes 5 and 5, and then a silicon oxide film is formed on the entire surface. Then, the silicon oxide film is etched to form a contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a contact hole forming step.

[0002]

2. Description of the Related Art In recent years, with the integration of semiconductor devices, miniaturization of contact holes for connecting a semiconductor substrate and a wiring layer has been advanced. At the time of opening the contact hole, a variation in alignment is taken into consideration, so that the design size of the contact hole may become too large. Therefore, attention has been paid to the development of a self-aligned contact technology described below, which does not require a design margin for the mask, in order to align the mask with the contact hole opening.

FIGS. 6 and 7 are sectional views showing a contact hole opening step in a MOS type semiconductor memory using a conventional self-aligned contact technique in the order of steps. First, as shown in FIG. 6A, a gate oxide film 2 is formed on a semiconductor substrate 1 by a thermal oxidation method, a polycrystalline silicon film 3 having a high conductivity is formed thereon by a plasma chemical deposition method, and a gate oxide film 2 is further formed thereon. A silicon nitride film 4 is sequentially deposited by a plasma chemical vapor deposition method. Thereafter, using a predetermined mask, the laminated film composed of the gate oxide film 2, the polycrystalline silicon film 3, and the silicon nitride film 4 is selectively removed by etching.
Gate electrodes 5 and 5 are formed.

Subsequently, as shown in FIG. 6B, a common source region 6 and drain regions 7, 7 are formed in the substrate 1 by an ion implantation method using the gate electrodes 5, 5 as a mask.
To form Subsequently, a silicon nitride film 8 is deposited on the entire surface by a plasma chemical vapor deposition method.

Next, as shown in FIG. 6C, the silicon nitride layer 8 is etched by anisotropic etching (for example, RIE) so that the side wall silicon nitride is formed only on the side walls of the gate electrodes 5 and 5. The film 8a is left.

Subsequently, as shown in FIG. 7A, a silicon oxide film 9 is deposited on the entire surface by a plasma chemical vapor deposition method. Subsequently, as shown in FIG. 7B, a region not requiring etching is masked by a well-known lithography technique to form a contact hole formation region, for example, a silicon oxide film 9 on the common source region 6 into a silicon nitride film. Etching is performed under the condition of an etching selectivity of 20. When etching is performed with this selectivity, only the silicon oxide film 9 in the region where the contact is to be formed and the periphery thereof is removed, and the sidewall silicon nitride film 8a remains. As a result, a self-aligned contact hole 10 leading to the common source region 6 is formed.

In this case, since the diameter of the contact hole 10 is reduced, if the aspect ratio of the contact hole 10 is increased, the contact hole may not be completely opened due to the microloading effect. Therefore, usually, over-etching is performed for about 1.5 times the desired etching time corresponding to the thickness of the silicon oxide film 9,
Unopened contact holes are prevented.

[0008]

However, since the silicon oxide film 9 is over-etched, a part of the sidewall silicon nitride film 8a is also etched. As a result, the side surface of the polycrystalline silicon film 3 of the gate electrode 5 is exposed.
The shortcoming of the common source electrode formed so as to fill in the polysilicon film 3 occurs.

Conversely, if the etching time of the silicon oxide film 9 is shortened to prevent the common source electrode and the polycrystalline silicon film 3 from being short-circuited, the silicon oxide film 9 remains at the bottom of the contact hole. I will. Then, there is a problem that the contact resistance between the common source electrode and the common source region 6 formed in a later step increases, and a contact failure occurs, which adversely affects the reliability of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to prevent a short-circuit with a gate electrode when a contact hole is opened using the gate electrode as a mask, and that the contact hole is not formed. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of manufacturing a highly reliable semiconductor device free from defects.

[0011]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode on a semiconductor substrate; and introducing an impurity into the substrate using the gate electrode as a mask to form a diffusion region. Forming, forming a first insulating film so as to cover the gate electrode, forming a second insulating film over the entire surface, and etching and removing the second insulating film by an anisotropic etching method. Leaving the second insulating film only on the side wall of the gate electrode.

Further, the method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode on a semiconductor substrate, and a step of forming a diffusion region by introducing an impurity into the substrate using the gate electrode as a mask. Forming a first insulating film on the entire surface, etching the first insulating film by an anisotropic etching method to leave the first insulating film only on the side wall of the gate electrode, Forming a second insulating film so as to cover the gate electrode including the first insulating film.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are cross-sectional views showing the steps of manufacturing the MOS semiconductor memory according to the first embodiment of the present invention. 6 and 7 will be described with the same reference numerals.

First, as shown in FIG. 1A, a gate oxide film 2 having a thickness of about 10 nm is formed on a semiconductor substrate 1 by a thermal oxidation method, and a gate oxide film 2 having a thickness of 100 nm is formed thereon by a plasma chemical deposition method.
A polycrystalline silicon film 3 having a thickness of about 100 nm is formed thereon, and a silicon nitride film 4 having a thickness of about 100 nm is sequentially formed thereon by a plasma chemical vapor deposition method. Thereafter, using a predetermined mask, the laminated film composed of the gate oxide film 2, the polycrystalline silicon film 3, and the silicon nitride film 4 is selectively etched away to form gate electrodes 5, 5.

Subsequently, as shown in FIG. 1B, an impurity of the opposite conductivity type to the impurity contained in the substrate is ion-implanted into the substrate 1 by an ion implantation method using the gate electrodes 5 and 5 as a mask. After that, the implanted ions are activated to form the common source region 6 and the drain regions 7. Next, with the surface of the semiconductor substrate 1 exposed, a silicon nitride film 11 of about 10 nm is selectively formed so as to cover the gate electrodes 5 and 5. The formation of the silicon nitride film 11 is performed on the silicon oxide film (not shown) thinly remaining on the surface of the semiconductor substrate 1 and on the silicon nitride film 4 above the gate electrodes 5 and 5. Take advantage of the difference.
When a silicon nitride film is formed using LP-CVD (low-pressure CVD), the formation of the silicon nitride film on the silicon nitride film proceeds on the basis of nucleation during film formation. This nucleation is different in the film formation process between the silicon oxide film and the side walls of the gate electrodes 5 and 5 and the silicon nitride film 4 as the upper layer.
The film forming speed of the silicon nitride film on the silicon oxide film becomes slower than the others.

FIG. 3 is a diagram showing a difference in film forming characteristics of a silicon nitride film on a silicon nitride film (SiN) and a silicon oxide film (SiO ₂ ). That is, when the silicon nitride film is formed only on the sidewalls 5 and 5 and on the upper silicon nitride film 4, the formation of the silicon nitride film is stopped. The silicon nitride film 11 is formed utilizing this characteristic.

Next, as shown in FIG. 1C, a silicon nitride film 8 is formed on the entire surface by a plasma chemical vapor deposition method.
nm. Subsequently, as shown in FIG. 2A, the silicon nitride film 8 is etched by anisotropic etching (for example, RIE), and the sidewall silicon nitride film 8a is formed only on each side wall of the gate electrodes 5, 5. Leave.

Next, as shown in FIG. 2B, a silicon oxide film 9 serving as an interlayer insulating film is deposited on the entire surface to a thickness of 500 nm by a plasma chemical vapor deposition method. Subsequently, FIG.
As shown in (c), a region not requiring etching is masked with a photoresist by a known lithography, and a region where a contact hole is to be formed, for example, a silicon oxide film 9 above the common source region 6 is etched with a silicon nitride film. Etching is performed under the condition of a selectivity of 20 to expose the substrate 1, and a self-aligned contact hole 10 is opened.

In the first embodiment, the periphery of the gate electrodes 5 and 5 is covered with the silicon nitride film 11 and the side wall silicon nitride film 8a is present. No seam is formed, and the side wall silicon nitride film 8 between the gate electrodes 5 and 5 is not formed.
a is not so etched and is almost left. As a result, it is possible to lengthen the etching time when etching the silicon oxide film 9, and it is possible to sufficiently remove unnecessary portions of the silicon oxide film 9 by etching. Therefore, a short circuit between the common source electrode formed later and the polysilicon film 3 and the common source region 6
Contact failure between the semiconductor device and the semiconductor device is less likely to occur, and the reliability of the semiconductor device is improved.

Next, a second embodiment of the present invention will be described. FIGS. 4 and 5 are cross-sectional views showing a manufacturing process when the present invention is applied to a MOS semiconductor memory. 1 and 2 will be described with the same reference numerals.

First, as shown in FIG.
Gate electrodes 5 and 5 having a laminated structure of a gate oxide film 2, a polycrystalline silicon film 3 and a silicon nitride film 4 are patterned and formed on a semiconductor substrate 1 by the same steps as those in FIG.

Subsequently, as shown in FIG. 5B, after a common source region 6 and drain regions 7, 7 are formed by the same steps as in FIG. 1B, a silicon nitride film 8 is formed on the entire surface. accumulate.

Next, as shown in FIG. 4C, the silicon nitride layer 8 is etched by anisotropic etching to leave a sidewall silicon nitride film 8a only on the side walls of the gate electrodes 5, 5.

Subsequently, as shown in FIG. 5A, a silicon nitride film 11 of about 10 nm is selectively formed so as to cover the periphery of the gate electrodes 5 and 5 with the surface of the semiconductor substrate 1 exposed. I do. As in the first embodiment, this film forming step is performed on the silicon oxide film remaining thin on the substrate surface and the silicon nitride film on the gate electrodes 5, 5 and the side surfaces and the gate electrodes 5, 5. 4, that is, utilizing the characteristic as shown in FIG.

Next, as shown in FIG. 5B, a silicon oxide film 9 serving as an interlayer insulating film is deposited on the entire surface to a thickness of about 500 nm by, for example, a plasma chemical deposition method. Subsequently, as shown in FIG. 5C, a region not requiring etching is masked with a photoresist by well-known lithography, and a region where a contact hole is to be formed, for example, a silicon oxide film 9 on the common source region 6 is formed by silicon. Etching is performed under the condition of an etching selectivity of 20 with respect to the nitride film to expose the substrate 1, and a self-aligned contact hole 10 is opened.

In the second embodiment, the gate electrodes 5, 5 and the sidewall silicon nitride films 8 on the side surfaces thereof are formed.
Since a is covered with the silicon nitride film 11, no seam of the silicon nitride film occurs, and the sidewall silicon nitride film 8a is hardly etched. In addition, the over-etching time can be lengthened, and unnecessary portions of the silicon oxide film 9 can be sufficiently removed by etching, so that a short circuit and a contact failure with the crystalline silicon film 3 hardly occur. As a result, the reliability of the semiconductor device can be improved.

In each of the above embodiments, the silicon oxide film 9 serving as an interlayer insulating film may contain boron (BSG film), or may contain boron and phosphorus (BPSG film). When such a BSG film or a BPSG film is used, planarization is easily performed when annealing is performed in a later planarization step. Therefore, a wiring layer or the like formed in a later step is easily formed on the silicon oxide film 9, and defects such as disconnection are less likely to occur. Thereby, the reliability is further improved.

[0028]

As described above, according to the present invention, when a contact hole is opened, a highly reliable semiconductor device that does not short-circuit with a gate electrode and that does not cause contact failure is manufactured. It is possible to provide a method of manufacturing a semiconductor device which can be performed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a sectional view of a step following FIG. 1;

FIG. 3 is a characteristic diagram for explaining a method of manufacturing a semiconductor device according to the first and second embodiments of the present invention.

FIG. 4 is a sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view of a step following FIG. 4;

FIG. 6 is a sectional view showing an example of a conventional method for manufacturing a semiconductor device in the order of steps.

FIG. 7 is a sectional view of a step following FIG. 6;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate, 2 gate oxide film, 3 polycrystalline silicon film, 4 silicon nitride film, 5 gate electrode, 6 common source region, 7 drain region, 8 silicon nitride film
8a: sidewall silicon nitride film, 9: silicon oxide film, 10: self-aligned contact hole, 11: silicon nitride film.

Claims (2)

[Claims] A step of forming a gate electrode on the semiconductor substrate; a step of introducing a dopant into the substrate using the gate electrode as a mask to form a diffusion region; and a first step of covering the gate electrode. Forming an insulating film; forming a second insulating film over the entire surface; etching and removing the second insulating film by an anisotropic etching method to form the second insulating film only on the side walls of the gate electrode; A method of manufacturing a semiconductor device, comprising: 2. A step of forming a gate electrode on a semiconductor substrate; a step of introducing a dopant into the substrate using the gate electrode as a mask to form a diffusion region; and forming a first insulating film over the entire surface. A step of removing the first insulating film by an anisotropic etching method to leave the first insulating film only on the side wall of the gate electrode; and forming the gate including the first insulating film on the side wall. Forming a second insulating film so as to cover the electrodes.