JPH10326267A - Microcomputer and microcomputer test method - Google Patents

Abstract

(57) [Problem] It takes a lot of time to debug an external interrupt input of “L” level of a test pattern. SOLUTION: When "1" is written to a self-return bit 21, it is judged that a test of a WIT instruction or an STP instruction is performed, and a function of a WIT / STP control circuit unit 22 and a port control circuit unit 23 causes a WIT state. Alternatively, it is possible to use a test pattern that automatically returns from the STP state and does not require an external interrupt input of “L” level from the VLSI tester, thereby reducing the burden of debugging the test pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer which is tested in accordance with a test pattern supplied by a test apparatus, and to a microcomputer test method.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a standby control circuit of a conventional microcomputer. In the figure, reference numeral 1 denotes a flip-flop which is reset when a stop instruction (hereinafter, referred to as an STP instruction) is executed. Step 1 controls a source clock control circuit (not shown) when the STP instruction is executed. Reference numeral 2 denotes a flip-flop which is reset when a wait instruction (hereinafter, referred to as a WIT instruction) is executed.
It controls an internal clock control circuit (not shown) when executing an instruction. 3 is a flip-flop similar to the flip-flop 2, but this flip-flop 3
This controls the internal clock control circuit when the STP instruction is executed.

[0003] Reference numeral 4 denotes a watch dog timer (hereinafter, WDT).
The OR gate takes the logical sum of the reset signal and the OR signal. If either of the WDT and the reset signal is at "H" level by the OR gate 4, the flip-flop 3 is set. Reference numeral 5 denotes an AND gate that takes the logical product of the interrupt disable flag and the interrupt request signal, and 6 denotes an OR gate that takes the logical sum of the output of the AND gate 5 and the reset signal. The flip-flops 1 and 2 are set when there is an interrupt request and the interrupt is permitted.

[0004] Reference numeral 7 denotes an AND gate which takes the logical product of the outputs of the flip-flop 2 and the flip-flop 3, and 8 denotes the AND gate which takes the logical product of the output of the AND gate 7 and the internal source clock and uses it as an internal clock. FIG. 5 is a circuit diagram showing a port circuit of a conventional microcomputer. In the figure, reference numeral 11 denotes a port terminal, and 12 denotes a tristate buffer.

Next, the operation will be described. Microcomputer (hereinafter referred to as “microcomputer”) tests are performed by VLS
It is performed by an integrated circuit inspection device called an I tester. The VLSI tester has check pins corresponding to each terminal of the microcomputer, runs a program called a test pattern in various operation modes, and checks the output value of the microcomputer for the program. The test pattern is mainly a test pattern generator (hereinafter, T
PG), which is based on the logic simulation of the microcomputer. That is, each instruction execution system in the logic simulation is directly converted into a test pattern using TPG.

In FIG. 4, when an interrupt disable flag is set to enable an interrupt, that is, set to "L" level and a WIT instruction on a test pattern is executed, an internal clock is generated by a flip-flop 2 and when an STP instruction is executed,
The flip-flops 1 and 3 stop both the source clock and the internal clock. Since the interrupt disable flag is set to “L” level, if there is an external interrupt of “L” level input from the VLSI tester according to the test pattern in the WIT instruction, the flip-flop 2 is set and the operation of the internal clock is resumed W after interrupt processing
Return from the IT state. In addition, in the STP instruction, the operation of the source clock is restarted, and after waiting for oscillation stabilization by the WDT, an interrupt process is performed, and the operation returns from the STP state.

In FIG. 5, upon input from the VLSI tester, the tri-state buffer 12 is turned off, and a WIT instruction and an STP instruction are input from the port terminal 11. When outputting to the VLSI tester,
The tri-state buffer 12 is turned on, and the output value from the internal circuit is output from the port terminal 11. In the test pattern, the state of each terminal of the microcomputer during operation and the signal level to be input / output are all described. If the actual chip performs the same operation, "GO";
If any one is different from the test pattern, it is determined to be "NG".

[0008]

Since the conventional microcomputer is configured as described above, even if the microcomputer operates without any problem on the product, the VL
If the operation does not match the test pattern due to the timing shift of the external interrupt input of “L” level from the SI tester, a phenomenon of “NG” occurs. In order to avoid a problem due to this, the test pattern is usually debugged so that "NG" is not caused by a mismatch with the test pattern. However, since this debugging operation takes a lot of time, there are problems such as hindering shortening of the development period.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and automatically cancels a standby state by itself.
It is an object of the present invention to provide a microcomputer and a microcomputer test method which can reduce the load of test pattern debugging work by eliminating the need for an external interrupt input of a test pattern for canceling a standby state.

[0010]

According to a first aspect of the present invention, a microcomputer holds a specific value only when a standby instruction is tested, and sets a peripheral function in a standby state according to the standby instruction. And a standby control unit that outputs a standby state release signal when the standby instruction is issued and the specific value is held in the specific value holding unit, and when the specific value is held in the specific value holding unit. A port control unit that interrupts an external input from a port terminal and outputs an interrupt signal in response to a standby state release signal from the standby control unit, and instructs the standby control unit to return from the standby state according to the interrupt signal. And an interrupt control unit.

According to a second aspect of the present invention, there is provided a microcomputer including a delay time control unit for outputting a standby state release signal after an elapse of an arbitrary time.

According to a third aspect of the present invention, a specific value is input to a specific value holding unit from an external input of a test apparatus or a central processing unit.

According to a fourth aspect of the present invention, in the microcomputer test method, a test pattern excluding a signal indicating release from the standby state is used as a test pattern supplied to the microcomputer.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a microcomputer according to Embodiment 1 of the present invention.
11, a port terminal; and 12, a tri-state buffer. Reference numeral 21 denotes a self-recovery bit (specific value holding unit) into which "1" (specific value) is written by a central processing unit (hereinafter referred to as CPU) only when testing a WIT instruction and an STP instruction. And the peripheral functions are set to the WIT state and the STP state in accordance with the STP instruction, and when the WIT instruction or the STP instruction is executed and "1" is held in the self-return bit 21, W
A WIT / STP control circuit unit (standby control unit) that outputs an IT / STP state release signal.

Reference numeral 23 denotes a case where "1" is held in the self-recovery bit 21, that is, the external input from the port terminal 11 is cut off during the test, and the WIT / STP control circuit 22
A port control circuit unit (port control unit) that outputs an interrupt signal A in response to a WIT / STP state release signal from the CPU. It should be noted that the port control circuit section 23 simply passes a port input / output signal to / from the port terminal 11 in normal times. 24 is the port control circuit unit 23
An interrupt control circuit unit (interrupt control unit) that instructs the WIT / STP control circuit unit 22 to return from the WIT state and the STP state in response to an interrupt signal A from the CPU.

Next, the operation will be described. The test of the microcomputer is performed by an integrated circuit inspection device called a VLSI tester. The VLSI tester has check pins corresponding to each terminal of the microcomputer, runs a program called a test pattern in various operation modes, and checks the output value of the microcomputer for the program. The test pattern is mainly created by the TPG, and the source is a logic simulation of the microcomputer. That is, each instruction execution system in the logic simulation is directly converted into a test pattern using TPG.

In FIG. 1, it is assumed that the CPU writes "1" to the self-recovery bit 21 immediately before the test of the WIT instruction or the STP instruction and executes the WIT instruction or the STP instruction on the test pattern. CPU is WI
When the T instruction or STP instruction is executed, WIT / STP
The control circuit unit 22 sets each peripheral function of the microcomputer to the WIT state or the STP state. At this time, the self-return bit 21
Is written in the port control circuit unit 2
3 becomes active and shuts off the external input from the port terminal 11. The WIT / STP control circuit unit 22
Since "1" is written in the self-return bit 21,
A WIT / STP state release signal is output to the port control circuit unit 23. The port control circuit unit 23 uses the WIT / ST
WIT instruction or STP according to input of P state release signal
After the execution of the instruction, an "L" level interrupt signal A is output.

The interrupt control circuit 24 determines that the "L" level interrupt signal A is an "L" level external interrupt input, and instructs the WIT / STP control circuit 22 to return from the WIT state or the STP state. I do. After returning from the WIT state or the STP state, WIT / S
The TP control circuit unit 22 outputs a signal to the port control circuit unit 23, and the port control circuit unit 23 returns the signal output from the “L” level to the original “H” level. When "1" is not written in the self-recovery bit 21, the port control circuit unit 23 is inactive and the port terminal 11 is inactive.
Is a normal port input / output function.

As described above, according to the first embodiment, when "1" is written to the self-recovery bit 21, it is determined that the test is the WIT instruction or the STP instruction.
By automatically returning from the WIT state or the STP state by the functions of the WIT / STP control circuit section 22 and the port control circuit section 23, there is no need to input an "L" level external interrupt from a VLSI tester in the prior art. The test pattern can be used, and the burden of debugging the test pattern can be reduced.

Embodiment 2 FIG. 2 is a circuit diagram showing details of a port control circuit unit according to a second embodiment of the present invention. In the figure, reference numeral 31 denotes a WIT / STP control circuit unit 22.
A flip-flop 32 that outputs an "H" level in response to a WIT / STP state release signal from the CPU, and 32 is a clocked inverter that is activated when the self-return bit 21 holds "1". Other configurations are shown in FIG.
Since it is the same as that described above, the duplicate description is omitted.

Next, the operation will be described. In FIG. 2, immediately before the test of the WIT instruction or the STP instruction, the CP
When "1" is written to the self-return bit 21 by U, the clocked inverter 32 becomes active. Also, W
Until the WIT / STP state release signal is input from the IT / STP control circuit unit 22, the flip-flop 31 outputs the “L” level to the clocked inverter 32. Therefore, the output of the clocked inverter 32 is "H".
Has been pulled up to the level. At this point, the “H” level is output to the interrupt control circuit unit 24.

When the WIT instruction or STP instruction is executed, the WIT / STP control
Since the state release signal is output to flip-flop 31, flip-flop 31 outputs an "H" level.
Accordingly, the clocked inverter 32 changes from the “H” level to the “L” level interrupt signal A, and the interrupt control circuit 24 sends the “L” level interrupt signal A to the
Judge as "L" level external interrupt input, WIT / S
It instructs the TP control circuit unit 22 to return from the WIT state or the STP state. After returning from the WIT state or the STP state, the WIT / STP control circuit unit 22 further outputs an “L” level to the flip-flop 31, and the flip-flop 31 changes from the “L” level to the original “H” level. To the signal output of When "1" is not written in the self-recovery bit 21, the clocked inverter 32 is inactive, so that the port terminal 11 has a normal port input / output function.

As described above, according to the second embodiment, when "1" is written to the self-return bit 21, it is determined that the test is the WIT instruction or the STP instruction.
The functions of the WIT / STP control circuit 22, the flip-flop 31, and the clocked inverter 32 enable
Since the automatic return from the state or the STP state is performed, it is possible to use a test pattern which does not require the input of an “L” level external interrupt from the VLSI tester in the related art, thereby reducing the burden of debugging the test pattern. it can.

Embodiment 3 FIG. FIG. 3 is a circuit diagram showing details of a WIT / STP control circuit unit according to a third embodiment of the present invention. In the figure, reference numeral 1 denotes a flip-flop that resets when an STP instruction is executed. It controls a source clock control circuit (not shown) when executing an instruction. Reference numeral 2 denotes a flip-flop that resets when the WIT instruction is executed. The flip-flop 2 controls an internal clock control circuit (not shown) when the WIT instruction is executed. Reference numeral 3 denotes a flip-flop similar to the flip-flop 2, but the flip-flop 3 controls the internal clock control circuit when the STP instruction is executed.

An OR gate 4 takes the logical sum of the WDT and the reset signal. The OR gate 4 sets the flip-flop 3 when either the WDT or the reset signal is at "H" level. is there. 5
Is an AND gate that takes the logical product of the interrupt disable flag and the interrupt request signal, and 6 is an OR gate that takes the logical sum of the output of the AND gate 5 and the reset signal. The flip-flops 1 and 2 are set when there is an interrupt request and the interrupt is permitted. Reference numeral 7 denotes an AND gate that calculates the logical product of the outputs of the flip-flop 2 and the flip-flop 3, and reference numeral 8 denotes an AND gate that calculates the logical product of the output of the AND gate 7 and the internal source clock and uses the logical product as the internal clock. The above is the same as FIG. 4 shown as the prior art.

Reference numeral 41 denotes an OR gate which takes the logical sum of the WIT instruction and the STP instruction, and reference numeral 42 denotes an AND gate which takes the logical product of the signal from the self-return bit 21 and the output signal of the OR gate 41. 43 is a counter (delay time control unit) that counts clock sources and outputs a WIT / STP state release signal after an elapse of an arbitrary time.
3 is a selection circuit for selecting whether or not to use 3;
The PU sets “0” or “1”, and the selection circuit 4
A selection bit 46 for switching 4 is a switching circuit for switching the count source of the counter 43 to an internal clock source or an external clock source.

Next, the operation will be described. In FIG. 3, immediately before the test of the WIT instruction or the STP instruction, the CP
When the WIT instruction on the test pattern is executed with “1” written to the self-return bit 21 by U, the internal clock is output by the flip-flop 2, and when the STP instruction is executed, the source clock is output by the flip-flops 1 and 3. And the internal clock both stop. At this time, WIT
The OR gate 41 outputs an "H" level by the instruction or the STP instruction, and the "H" level is output from the AND gate 42 by the "1" of the self-return bit 21 and the "H" level output of the OR gate 41. You.

This signal becomes the WIT / STP state release signal. A return signal from the WIT state or the STP state from the interrupt control circuit unit 24 is input to the AND gate 5 as an interrupt request, and the flip-flops 1 to
Set 3 As a result, a signal is output to the internal clock control circuit and the source clock control circuit, and the microcomputer returns from the WIT state and the STP state. At the same time, the port control circuit unit 23 which has become “L” level due to the interrupt
Is returned to the “H” level, the signals from the flip-flops 1 and 2 are also transmitted to the port control circuit unit 23.

Further, if the selection bit 45 is set to "1", the signal output from the AND gate 42 when the WIT instruction or the STP instruction is executed
4 and is input to the counter 43. Since the counter 43 can be set to an arbitrary value, at the time of a WIT instruction, the internal clock source is selected by the switching circuit 46 to count down, and the overflow signal is output to the port control circuit unit 2.
Output to 3. As a result, it is possible to return after an arbitrary time from the execution of the WIT instruction. When the STP instruction is executed, all the internal clocks are stopped, so that the counter 43 can be used by selecting an external clock source by the switching circuit 46.

As described above, according to the third embodiment, by setting the counter 43 to an arbitrary value, W
It is possible to return after an arbitrary time from the execution of the IT instruction or the STP instruction, and this is effective in a program for checking the port output value during the WIT instruction or the STP instruction. In the first to third embodiments, C
Although "1" is written to the self-return bit 21 by the PU, the external input of the VLSI tester (test device)
A specific voltage level (for example, twice the VCC level) may be input to an arbitrary terminal, and “1” may be written to the self-recovery bit 21.

[0031]

As described above, according to the first aspect of the present invention, a specific value holding unit that holds a specific value only when a standby instruction is tested, and a peripheral function is set to a standby state according to the standby instruction. A standby control unit for outputting a standby state release signal when the standby instruction is issued and the specific value is held in the specific value holding unit; and a port when the specific value is held in the specific value holding unit. A port control unit that shuts off external input from the terminal and outputs an interrupt signal in response to a standby state release signal from the standby control unit, and an interrupt that instructs the standby control unit to return from the standby state in response to the interrupt signal Since the control unit and the control unit are provided, it is possible to use a test pattern which does not require an external interrupt input in the related art, and has an effect of reducing a load of a test pattern debugging operation.

According to the second aspect of the present invention, since the delay time control section for outputting the standby state release signal after an elapse of an arbitrary time is provided, the delay time control section can be set to an arbitrary value. It is possible to return from the standby state after an arbitrary time, and it is possible to check the port output value during the standby state.

According to the third aspect of the present invention, the specific value is input from the external input of the test apparatus or the central processing unit to the specific value holding unit. There is an effect that can be input from outside or inside.

According to the fourth aspect of the present invention, since the test pattern supplied to the microcomputer is configured to use the test pattern excluding the signal indicating the release from the standby state, the burden of debugging the test pattern is reduced. There is an effect that can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of a port control circuit unit according to a second embodiment of the present invention.

FIG. 3 is a WIT / ST according to a third embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating details of a P control circuit unit.

FIG. 4 is a circuit diagram showing a standby control circuit of a conventional microcomputer.

FIG. 5 is a circuit diagram showing a port circuit of a conventional microcomputer.

[Explanation of symbols]

21 Self-return bit (specific value holding unit), 22 WIT
/ STP control circuit section (standby control section), 23 port control circuit section (port control section), 24 interrupt control circuit section (interrupt control section), 43 counter (delay time control section).

Claims (4)

[Claims] A specific value holding unit for holding a specific value only at the time of a test of a standby instruction, a peripheral function being put into a standby state in response to the standby instruction, the standby instruction being issued, and the specific value holding unit being A standby control unit that outputs a standby state release signal when a specific value is held, and an external input from a port terminal when the specific value is held in the specific value holding unit, and the standby control unit A port control unit that outputs an interrupt signal in response to a standby state release signal from the CPU, and an interrupt control unit that instructs the standby control unit to return from the standby state in response to an interrupt signal from the port control unit. Microcomputer. 2. The microcomputer according to claim 1, further comprising a delay time control unit that outputs a standby state release signal after an elapse of an arbitrary time. 3. The microcomputer according to claim 1, wherein a specific value is input to a specific value holding unit from an external input of the test apparatus or a central processing unit. 4. The microcomputer according to claim 1, wherein a test pattern excluding a signal indicating release from a standby state is used as a test pattern supplied to the microcomputer according to any one of claims 1 to 3. Computer testing method.