JPH10326868A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of a malfunction of a semiconductor device by a method, wherein high-frequency cutting circuits are formed within a semiconductor integrated circuit element, and electrostatic noise generated in signal lines such as clocks is reduced by the high-frequency noise cutting circuits. SOLUTION: A resistor 31 is connected with a power line, a resistor 32 is connected with a ground line, and a capacitor 1 is connected between the power and the ground lines, which are respectively located on the sides of the loads of those resistors, to form a high-frequency noise-cutting circuit. An element 33 on an LSI is formed in parallel with the capacitor 1 of this cutting circuit. Moreover, a capacitor 1 is formed between a power and the ground lines, a resistor 41 is connected with the power line on the side of the load of the resistor 41, a resistor 42 is connected with the earth line on the side of the load of the resistor 42 to form a high-frequency noise-cutting circuit. An element 43 on an LSI is formed between the power and the ground lines, which are respectively located on the sides of the loads of the resistors 41 and 42. Then such a way, an electrostatic noise generated on signal lines such as clocks, is reduced by the high-frequency noise-cutting circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an LSI structure and a circuit configuration for preventing a malfunction caused by electrostatic noise in an LSI used for a portable device or the like.

[0002]

2. Description of the Related Art Generally, a signal noise that enters a signal line is removed by providing a low-pass filter (hereinafter, referred to as an LPF) for noise cutting or a noise removing circuit using a flip-flop. Was like that.

[0003]

However, in the above-mentioned conventional method, the voltage fluctuation of the LSI substrate due to the static electricity noise causes the voltage fluctuation to be non-uniform.
It has been difficult to remove the effects of high frequency noise generated inside. At present, sufficient measures have not been taken against power supply noise generated in the power supply line itself.

Further, there is no measure against electromagnetic noise. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above problems and to provide a semiconductor device incorporating a circuit configuration and an LSI structure for preventing a malfunction of the semiconductor device caused by electrostatic noise.

[0005]

In order to achieve the above object, the present invention provides: [1] a high frequency noise cut circuit comprising a capacitor and a resistor formed in a semiconductor integrated circuit element; The circuit reduces electrostatic noise generated in a signal line such as a clock.

[2] The semiconductor device according to [1], wherein the high-frequency noise cut circuit is formed near a pad of a power supply line. [3] The semiconductor device according to [1] or [2], wherein a capacitor is formed at a power supply line entrance of a functional block of a circuit formed in the semiconductor integrated circuit element.

[4] In the semiconductor device according to the above [1], [2] or [3], the capacitor is connected to a pair of signal lines or power lines (that is, a pair of signal lines or power lines) existing through an oxide film in a semiconductor integrated circuit element. Metal-metal metal-polycrystalline silicon (polycrystalline silicon-polycrystalline silicon combination). [5] The semiconductor device according to [1] or [2], wherein the resistor is formed of metal or polycrystalline silicon routed inside the semiconductor integrated circuit element.

[6] The surface of the semiconductor chip is covered with metal or polycrystalline silicon.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an explanatory diagram of a first circuit configuration incorporated in a semiconductor device according to a first embodiment of the present invention. As shown in this figure, a high-frequency noise cut circuit comprising a resistor 2 connected to a pad 3 of a semiconductor device and a capacitor 1 connected to a load side of the resistor 2 and connected to a ground 4 is formed. ing. Note that since the resistor 2 has a resistance component due to the routing of the signal and the power supply line, it is not necessary to make it as a resistance element again.

This embodiment is particularly applied as a countermeasure circuit for a signal line susceptible to noise, such as a test signal, among signals input from a pad and routed inside the semiconductor device. FIG. 2 is an explanatory diagram of a second circuit configuration incorporated in the semiconductor device according to the first embodiment of the present invention.

In this embodiment, the configuration of a high-frequency noise cut circuit is the same as that of the first embodiment, but the high-frequency noise cut circuit is connected to an internal signal generating circuit 5 for a signal line running inside the semiconductor device. Applied as a countermeasure circuit. Note that since the resistor 2 has a resistance component due to the routing of the signal line, it is not necessary to make it as a resistance element again.

FIG. 3 is an explanatory diagram of a third circuit configuration incorporated in a semiconductor device according to a second embodiment of the present invention. FIG.
1A, a power supply _VDD pad 11 and a ground GND pad 12 are provided in a semiconductor device (LSI) 10. The capacitor 1 is connected between these pads 11 and 12, and the LSI internal element 15 has Resistor 13 for power line
Then, the resistor 14 is connected to the ground line.

In FIG. 3B, the semiconductor device (LS)
Power supply V _DD pad 21 to I) 20, the ground GND pad 22 is provided, resistance to the power supply V _DD pad 21 23
The resistor 24 is connected to the ground GND pad 22, and the capacitor 1 is connected between the power line on the load side and the ground line. 25 is LS
I internal element.

FIG. 4 is an explanatory diagram of a fourth circuit configuration incorporated in a semiconductor device according to a third embodiment of the present invention. Hereinafter, in each embodiment, in the case of polycrystalline silicon,
Polysilicon such as polysilicon and polycide or a compound (reactant) with polysilicon is generally referred to.

In FIG. 4A, a resistor 31 is connected to a power supply line, a resistor 32 is connected to an earth line, and a capacitor 1 is connected between the power supply line on the load side and the earth line. The element 33 on the LSI is formed on the side in parallel with the capacitor 1. In FIG. 4B, a capacitor 1 is formed between the power supply line and the ground line, a resistor 41 is connected to the load side power supply line, and a resistor 42 is connected to the ground line. The element 43 on the LSI is formed.

In the third and fourth embodiments, the high-frequency noise cut circuit is connected to the power supply circuit, and is applied as a countermeasure circuit for the power supply. Since the resistance has a resistance component due to the routing of the signal and the power supply line from the beginning, it is not necessary to make it as a resistance element again. With the above configuration, when voltage fluctuation occurs inside the LSI due to the influence of electrostatic noise, the noise peak of a signal that may cause an internal malfunction can be reduced by the capacitor and the resistor. , Malfunction can be prevented.

As for the clock, high-frequency noises on the oscillation waveform can be reduced. In addition, LSI
Noise applied to the power supply terminal due to external voltage fluctuation can also be reduced by a capacitor and a resistor arranged near the power supply pad.

As in the case of the signal line, the peak of the noise between power sources generated inside can be reduced by a capacitor and a resistor arranged inside the LSI. Next, as a specific example of the structure of the high-frequency noise cut-off circuit incorporated in the above-described semiconductor device, an LSI is formed by multilayering a metal layer (metal layer) or a polycrystalline silicon layer used as a signal line or a power supply line. A sixth embodiment that covers elements and signal lines or has a sandwich structure will be described.

The details will be described below. FIG. 5 is a cross-sectional view of a transistor covered with a multi-layer metal or a multi-layer crystalline silicon layer according to an embodiment of the present invention. In this figure, 51 is a semiconductor substrate (LSI substrate), 52 and 53 are source / drain, 54 and 55 are oxide films, 56 is a gate (polycrystalline silicon), 57 is a first layer metal, and source / drain 52 , 53 and a gate 56 respectively. The oxide film 5 is formed on the first layer metal 57.
8 and a second-layer metal or second-layer polycrystalline silicon 59 is further formed thereon.

Therefore, between the first layer metal 57 and the second layer metal or the second layer polycrystalline silicon 59, that is, between the source line 57A, the second layer metal or the second layer polycrystalline silicon 59, and the gate line 57B. Capacitors C can be formed between the second-layer metal or second-layer polycrystalline silicon 59 and the drain wiring 57C and the second-layer metal or second-layer polycrystalline silicon 59, respectively. The respective capacitors make it possible to equalize potential fluctuations due to static electricity noise.

FIG. 6 is a schematic diagram of a signal line incorporating a capacitor according to an embodiment of the present invention. In FIG. 6A, an oxide film 62 is formed on a semiconductor substrate (LSI substrate) 61, and a signal line 63, an oxide film 64, and a second polycrystalline silicon or metal 65 are sequentially formed thereon. The capacitor C ₁ is formed between the LSI substrate 61 and the signal line 63, and the capacitor C ₂ is formed between the signal line 63 and the second polycrystalline silicon or the second layer metal 65.

In FIG. 6B, polycrystalline silicon or metal 73 is formed above a signal line 71 via an oxide film 72.
The polycrystalline silicon or metal 75 is formed below the signal line 71 via the oxide film 74.
Therefore, a capacitor C ₃ is provided between the signal line 71 and the polysilicon or metal 73, and a capacitor C ₄ is provided between the signal line 71 and the polysilicon or metal 75.
Can be formed.

As described above, in this embodiment, polycrystalline silicon or metal used as a signal line or a power supply line is covered with another polycrystalline silicon or metal. Alternatively, a capacitor is formed by forming a sandwich structure using another polycrystalline silicon or metal. 7 to 10
FIG. 14 is a diagram showing an example in which the entire LSI chip of the sixth embodiment of the present invention is covered with metal or polycrystalline silicon.

As shown in FIG. 7, a multi-layered polycrystalline silicon layer or metal layer 81 is arranged at the center of an LSI chip 80, and pads 82 are arranged at the periphery of the LSI chip 80. I have. Also, as shown in FIG.
A multi-layered polycrystalline silicon layer or metal layer 83 formed in a fence shape is arranged at the center of the LSI chip 80, and LS
The pad 84 is arranged around the periphery of the I chip 80.

Further, as shown in FIG. 9, a multi-layered polycrystalline silicon layer or metal layer 85 formed in a lattice shape and arranged in the center of the LSI chip 80 is formed.
The pad 86 is arranged around the periphery of the.
Further, as shown in FIG. 10, a multi-layered polycrystalline silicon layer or metal layer 87 formed on a designated area such as a functional block or a signal wiring region is arranged at the center of the LSI chip 80, and Pad 88 around 80
Are arranged.

The above-mentioned polycrystalline silicon layer or metal layer is fixed to an LSI substrate ( _VDD or GND) or is in a floating state. Normally, the LSI chip 80
LSI chip 80 due to static noise generated outside
When a voltage fluctuation occurs in the LSI, the LSI substrate causes a voltage fluctuation. According to the present invention, a transistor is formed by forming a multi-layered polysilicon layer or a metal layer formed on an LSI chip 80 and a transistor. Since there is a capacitance (capacitor) between the signal line, the power supply line, and the gate, the voltage fluctuates while the internal state is maintained.

As a result, the potential between V _{DD and} GND of the LSI is kept uniform inside the LSI chip 80, and a malfunction hardly occurs. Electromagnetic noise that enters the LSI is absorbed by the multi-layered polysilicon layer or metal layer that covers the LSI. Regarding the capacitive dielectric property, even if the multilayered polycrystalline silicon layer or metal layer covering the LSI has a capacitive / dielectric property, the state of the underlying LSI is maintained as described above. Therefore, malfunction becomes difficult.

As described above, by using the multi-layered polycrystalline silicon layer or metal layer to cover the elements of the LSI, these polycrystalline silicon layer or metal layer and each element / signal line / power supply line of the LSI are covered. Due to the presence of the capacitor between the internal state and the internal state, even if a voltage fluctuation due to static electricity noise occurs, the internal state is maintained and an effect of preventing malfunction is obtained.

Further, even if the capacitance / dielectric noise varies between the multi-layered polycrystalline silicon layer or metal layer covering the surface, the state is uniform on the LSI underneath. And does not malfunction. In addition, the electromagnetic noise is absorbed by the surface, so that the lower LSI is not affected.

As described above, the resistance due to static electricity noise can be improved. It should be noted that the present invention is not limited to the above embodiments, and various modifications are possible based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0031]

As described above in detail, according to the present invention, by incorporating a capacitor for cutting high-frequency noise and a resistor as necessary inside the LSI, voltage fluctuation caused by static electricity noise and LSI Noise generated in a signal line, a clock line, a power supply line, and the like due to uneven voltage fluctuations inside can be reduced, and malfunction can be prevented.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first circuit configuration incorporated in a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a second circuit configuration incorporated in the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a third circuit configuration incorporated in a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a fourth circuit configuration incorporated in a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a cross-sectional view of a transistor covered with a multi-layered metal or a multi-layered crystalline silicon layer according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a signal line incorporating a capacitor according to an embodiment of the present invention.

FIG. 7 is a diagram (part 1) illustrating an example in which a capacitance (capacitor) is provided to the entire LSI chip according to a sixth embodiment of the present invention;

FIG. 8 is a diagram (part 2) illustrating an example in which a capacitance (capacitor) is provided to the entire LSI chip according to a sixth embodiment of the present invention.

FIG. 9 is a diagram (part 3) illustrating an example in which a capacitance (capacitor) is provided to the entire LSI chip according to the sixth embodiment of the present invention;

FIG. 10 is a diagram (part 4) illustrating an example in which the entire LSI chip according to the sixth embodiment of the present invention has a capacitance (capacitor).

[Explanation of symbols]

1 capacitor 2,13,14,23,24,31,32,41,42
Resistor 3, 82, 84, 86, 88 Pad 4 Ground 5 Internal signal generation circuit 10, 20 Semiconductor device (LSI) 11, 21 Power supply V _DD pad 12, 22 Ground GND pad 15, 25 LSI internal element 33, 43 On LSI Element 51, 61 Semiconductor substrate (LSI substrate) 52, 53 Source / drain 54, 55, 58, 62, 64, 72, 74 Oxide film 56 Gate (polycrystalline silicon) 57 First layer metal 57A Source wiring 57B Gate Wiring 57C drain wiring 59 second-layer metal or second-layer polycrystalline silicon 63, 71 signal line 65, 73, 75 polycrystalline silicon or metal 80 LSI chip 81, 83, 85, 87 multi-layered polycrystalline silicon Layer or metal layer

Claims (6)

[Claims] 1. A high frequency noise cut circuit comprising a capacitor and a resistor formed in a semiconductor integrated circuit element is formed, and the high frequency noise cut circuit reduces electrostatic noise generated on a signal line such as a clock. Semiconductor device. 2. The semiconductor device according to claim 1, wherein said high-frequency noise cut circuit is formed near a pad of a power supply line. 3. The semiconductor device according to claim 1, wherein a capacitor is formed at a power supply line entrance of a functional block of a circuit formed in the semiconductor integrated circuit element. 4. The semiconductor device according to claim 1, wherein said capacitor is formed by a pair of signal lines or power lines existing through an oxide film in the semiconductor integrated circuit element. Semiconductor device. 5. The semiconductor device according to claim 1, wherein said resistor is formed of metal or polycrystalline silicon routed inside a semiconductor integrated circuit element. 6. A semiconductor device, wherein a transistor, a signal line, a power supply line, and the like which constitute an LSI are covered with metal or polycrystalline silicon.