JPH0322470A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0322470A JPH0322470A JP15771489A JP15771489A JPH0322470A JP H0322470 A JPH0322470 A JP H0322470A JP 15771489 A JP15771489 A JP 15771489A JP 15771489 A JP15771489 A JP 15771489A JP H0322470 A JPH0322470 A JP H0322470A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- metal layer
- power source
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000010408 film Substances 0.000 abstract description 17
- 239000010409 thin film Substances 0.000 abstract description 4
- 230000007257 malfunction Effects 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910007277 Si3 N4 Inorganic materials 0.000 description 1
- -1 Ta20 Inorganic materials 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路に関し、特に電源雑音吸収用
のコンデンサを内蔵する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit incorporating a capacitor for absorbing power supply noise.
第２図（ａ）は、従来例を示す半導体チップの平面模式
図、第２図（ｂ）は第２図（ａ）のＡＡ線断面図である
。FIG. 2(a) is a schematic plan view of a semiconductor chip showing a conventional example, and FIG. 2(b) is a sectional view taken along the line AA in FIG. 2(a).
従来の半導体集積回路の電源雑音吸収用のコンデンサは
、拡散層容量あるいはゲート酸化膜容量を用いていたが
、要領を形成するため大きな面積が必要とし、十分大き
な容量のコンデンサを設けることができないため、雑音
吸収の効果が低かった。Conventional capacitors for absorbing power supply noise in semiconductor integrated circuits use diffusion layer capacitance or gate oxide film capacitance, but this requires a large area to form the capacitance, and it is not possible to provide a capacitor with a sufficiently large capacitance. , the noise absorption effect was low.
前述した従来の半導体集積回路においては、電源雑音吸
収用のコンデンサを内蔵させる場合、拡散層容量やゲー
ト酸化膜容量を使用していたので十分大きな容量をもた
せることができないため、外部あるいは内部で発生した
電源雑音によって誤動作を引き起こすことがある。これ
を防ぐため外付けコンデンサを使用すると、回路基板へ
の実装密度が低下する。In the conventional semiconductor integrated circuits mentioned above, when incorporating a capacitor for absorbing power supply noise, diffusion layer capacitance and gate oxide film capacitance are used, which makes it impossible to provide a sufficiently large capacitance. Power supply noise may cause malfunction. If an external capacitor is used to prevent this, the mounting density on the circuit board will be reduced.
本発明の目的は集積度を低下させることなく又電源雑音
吸収用の外付けコンデンサを必要としない半導体集積回
路を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit that does not require a reduction in the degree of integration and does not require an external capacitor for absorbing power supply noise.
本発明の半導体集積回路は、半導体チップの絶縁膜上に
、電源（又は接地）端子に接続された第１の金属層、誘
電体層及び接地（又は電源）端子に接続された第２の金
属層がらなる電源雑音吸収用のコンデンサを設けたとい
うものである。The semiconductor integrated circuit of the present invention includes, on an insulating film of a semiconductor chip, a first metal layer connected to a power (or ground) terminal, a dielectric layer, and a second metal layer connected to the ground (or power) terminal. A layered capacitor was installed to absorb power supply noise.
次に本発明について、図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）は、本発明の一実施例を示す半導体チップ
の平面模式図、第１図（ｂ）は第１図（ａ＞のＡ−Ａ線
断面図である。FIG. 1(a) is a schematic plan view of a semiconductor chip showing an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along the line A--A in FIG. 1(a).
半導体チップのカバー絶縁膜上に第１の金属層９、誘電
体層ｌＯ、第２の金属層ｌ１がらなるコンデンサを形威
し、その上を他のカバー絶縁膜１２で被覆してある。ま
た、第１の金属層つと接続されている電源パッド６、第
２の金属層１１と接続されている接地パッド７を介して
外部電源と接続される。A capacitor consisting of a first metal layer 9, a dielectric layer lO, and a second metal layer l1 is formed on the cover insulating film of the semiconductor chip, and is covered with another cover insulating film 12. Further, it is connected to an external power source via a power supply pad 6 connected to the first metal layer and a ground pad 7 connected to the second metal layer 11.
誘電体層の材質としては、Ｓｉｎ，Ｓｉ０２ ，Ｓｉ３
Ｎ４ ，Ｔａ２ ０，，Ｔｉ０２などを用いることが
できる。特にＴａ２０５薄膜は、反応性スパッタリング
法やＴａ膜の陽極酸化により比誘電率の高いものを形戒
でき、膜厚２００ＯＡで０．１μＦ ／ ｃ ｍ ２程
度の大きな静電容量が得られる。第１，第２の金属層と
してはＴａ膜やＭｏ膜を使用すればよい。The material of the dielectric layer is Sin, Si02, Si3
N4, Ta20, Ti02, etc. can be used. In particular, the Ta205 thin film can be made to have a high dielectric constant by reactive sputtering or anodization of the Ta film, and a large capacitance of about 0.1 μF/cm 2 can be obtained with a film thickness of 200 OA. A Ta film or a Mo film may be used as the first and second metal layers.
以上の構造を持つことにより、内部あるいは外部で発生
した電源雑音をこのコンデンザで吸収させることができ
る。また、このコンデンサは、半導体チップの絶縁膜上
に設けた薄膜コンデンサであり集積度を低下させず雑音
吸収に十分な容量のコンデンサを形或することができる
。With the above structure, power supply noise generated internally or externally can be absorbed by this capacitor. Further, this capacitor is a thin film capacitor provided on an insulating film of a semiconductor chip, and a capacitor having a sufficient capacity for noise absorption can be formed without reducing the degree of integration.
以上説明したように本発明は、電源雑音吸収用のコンデ
ンサを半導体チップの絶縁膜上に薄膜コンデンサとして
設けることにより、集積密度を低下させずに電源雑音に
よる誤動作のない半導体集積回路がえられる。又、電源
雑音吸収用のコンデンサを外付けする必要がないため、
回路基板への実装密度を向上させることができるという
効果がある。As described above, the present invention provides a capacitor for absorbing power supply noise as a thin film capacitor on the insulating film of a semiconductor chip, thereby providing a semiconductor integrated circuit that does not malfunction due to power supply noise without reducing the integration density. In addition, there is no need to attach an external capacitor for absorbing power supply noise.
This has the effect of improving the packaging density on the circuit board.
第１図（ａ）は、本発明の一実施例を示す半導体チップ
の平面模式図、第１図（ｂ）は第１図（ａ〉のＡ−Ａ線
断面図、第２図（ａ）は、従来例を示す半導体チップの
平面模式図、第２図（ｂ）は第２図（ａ）のＡ−Ａ線断
面図である。
１・・・ｐ型半導体基板、２・・・ｐ＋拡散層、３・・
・ｎウェル、４・・・ｎ＋拡散層、５・・・酸化シリコ
ン膜、６・・・電源パッド、７・・・接地パッド、８・
・・カバー絶縁膜、９・・・第１の金属層、１ｏ・・・
誘電体層、１１・・・第２の金属層、１２・・・他のカ
バー絶縁膜。FIG. 1(a) is a schematic plan view of a semiconductor chip showing an embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-A in FIG. 1(a), and FIG. 2(a) is a schematic plan view of a semiconductor chip showing a conventional example, and FIG. 2(b) is a cross-sectional view taken along the line A-A in FIG. 2(a). 1...p-type semiconductor substrate, 2...p+ Diffusion layer, 3...
・n well, 4...n+ diffusion layer, 5...silicon oxide film, 6...power supply pad, 7...ground pad, 8.
...Cover insulating film, 9...First metal layer, 1o...
Dielectric layer, 11... second metal layer, 12... other cover insulating film.
Claims (1)
続された第１の金属層、誘電体層及び接地（又は電源）
端子に接続された第２の金属層からなる電源雑音吸収用
のコンデンサを設けたことを特徴とする半導体集積回路
。A first metal layer, a dielectric layer, and a ground (or power source) connected to a power (or ground) terminal on the insulating film of the semiconductor chip.
1. A semiconductor integrated circuit comprising a power supply noise absorbing capacitor made of a second metal layer connected to a terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15771489A JPH0322470A (en) | 1989-06-19 | 1989-06-19 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15771489A JPH0322470A (en) | 1989-06-19 | 1989-06-19 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0322470A true JPH0322470A (en) | 1991-01-30 |
Family
ID=15655773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15771489A Pending JPH0322470A (en) | 1989-06-19 | 1989-06-19 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0322470A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05326838A (en) * | 1992-04-08 | 1993-12-10 | Nec Corp | Semiconductor device |
| US5633785A (en) * | 1994-12-30 | 1997-05-27 | University Of Southern California | Integrated circuit component package with integral passive component |
| JP2007095965A (en) * | 2005-09-28 | 2007-04-12 | Technology Alliance Group Inc | Semiconductor device and bypass capacitor module |
| US8299518B2 (en) | 2008-03-17 | 2012-10-30 | Liquid Design Systems Inc. | Semiconductor device and bypass capacitor module |
-
1989
- 1989-06-19 JP JP15771489A patent/JPH0322470A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05326838A (en) * | 1992-04-08 | 1993-12-10 | Nec Corp | Semiconductor device |
| US5633785A (en) * | 1994-12-30 | 1997-05-27 | University Of Southern California | Integrated circuit component package with integral passive component |
| JP2007095965A (en) * | 2005-09-28 | 2007-04-12 | Technology Alliance Group Inc | Semiconductor device and bypass capacitor module |
| US8299518B2 (en) | 2008-03-17 | 2012-10-30 | Liquid Design Systems Inc. | Semiconductor device and bypass capacitor module |
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