JPH1041621A - Tin-bismuth solder joining method - Google Patents
Tin-bismuth solder joining methodInfo
- Publication number
- JPH1041621A JPH1041621A JP8189546A JP18954696A JPH1041621A JP H1041621 A JPH1041621 A JP H1041621A JP 8189546 A JP8189546 A JP 8189546A JP 18954696 A JP18954696 A JP 18954696A JP H1041621 A JPH1041621 A JP H1041621A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- tin
- circuit board
- bismuth
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing of the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3465—Application of solder
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】
【課題】 本発明は、ＬＳＩ素子および電子機器中の
はんだ材料や接合用電極材料、またはんだにより回路基
板に表面実装する際に重要な役割を果たす電極接合部表
面の被覆処理に関し、Ｓｎ−Ｂｉはんだの接着強度を増
す接着方法を得る。
【解決手段】 回路基板上のはんだ付け部にあらかじ
め銀添加膜を形成し、次いではんだ付け部に電子部品を
Ｓｎ−Ｂｉはんだで接合する。はんだ付け部をニッケル
または銅の膜で形成し、その表面に５μｍを超えない厚
さの銀添加膜を形成する。また、Ｓｎを４０〜５０Ｗｔ
％、Ｂｉを４０〜７０Ｗｔ％を含む錫−ビスマスはんだ
を用いて電子部品を回路基板にはんだ付けする際、該回
路基板上のはんだ付け部の表面被覆材に少なくともビス
マスが５０Ｗｔ％を超える錫−ビスマスはんだを用い
る。
PROBLEM TO BE SOLVED: To provide a coating for a surface of an electrode joint portion which plays an important role when a surface material is mounted on a solder material or a bonding electrode material in an LSI element or an electronic device or a circuit board. Regarding the treatment, a bonding method for increasing the bonding strength of the Sn-Bi solder is obtained. SOLUTION: A silver-added film is formed in advance on a soldered portion on a circuit board, and then the electronic component is joined to the soldered portion with Sn-Bi solder. The soldered portion is formed of a nickel or copper film, and a silver-added film having a thickness not exceeding 5 μm is formed on the surface. Further, Sn is set to 40 to 50 Wt.
%, When the electronic component is soldered to the circuit board using a tin-bismuth solder containing 40 to 70 Wt% of Bi, the surface covering material of the soldering portion on the circuit board has at least 50% by weight of tin-bismuth over 50 wt%. Use bismuth solder.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＬＳＩ素子および
電子機器中のはんだ材料や接合用電極材料、またはんだ
により回路基板に表面実装する際に重要な役割を果たす
電極接合部表面の被覆処理に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for coating a surface of an electrode joint portion, which plays an important role in the surface mounting of a solder material or a bonding electrode material in an LSI device or an electronic device or a circuit board. .
【０００２】電子機器等の部品ははんだによって接合さ
れる部分が大多数を占める。一般的にはんだというと錫
−鉛（Ｐｂ）の合金が知られ、上記の各種実装方式の接
合材料としても使用されている。2. Description of the Related Art Most parts such as electronic devices are joined by solder. Generally, a solder is known as a tin-lead (Pb) alloy, and is also used as a bonding material in the above various mounting methods.
【０００３】[0003]
【従来の技術】従来技術では、例えば、ＤＩＰ方式、Ｑ
ＦＰ方式、ＬＣＣ方式の実装においては、Ｓｎ−６３Ｗ
ｔ％Ｐｂという共晶組成の融点１８３℃のはんだを用い
て、約２２０℃程度の温度を加えることによって、電子
部品等の端子（リード）、または電極をプリント基板等
の回路基板上の銅（Ｃｕ）電極パッドに接合している。2. Description of the Related Art In the prior art, for example, a DIP method, a Q
In implementation of FP system and LCC system, Sn-63W
By using a solder having a melting point of 183 ° C. having a eutectic composition of t% Pb and applying a temperature of about 220 ° C., a terminal (lead) of an electronic component or the like or an electrode is formed of copper (C) on a circuit board such as a printed board. Cu) bonded to the electrode pad.
【０００４】しかし、Ｓｎ−Ｐｂ系はんだでは、溶融す
る最も低い温度がＳｎ−３７Ｗｔ％Ｐｂの１８３℃であ
り、はんだ接合には２１０〜２２０℃程度の温度が必要
となり、耐熱性の低い部品をリフローで一括接合するこ
とができないなどのことから実装温度の低温化に対応で
きるはんだが注目されている。[0004] However, in the case of Sn-Pb solder, the lowest melting temperature is 183 ° C of Sn-37Wt% Pb, and a temperature of about 210 to 220 ° C is required for solder joining. Attention has been focused on solders that can cope with lower mounting temperatures because they cannot be joined together by reflow.
【０００５】また、最近は環境汚染という観点からも、
エレクトロニクス用はんだに含まれるＰｂを規制しよう
という動きが国際的にく活発化している。この動きに対
応して、Ｐｂを含まないはんだ、いわゆるＰｂフリーは
んだの開発が盛んになっている。[0005] Recently, from the viewpoint of environmental pollution,
The movement to regulate Pb contained in solder for electronics is becoming increasingly active internationally. In response to this movement, the development of Pb-free solders, so-called Pb-free solders, has been active.
【０００６】現在、開発が進められているＰｂフリーは
んだ合金は、Ｂｉ−４３Ｓｎ（融点：１３９℃）：Ｓｎ
−３．５Ａｇ（融点：２２１℃）などのＳｎ系の共晶は
んだ合金をベースとして、融点の調整、機械的性質の改
善のために、少量の第三、第四の元素を添加したもので
ある。開発のポイントは、Ｓｎ−３７Ｐｂと同等の接合
性、作業性を持ち、且つＰｂその他の有害元素を含まな
いことである。The Pb-free solder alloy currently under development is Bi-43Sn (melting point: 139 ° C.): Sn
Based on Sn-based eutectic solder alloy such as -3.5Ag (melting point: 221 ° C), a small amount of third and fourth elements are added for adjusting melting point and improving mechanical properties. is there. The point of development is that it has the same bonding properties and workability as Sn-37Pb, and does not contain Pb or other harmful elements.
【０００７】従来は、Ｓｎ−Ｐｂ系はんだに代わる低温
はんだとして、Ｓｎ−５２Ｉｎ（融点１１７℃）、Ｓｎ
−５８Ｂｉ（融点１３９℃）等が知られている。低温接
合、Ｐｂフリー化という観点から、Ｓｎ−Ｂｉはんだが
注目されている。Ｓｎ−ＢｉはんだというのはＳｎが２
０〜６５Ｗｔ％で残部がＢｉである合金、および微量
（１〜３％）の範囲の銀（Ａｇ）、亜鉛（Ｚｎ）、ゲル
マニウム（Ｇｅ）、銅（Ｃｕ）、アンチモン（Ｓｂ）、
インジウム（Ｉｎ）等を含んだ合金のことをいう。Conventionally, Sn-52In (melting point 117 ° C.), Sn-52In
-58 Bi (melting point: 139 ° C.) and the like are known. From the viewpoint of low-temperature bonding and Pb-free, Sn-Bi solder has been attracting attention. Sn-Bi solder means that Sn is 2
Alloys of 0 to 65 Wt% with the balance being Bi, and a small amount (1 to 3%) of silver (Ag), zinc (Zn), germanium (Ge), copper (Cu), antimony (Sb),
An alloy containing indium (In) or the like.
【０００８】はんだ接合においては接合信頼性が重要な
ポイントとなるため、機械的形質の優れた材料であるこ
と、接合強度が大きいことの二つが重要になる。ここで
加えた第三元素は、はんだの性質を補うために添加す
る。例えば、Ｓｎ−５８ＢｉはＢｉの脆さからくる接合
信頼性への懸念があるが、Ａｇを加えることで、機械的
性質を改善出来ることが知られている。とが知られてい
る。[0008] In solder joining, joining reliability is an important point, and two important factors are a material having excellent mechanical characteristics and a large joining strength. The third element added here is added to supplement the properties of the solder. For example, Sn-58Bi has a concern about bonding reliability due to the brittleness of Bi, but it is known that the mechanical properties can be improved by adding Ag. And is known.
【０００９】また、基板あるいは部品の接合部に表面被
覆処理が施される目的は、はんだ付け性を良好にし、接
合部の機械的強度を十分なものとして、製品の信頼性を
確保するためである。はんだ付け性を改善する作用とし
ては以下の通りである。[0009] The purpose of the surface coating treatment on the joints of the substrate or the parts is to improve the solderability and to ensure the mechanical strength of the joints to ensure the reliability of the product. is there. The effect of improving the solderability is as follows.
【００１０】 はんだ付け性の悪い母材に対して、よ
りはんだ付け性の良い材料を被覆することによって、は
んだ付け性を改善する。実装時に使用するはんだ合金を
母材に被覆すると、いわゆる予備はんだとなる。[0010] By coating a base material having poor solderability with a material having better solderability, the solderability is improved. When the base material is coated with a solder alloy used at the time of mounting, it becomes a so-called preliminary solder.
【００１１】 酸化等の表面腐食を起こしやすい母材
を、腐食しにくい材料によって被覆することにより母材
表面の腐食を防止し、はんだ付け性を確保する。表面被
覆処理は電解めっきや無電解めっきのような電気めっき
法の他、溶融めっき法、蒸着法などによって形成され
る。現在エレクトロニクス用はんだの大部分が前述のよ
うにＳｎ−３７Ｐｂが占めているため、表面被覆処理も
Ｓｎ−Ｐｂ系の予備はんだが大半を占めている。[0011] By coating a base material that is susceptible to surface corrosion such as oxidation with a non-corrosive material, corrosion of the base material surface is prevented and solderability is ensured. The surface coating treatment is formed by an electroplating method such as electrolytic plating or electroless plating, a hot-dip plating method, a vapor deposition method, or the like. At present, most of the solder for electronics is Sn-37Pb as described above, so that the Sn-Pb-based spare solder occupies most of the surface coating treatment.
【００１２】[0012]
【発明が解決しようとする課題】前項のＳｎ−Ｂｉ系は
んだにおいて、添加するＡｇが多くなりすぎると、逆に
機械的性質が劣化するということも知られている。It is also known that in the Sn-Bi-based solder described in the preceding paragraph, if too much Ag is added, the mechanical properties are adversely degraded.
【００１３】例えば、伸びの優れたＳｎ−５８Ｂｉ−１
Ａｇはんだは、ＮｉやＣｕに対して接合すると高い接合
強度が実現できる。しかし、Ａｇに対してはんだ接合を
行なうとはんだ中のＡｇの含有量が多くなり、伸びが小
さくなると同時に接合部の強度を低下させてしまう。For example, Sn-58Bi-1 having excellent elongation is used.
Ag solder can achieve high bonding strength when bonded to Ni or Cu. However, when solder bonding is performed on Ag, the content of Ag in the solder increases, and the elongation decreases, and at the same time, the strength of the bonding portion decreases.
【００１４】このため、Ｓｎ−５８Ｂｉはんだ中のＡｇ
の量を最適に添加できるようにすることが必要である。
また、Ｐｂ規制の問題は、はんだだけではなく、接合部
の表面被覆材料についても、Ｐｂフリー化を進める必要
がある。Ｐｂフリー表面被覆材料には、金（Ａｕ）、バ
ラジウム（Ｐｄ）、Ｓｎ、Ａｇ−Ｐｄや、Ｐｂフリーは
んだによる予備はんだが考えられる。部品リード部の表
面被覆材として、Ｓｎめっき、Ｐｄめっきを使用した部
品が既に市販されている。Therefore, Ag in Sn-58Bi solder
Need to be optimally added.
The problem of Pb regulation is that it is necessary to promote Pb-free not only for solder but also for the surface coating material of the joint. As a Pb-free surface coating material, gold (Au), palladium (Pd), Sn, Ag-Pd, or a preliminary solder using Pb-free solder can be considered. Components using Sn plating and Pd plating as the surface covering material of the component lead portions are already commercially available.
【００１５】ところが、Ｓｎ−Ｂｉ共晶系のはんだ合金
を用いてＳｎめっき部品を実装した場合、Ｓｎ−Ｂｉ共
晶はんだめっき部品を用いて実装した場合に比べて、接
合強度が著しく低下するといって問題が発生する。However, when the Sn-plated component is mounted using the Sn-Bi eutectic solder alloy, the bonding strength is significantly reduced as compared with the case where the Sn-Bi eutectic solder-plated component is mounted. Problem.
【００１６】[0016]
【課題を解決するための手段】図１は本発明の原理説明
図である。図において、１は回路基板、２ははんだ付け
部、３金属電極、４はＡｇ添加膜、５はＳｎ−Ｂｉはん
だ、６は電子部品、７は表面被覆材である。FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a circuit board, 2 is a soldering portion, 3 is a metal electrode, 4 is an Ag-added film, 5 is Sn-Bi solder, 6 is an electronic component, and 7 is a surface coating material.
【００１７】本発明では、図１（ａ）に回路基板１の金
属電極３への電子部品６のはんだ付け部２を断面構造図
で示すように、被接合電極材料にＡｇ添加膜４を用い、
はんだ接合時にＳｎ−５８Ｂｉはんだ５との拡散によっ
て、Ｓｎ−Ｂｉはんだ５中にＡｇ添加膜４よりＡｇを添
加させることにより、接合強度の高いＳｎ−５８Ｂｉは
んだ５を用いた場合と同様に、高い接合強度を提供す
る。In the present invention, an Ag-added film 4 is used as an electrode material to be joined, as shown in FIG. 1 (a) as a sectional structural view of a soldering portion 2 of an electronic component 6 to a metal electrode 3 of a circuit board 1. ,
By adding Ag from the Ag-added film 4 to the Sn-Bi solder 5 by diffusion with the Sn-58Bi solder 5 at the time of solder joining, the same as in the case of using the Sn-58Bi solder 5 having high joining strength, the same as in the case of using the Sn-58Bi solder 5 having a high joining strength. Provides joint strength.
【００１８】また、金属電極３の表面にはんだ接合時に
Ｓｎ−Ｂｉはんだ５中に全て拡散しつくす量のＡｇ、第
二層にＮｉまたはＣｕを配置することで、全体としてＡ
ｇを添加したＳｎ−５８Ｂｉ５がＮｉ、Ｃｕと接合され
ている状態となり、より強度の高い接合が可能となる。Further, by dispersing Ag in the Sn-Bi solder 5 at the surface of the metal electrode 3 at the time of solder joining, and Ni or Cu in the second layer, A
Sn-58Bi5 to which g has been added is in a state of being bonded to Ni and Cu, and bonding with higher strength is possible.
【００１９】また、Ｓｎを主成分とする表面被覆材７に
おいても、上記の問題を解決するため、接合後のはんだ
合金の組織や組成等の状態を調査し、鋭意検討を重ねた
結果、接合強度の低下の原因は、はんだ合金の溶融や拡
散により、電子部品６の端子等の表面被覆材７であるＳ
ｎが、Ｓｎ−Ｂｉはんだ５の合金と混合し、はんだ付け
部２のはんだ合金の組成が変化して、Ｓｎリッチ化して
いるためであることが明らかとなった。In order to solve the above-mentioned problems, the surface coating material 7 containing Sn as a main component was also examined for the structure, composition, and the like of the solder alloy after joining. The reason for the decrease in strength is that the surface coating material 7 such as a terminal of the electronic component 6 is formed by melting or diffusion of the solder alloy.
It has been clarified that n is mixed with the alloy of the Sn—Bi solder 5 and the composition of the solder alloy of the soldered portion 2 changes to make the Sn rich.
【００２０】この合金組成の変化によって、伸び、引っ
張り強さといった合金の機械的性質が変わることにより
接合強度が低下する。従って、接合強度を向上させるた
めには、接合部のはんだ合金の組成変化を抑制すること
が必要である。The change in the alloy composition changes the mechanical properties of the alloy, such as elongation and tensile strength, thereby lowering the bonding strength. Therefore, in order to improve the joining strength, it is necessary to suppress a change in the composition of the solder alloy at the joint.
【００２１】合金の組成変化抑制は、回路基板側の接合
部表面被覆材を、はんだ合金とリードおよびパッドの表
面処理材混合後の組成が、はんだ合金と同じになるよう
に調整することで達成できる。Suppression of the change in the composition of the alloy is achieved by adjusting the surface coating material of the bonding portion on the circuit board side so that the composition of the solder alloy and the lead and pad after mixing the surface treatment materials becomes the same as that of the solder alloy. it can.
【００２２】接合時のはんだ合金と接合部表面処理材の
混合によって接合部のはんだ合金は、元の合金とは異な
った組成、機械的性質を持ち、接合強度は低下する。回
路基板の接合部表面被覆処理は、プリント回路基板の製
作者の意志に応じて、有る程度自由に組成を調整するこ
とが可能である。そこで、はんだ合金と部品側接合部表
面被覆材が混合する時に、更に基板側接合部表面被覆材
が混合することにより、はんだ合金の組成変化が抑制で
きるように、基板側接合部表面被覆材の組成を調整する
ことで、接合強度を向上させることができる。Due to the mixing of the solder alloy and the surface treatment material at the time of joining, the solder alloy at the joint has a different composition and mechanical properties from the original alloy, and the joining strength is reduced. The composition of the surface coating of the joint of the circuit board can be adjusted to some extent freely according to the intention of the maker of the printed circuit board. Therefore, when the solder alloy and the component-side joint surface covering material are mixed, the board-side joint surface covering material is further mixed, so that the composition change of the solder alloy can be suppressed. By adjusting the composition, the bonding strength can be improved.
【００２３】部品側接合部表面処理材がＳｎめっきやＳ
ｎ−１０Ｂｉめっきの場合、接合後の半田合金組成はＳ
ｎリッチ化するため、基板側接合部表面処理材をＢｉリ
ッチとすることで、組成変化を抑制できる。[0023] The surface treatment material at the part-side joint is Sn plating or S
In the case of n-10Bi plating, the solder alloy composition after bonding is S
In order to make the substrate n-rich, the composition change can be suppressed by making the substrate side surface treatment material Bi-rich.
【００２４】つまり、Ｂｉ５０ｗｔ％以上、Ｓｎ残部、
このましくはＢｉ７０〜９０ｗｔ％、Ｓｎ残部のめっき
を基板パッド上に施すことで、組成変化を抑制し、接合
強度を向上することができる。That is, Bi is 50% by weight or more, the balance of Sn is
Preferably, plating of 70 to 90 wt% of Bi and the remainder of Sn on the substrate pad suppresses a change in composition and improves the bonding strength.
【００２５】[0025]
【発明の実施の形態】図２〜図５は本発明の実施例の説
明図である。図において、８はＡｇワイヤ、９はポリイ
ミド膜、10ははんだボール、11はＡｇ膜、12はＮｉまた
はＣｕワイヤ、13はプリント基板、14はＡｇ、15はＳｎ
−Ｂｉはんだ、16は電子部品、17は端子、18はＱＦＰパ
ッケージ、19はガラスエポキシ基板、20はＣｕパッドで
ある。FIG. 2 to FIG. 5 are explanatory views of an embodiment of the present invention. In the figure, 8 is an Ag wire, 9 is a polyimide film, 10 is a solder ball, 11 is an Ag film, 12 is a Ni or Cu wire, 13 is a printed circuit board, 14 is Ag, and 15 is Sn.
-Bi solder, 16 is an electronic component, 17 is a terminal, 18 is a QFP package, 19 is a glass epoxy board, and 20 is a Cu pad.
【００２６】接着強度を確認する本発明の第一の実施例
について、図２により説明する。直径１ｍｍのＡｇワイ
ヤ８にポリイミド膜９を被覆し、Ａｇワイヤ８の端面に
直径０．８ｍｍのはんだボール10を予備はんだし、これ
を２本一組としてはんだボール10同士を互いに突き合わ
せて加熱することによりＡｇワイヤ８を接合した。A first embodiment of the present invention for checking the adhesive strength will be described with reference to FIG. An Ag wire 8 having a diameter of 1 mm is coated with a polyimide film 9, and a solder ball 10 having a diameter of 0.8 mm is pre-soldered on the end surface of the Ag wire 8. Thus, the Ag wire 8 was joined.
【００２７】接合温度は１７０℃、加熱時間は３０秒で
行った。はんだボール10にはＳｎ−５８ＢｉとＳｎ−５
８Ｂｉ−１Ａｇの２種類のはんだを用いた。本発明と比
較のため、従来のＳｎ−３７Ｐｂはんだでも同様の実験
を行った。その結果、接合温度は２１０℃で、加熱時間
は３０秒で行った。The bonding temperature was 170 ° C. and the heating time was 30 seconds. Solder balls 10 include Sn-58Bi and Sn-5
8Bi-1Ag two kinds of solders were used. For comparison with the present invention, a similar experiment was performed with a conventional Sn-37Pb solder. As a result, the bonding temperature was 210 ° C. and the heating time was 30 seconds.
【００２８】引っ張り試験を行った結果を表１に示す。Table 1 shows the results of the tensile test.
【００２９】[0029]
【表１】 [Table 1]
【００３０】ＡｇとＳｎ−５８Ｂｉの接合で８．５９ｋ
ｇ／ｍｍ2 、ＡｇとＳｎ−５８Ｂｉ−１Ａｇの接合で
６．９０ｋｇ／ｍｍ2 、ＡｇとＳｎ−３７Ｐｂの接合で
８．０４ｋｇ／ｍｍ2 となり、ＡｇとＳｎ−５８Ｂｉを
接合すると高い接合強度が得られることが分かった。8.59k at the junction of Ag and Sn-58Bi
g / mm 2, Ag and Sn-58Bi-1Ag 6.90kg / mm 2 at the junction, Ag and 8.04 kg / mm 2 next at the junction of Sn-37Pb, high bonding strength when bonding the Ag and Sn-58Bi It turned out to be obtained.
【００３１】次に、接着強度を確認する本発明の第二の
実施例について、図３により説明する。直径１ｍｍのＮ
ｉまたはＣｕワイヤ12にポリイミド膜９を被覆し、ワイ
ヤ12の端面にＡｇ膜11をめっきよって１μｍの厚さに形
成した。これに直径０．８ｍｍのはんだボール10を予備
はんだし、これを２本一組としてはんだ同士を互いに突
き合わせて加熱することにより接合した。Next, a second embodiment of the present invention for checking the adhesive strength will be described with reference to FIG. 1mm diameter N
An i or Cu wire 12 was coated with a polyimide film 9, and an Ag film 11 was formed on the end face of the wire 12 by plating to a thickness of 1 μm. A solder ball 10 having a diameter of 0.8 mm was preliminarily soldered to the solder ball, and the solder ball 10 was joined as a set of two pieces by abutting and heating the solder pieces.
【００３２】はんだはＳｎ−５８ＢｉとＳｎ−３７Ｐｂ
の２種類を用いた。接合温度は、Ｓｎ−５８Ｂｉは１７
０℃、Ｓｎ−３７Ｐｂは２１０℃で加熱時間はともに３
０秒である。Solder is Sn-58Bi and Sn-37Pb
Were used. The bonding temperature is 17 for Sn-58Bi.
0 ° C, Sn-37Pb is 210 ° C and the heating time is 3
0 seconds.
【００３３】引っ張り試験を行った結果を表２に示す。Table 2 shows the results of the tensile test.
【００３４】[0034]
【表２】 [Table 2]
【００３５】Ｓｎ−５８Ｂｉで接合した場合、ベースの
ワイヤ12がＮｉ、Ｃｕのいづれにおいても、Ｓｎ−３７
Ｐｂを用いて接合したものよりも高い接合強度が得られ
る。次に、本出願の第一の発明について、実際に電子部
品をプリント板等の回路基板にはんだ付けした本発明の
第三の実施例について説明する。In the case of joining with Sn-58Bi, the base wire 12 is made of Sn-37 regardless of Ni or Cu.
Higher bonding strength than that obtained by bonding using Pb can be obtained. Next, with respect to the first invention of the present application, a third embodiment of the present invention in which electronic components are actually soldered to a circuit board such as a printed board will be described.
【００３６】図４に断面図で示すように、プリント基板
13上の配線銅箔の電子部品16の端子17との接合部分（は
んだ付け部）に銀を１００μｍの厚さに予め蒸着法とフ
ォトプロセスにより形成しておく。その上にＳｎ−５８
Ｂｉのはんだを載せ、１７０℃に加熱で３０秒加熱す
る。銅箔上の銀の薄膜から銀がＳｎ−Ｂｉはんだに拡散
し、プリント基板への電子部品の強固なはんだ付けが完
了する。As shown in the sectional view of FIG.
Silver is previously formed to a thickness of 100 μm by a vapor deposition method and a photo process on a bonding portion (solder portion) of the wiring copper foil on the 13 and the terminal 17 of the electronic component 16. On top of that, Sn-58
The Bi solder is placed and heated to 170 ° C. for 30 seconds. The silver diffuses from the silver thin film on the copper foil into the Sn-Bi solder, and the solid soldering of the electronic component to the printed circuit board is completed.
【００３７】次に、本出願の第二の発明について、表面
被覆材に関する本発明の第四の実施例について説明す
る。端子17表面に厚さ１０μｍのＳｎめっきが施してあ
る、０．５ｍｍピッチの２０８ピンＱＦＰパッケージ18
をＳｎ−Ｂｉ共晶はんだでガラスエポキシ基板19の接合
部のＣｕパッド20に接合した。Ｃｕパッド20は厚さ１５
μｍの１０Ｓｎ−９０Ｂｉめっきを施したものと、比較
のために無処理のものとを用いた。Next, with respect to the second invention of the present application, a fourth embodiment of the present invention relating to a surface covering material will be described. 0.5 mm pitch 208-pin QFP package 18 with 10 μm thick Sn plating on the surface of terminal 17
Was bonded to the Cu pad 20 at the joint of the glass epoxy substrate 19 with Sn-Bi eutectic solder. Cu pad 20 has a thickness of 15
The one subjected to 10 μm 10Sn-90Bi plating and the untreated one for comparison were used.
【００３８】リードの接合強度をピーリング（剥離）試
験により評価した結果を表３に示す。Table 3 shows the results of evaluation of the bonding strength of the leads by a peeling (peeling) test.
【００３９】[0039]
【表３】 [Table 3]
【００４０】表３に示されたように、はんだ合金とリー
ド表面処理材の組成が異なる条件１では、接合強度は１
００ｇ／ピンとなる。これは比較実験して行った合金と
表面処理材の組成が同一である条件３、条件４と比べて
非常に低い値である。As shown in Table 3, under the condition 1 in which the compositions of the solder alloy and the lead surface treatment material were different, the bonding strength was 1
00 g / pin. This is a very low value compared to the conditions 3 and 4 in which the composition of the alloy and the surface treatment material were the same in the comparative experiment.
【００４１】これに対して、はんだ合金とリードおよび
パッドの表面処理材が混合後の組成がはんだ合金と同じ
になるようにパッドの表面処理材を調整した条件２で
は、条件１に比べて接合強度は大幅に向上しており、条
件３、条件４と同程度の強度となる。On the other hand, under the condition 2 in which the surface treatment material of the pad was adjusted so that the composition after mixing the solder alloy with the surface treatment material of the lead and the pad was the same as that of the solder alloy, the bonding was more effective than in the condition 1. The strength is greatly improved, and is about the same as the conditions 3 and 4.
【００４２】[0042]
【発明の効果】以上説明したように、Ｓｎ−Ｂｉ系はん
だを用いた場合は、Ａｇ添加膜の電極に対してＳｎ−Ｂ
ｉはんだを接合することで、はんだ中へのＡｇの添加が
可能となり、強度の高い接合が可能となる。As described above, when the Sn-Bi solder is used, the Sn-Bi solder is used for the electrode of the Ag-added film.
By joining the i-solder, Ag can be added to the solder, and a high-strength joint can be achieved.
【００４３】また、Ｓｎ−Ｂｉ共晶系はんだを用いたＳ
ｎめっき部品の高強度接合方法を用いることにより、接
合部ははんだ合金の組成変化による接合強度の低下とい
う問題を解決することができる。これにより、Ｓｎ−Ｂ
ｉ共晶系の鉛フリーはんだを用いたＳｎめっき部品の接
合信頼性を確保することができる。In addition, S using Sn—Bi eutectic solder
By using the high-strength joining method of the n-plated component, the problem that the joining strength of the joining portion is reduced due to a change in the composition of the solder alloy can be solved. Thereby, Sn-B
Bonding reliability of Sn plated parts using i-eutectic lead-free solder can be ensured.
【図１】 本発明の原理説明図FIG. 1 is a diagram illustrating the principle of the present invention.
【図２】 本発明の第一の実施例の説明図FIG. 2 is an explanatory diagram of a first embodiment of the present invention.
【図３】 本発明の第二の実施例の説明図FIG. 3 is an explanatory view of a second embodiment of the present invention.
【図４】 本発明の第三の実施例の説明図FIG. 4 is an explanatory view of a third embodiment of the present invention.
【図５】 本発明の第四の実施例の説明図FIG. 5 is an explanatory view of a fourth embodiment of the present invention.
【符号の説明】 図において １ 回路基板 ２ はんだ付け部 ３ 金属電極 ４ Ａｇ添加膜 ５ Ｓｎ−Ｂｉはんだ ６ 電子部品 ７ 表面被覆材 ８ Ａｇワイヤ ９ ポリイミド膜 10 はんだボール 11 Ａｇ膜 12 ＮｉまたはＣｕワイヤ 13 プリント基板 14 Ａｇ 15 Ｓｎ−Ｂｉはんだ 16 電子部品 17 端子 18 ＱＦＰパッケージ 19 ガラスエポキシ基板 20 Ｃｕパッド[Description of Signs] In the drawings, 1 circuit board 2 soldering portion 3 metal electrode 4 Ag-added film 5 Sn-Bi solder 6 electronic component 7 surface coating material 8 Ag wire 9 polyimide film 10 solder ball 11 Ag film 12 Ni or Cu wire 13 Printed circuit board 14 Ag 15 Sn-Bi solder 16 Electronic component 17 Terminal 18 QFP package 19 Glass epoxy board 20 Cu pad
───────────────────────────────────────────────────── フロントページの続き (72)発明者 表 孝 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 山岸 康男 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Omotaka 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Yasuo Yamagishi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Inside Fujitsu Limited
Claims (3)
添加膜を形成し、次いで該はんだ付け部に電子部品を錫
（Ｓｎ）−ビスマス（Ｂｉ）はんだで接合することを特
徴とする錫−ビスマスはんだの接合方法。1. Silver (Ag) is applied to a soldered portion on a circuit board.
A method for joining tin-bismuth solder, comprising forming an additive film and then joining the electronic component to the soldered portion with tin (Sn) -bismuth (Bi) solder.
たは銅（Ｃｕ）の膜で形成し、該ニッケルまたは銅の表
面に５μｍを超えない厚さの前記銀添加膜を形成するこ
とを特徴とする請求項１記載の錫−ビスマスはんだの接
合方法。2. The method according to claim 1, wherein the soldering portion is formed of a nickel (Ni) or copper (Cu) film, and the silver-added film having a thickness not exceeding 5 μm is formed on the surface of the nickel or copper. The method for joining tin-bismuth solder according to claim 1.
〜７０Ｗｔ％を含む錫−ビスマスはんだを用いて電子部
品を回路基板にはんだ付けする際、該回路基板上のはん
だ付け部の表面被覆材にビスマスが５０Ｗｔ％を超える
錫−ビスマスはんだを用いることを特徴とする錫−ビス
マスはんだの接合方法。3. Tin is 40 to 50% by weight and bismuth is 40% by weight.
When soldering an electronic component to a circuit board using a tin-bismuth solder containing up to 70 Wt%, the use of a tin-bismuth solder in which bismuth exceeds 50 Wt% is used as a surface covering material of a soldered portion on the circuit board. Characteristic method of joining tin-bismuth solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8189546A JPH1041621A (en) | 1996-07-18 | 1996-07-18 | Tin-bismuth solder joining method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8189546A JPH1041621A (en) | 1996-07-18 | 1996-07-18 | Tin-bismuth solder joining method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1041621A true JPH1041621A (en) | 1998-02-13 |
Family
ID=16243130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8189546A Pending JPH1041621A (en) | 1996-07-18 | 1996-07-18 | Tin-bismuth solder joining method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1041621A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999030866A1 (en) * | 1997-12-16 | 1999-06-24 | Hitachi, Ltd. | Pb-FREE SOLDER-CONNECTED STRUCTURE AND ELECTRONIC DEVICE |
| US6241145B1 (en) | 1999-04-22 | 2001-06-05 | Mitsubishi Denki Kabushiki Kaisha | Lead-free solder joining method and electronic module manufactured by using the method |
| EP1243026A1 (en) * | 1999-12-21 | 2002-09-25 | Advanced Micro Devices, Inc. | Organic packages with solders for reliable flip chip connections |
| GB2383552A (en) * | 2001-12-28 | 2003-07-02 | Matsushita Electric Industrial Co Ltd | Use of a barrier layer on a Cu substrate when using a Sn-Bi alloy as solder |
| JP2004322213A (en) * | 2004-05-28 | 2004-11-18 | Hitachi Ltd | Pb-free solder connection structure and electronic equipment |
| JP2007324447A (en) * | 2006-06-02 | 2007-12-13 | Hitachi Kyowa Engineering Co Ltd | Electronic component mounting substrate, electronic component and electronic device |
| JP2008113003A (en) * | 2007-10-26 | 2008-05-15 | Hitachi Ltd | Pb-free solder connection structure and electronic device |
| JP2009044180A (en) * | 1999-01-11 | 2009-02-26 | Panasonic Corp | Printed circuit boards and electrical products, and methods for recycling these wastes |
| US8556157B2 (en) | 2008-11-28 | 2013-10-15 | Fujitsu Limited | Method of manufacturing electronic apparatus, electronic component-mounting board, and method of manufacturing the same |
| JP2014027314A (en) * | 2013-11-05 | 2014-02-06 | Rohm Co Ltd | Semiconductor device and method for manufacturing semiconductor device |
| WO2014115798A1 (en) * | 2013-01-28 | 2014-07-31 | 株式会社村田製作所 | Solder bump formation method and solder bump |
| JP2014146652A (en) * | 2013-01-28 | 2014-08-14 | Toppan Printing Co Ltd | Wiring board and method of manufacturing the same |
| US10056342B2 (en) | 2011-12-26 | 2018-08-21 | Fujitsu Limited | Electronic component and electronic device |
-
1996
- 1996-07-18 JP JP8189546A patent/JPH1041621A/en active Pending
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999030866A1 (en) * | 1997-12-16 | 1999-06-24 | Hitachi, Ltd. | Pb-FREE SOLDER-CONNECTED STRUCTURE AND ELECTRONIC DEVICE |
| KR100716094B1 (en) * | 1997-12-16 | 2007-05-09 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor devices |
| US8503189B2 (en) | 1997-12-16 | 2013-08-06 | Renesas Electronics Corporation | Pb-free solder-connected structure and electronic device |
| US7709746B2 (en) | 1997-12-16 | 2010-05-04 | Renesas Technology Corp. | Pb-free solder-connected structure and electronic device |
| US8907475B2 (en) | 1997-12-16 | 2014-12-09 | Renesas Electronics Corporation | Pb-free solder-connected structure |
| US6960396B2 (en) | 1997-12-16 | 2005-11-01 | Hitachi, Ltd. | Pb-free solder-connected structure and electronic device |
| US7013564B2 (en) | 1997-12-16 | 2006-03-21 | Hitachi, Ltd. | Method of producing an electronic device having a PB free solder connection |
| JP2009044180A (en) * | 1999-01-11 | 2009-02-26 | Panasonic Corp | Printed circuit boards and electrical products, and methods for recycling these wastes |
| US6241145B1 (en) | 1999-04-22 | 2001-06-05 | Mitsubishi Denki Kabushiki Kaisha | Lead-free solder joining method and electronic module manufactured by using the method |
| JP2003518743A (en) * | 1999-12-21 | 2003-06-10 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Organic packages with solder for reliable flip-chip connection |
| EP1243026A1 (en) * | 1999-12-21 | 2002-09-25 | Advanced Micro Devices, Inc. | Organic packages with solders for reliable flip chip connections |
| US6871775B2 (en) | 2001-12-28 | 2005-03-29 | Matsushita Electric Industrial Co., Ltd. | Process for soldering and connecting structure |
| GB2383552B (en) * | 2001-12-28 | 2005-03-02 | Matsushita Electric Industrial Co Ltd | Process for soldering and connecting structure |
| GB2383552A (en) * | 2001-12-28 | 2003-07-02 | Matsushita Electric Industrial Co Ltd | Use of a barrier layer on a Cu substrate when using a Sn-Bi alloy as solder |
| JP2004322213A (en) * | 2004-05-28 | 2004-11-18 | Hitachi Ltd | Pb-free solder connection structure and electronic equipment |
| JP2007324447A (en) * | 2006-06-02 | 2007-12-13 | Hitachi Kyowa Engineering Co Ltd | Electronic component mounting substrate, electronic component and electronic device |
| JP2008113003A (en) * | 2007-10-26 | 2008-05-15 | Hitachi Ltd | Pb-free solder connection structure and electronic device |
| US8740047B2 (en) | 2008-11-28 | 2014-06-03 | Fujitsu Limited | Method of manufacturing electronic apparatus, electronic component-mounting board, and method of manufacturing the same |
| US8556157B2 (en) | 2008-11-28 | 2013-10-15 | Fujitsu Limited | Method of manufacturing electronic apparatus, electronic component-mounting board, and method of manufacturing the same |
| US10056342B2 (en) | 2011-12-26 | 2018-08-21 | Fujitsu Limited | Electronic component and electronic device |
| US10062658B2 (en) | 2011-12-26 | 2018-08-28 | Fujitsu Limited | Electronic component and electronic device |
| WO2014115798A1 (en) * | 2013-01-28 | 2014-07-31 | 株式会社村田製作所 | Solder bump formation method and solder bump |
| JP2014146652A (en) * | 2013-01-28 | 2014-08-14 | Toppan Printing Co Ltd | Wiring board and method of manufacturing the same |
| US9883586B2 (en) | 2013-01-28 | 2018-01-30 | Toppan Printing Co., Ltd. | Wiring substrate for bonding using solder having a low melting point and method for manufacturing same |
| US10090268B2 (en) | 2013-01-28 | 2018-10-02 | Murata Manufacturing Co., Ltd. | Method of forming solder bump, and solder bump |
| JP2014027314A (en) * | 2013-11-05 | 2014-02-06 | Rohm Co Ltd | Semiconductor device and method for manufacturing semiconductor device |
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