JPH1050935A - Ｅｓｄ保護のためのｄｅｎｍｏｓトランジスタおよびｍｏｓトランジスタの設計を最適化する方法 - Google Patents

Ｅｓｄ保護のためのｄｅｎｍｏｓトランジスタおよびｍｏｓトランジスタの設計を最適化する方法

Info

Publication number
JPH1050935A
JPH1050935A JP9127248A JP12724897A JPH1050935A JP H1050935 A JPH1050935 A JP H1050935A JP 9127248 A JP9127248 A JP 9127248A JP 12724897 A JP12724897 A JP 12724897A JP H1050935 A JPH1050935 A JP H1050935A
Authority
JP
Japan
Prior art keywords
region
transistor
gate
drain
esd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9127248A
Other languages
English (en)
Japanese (ja)
Inventor
Charvaka Duvvury
ドゥブブリィ チャルバカ
David Douglas Briggs
ダグラス ブリッグス デビッド
Debitsudo Karubajiyaru Fuerunando
デビッド カルバジャル フェルナンド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH1050935A publication Critical patent/JPH1050935A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
    • H10D84/409—Combinations of FETs or IGBTs with lateral BJTs and with one or more of diodes, resistors or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
JP9127248A 1996-05-17 1997-05-16 Ｅｓｄ保護のためのｄｅｎｍｏｓトランジスタおよびｍｏｓトランジスタの設計を最適化する方法 Pending JPH1050935A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1834496P 1996-05-17 1996-05-17
US018344 1996-05-17

Publications (1)

Publication Number Publication Date
JPH1050935A true JPH1050935A (ja) 1998-02-20

Family

ID=21787455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9127248A Pending JPH1050935A (ja) 1996-05-17 1997-05-16 Ｅｓｄ保護のためのｄｅｎｍｏｓトランジスタおよびｍｏｓトランジスタの設計を最適化する方法

Country Status (5)

Country Link
US (1) US6071768A (de)
EP (1) EP0807977A3 (de)
JP (1) JPH1050935A (de)
KR (1) KR970077370A (de)
TW (1) TW373315B (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1009036B1 (de) * 1998-12-09 2007-09-19 STMicroelectronics S.r.l. Leistungsbauelement mit MOS-Gate für hohe Spannungen und diesbezügliches Herstellungsverfahren
KR100302611B1 (ko) * 1999-06-07 2001-10-29 김영환 고전압 반도체 소자 및 그 제조방법
US6660603B2 (en) 2000-09-21 2003-12-09 Texas Instruments Incorporated Higher voltage drain extended MOS transistors with self-aligned channel and drain extensions
US6303444B1 (en) * 2000-10-19 2001-10-16 Sun Microsystems, Inc. Method for introducing an equivalent RC circuit in a MOS device using resistive wells
US6583001B1 (en) * 2001-05-18 2003-06-24 Sun Microsystems, Inc. Method for introducing an equivalent RC circuit in a MOS device using resistive paths
US6586817B1 (en) * 2001-05-18 2003-07-01 Sun Microsystems, Inc. Device including a resistive path to introduce an equivalent RC circuit
KR100522519B1 (ko) * 2002-06-07 2005-10-18 재단법인서울대학교산학협력재단 정전기 보호 사이리스터
US7235451B2 (en) * 2003-03-03 2007-06-26 Texas Instruments Incorporated Drain extended MOS devices with self-aligned floating region and fabrication methods therefor
US6900101B2 (en) * 2003-06-13 2005-05-31 Texas Instruments Incorporated LDMOS transistors and methods for making the same
US7005354B2 (en) * 2003-09-23 2006-02-28 Texas Instruments Incorporated Depletion drain-extended MOS transistors and methods for making the same
US6960807B2 (en) * 2003-11-25 2005-11-01 Texas Instruments Incorporated Drain extend MOS transistor with improved breakdown robustness
US7238986B2 (en) * 2004-05-03 2007-07-03 Texas Instruments Incorporated Robust DEMOS transistors and method for making the same
US20080061374A1 (en) * 2006-09-07 2008-03-13 System General Corporation Semiconductor resistor and semiconductor process of making the same
US8163621B2 (en) * 2008-06-06 2012-04-24 Globalfoundries Singapore Pte. Ltd. High performance LDMOS device having enhanced dielectric strain layer
US8354710B2 (en) 2008-08-08 2013-01-15 Infineon Technologies Ag Field-effect device and manufacturing method thereof
US8536648B2 (en) 2011-02-03 2013-09-17 Infineon Technologies Ag Drain extended field effect transistors and methods of formation thereof
US8681461B2 (en) 2012-03-26 2014-03-25 Intel Mobile Communications GmbH Selective current pumping to enhance low-voltage ESD clamping using high voltage devices
US8654491B2 (en) 2012-04-02 2014-02-18 Intel Mobile Communications GmbH Low voltage ESD clamping using high voltage devices
FR3048288B1 (fr) * 2016-02-25 2018-03-23 Stmicroelectronics (Crolles 2) Sas Detecteur electronique integre de variations de potentiel a haute sensibilite

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019888A (en) * 1987-07-23 1991-05-28 Texas Instruments Incorporated Circuit to improve electrostatic discharge protection
US5173755A (en) * 1989-05-12 1992-12-22 Western Digital Corporation Capacitively induced electrostatic discharge protection circuit
JP3199808B2 (ja) * 1991-05-14 2001-08-20 セイコーインスツルメンツ株式会社 半導体集積回路装置
US5371395A (en) * 1992-05-06 1994-12-06 Xerox Corporation High voltage input pad protection circuitry
US5369041A (en) * 1993-07-14 1994-11-29 Texas Instruments Incorporated Method for forming a silicon controlled rectifier
US5517046A (en) * 1993-11-19 1996-05-14 Micrel, Incorporated High voltage lateral DMOS device with enhanced drift region
KR100320354B1 (ko) * 1994-01-12 2002-06-24 쥴리 와이. 마-스피놀라 최적화된정전방전보호성능을갖는입력/출력트랜지스터
DE4423591C2 (de) * 1994-07-06 1996-08-29 Itt Ind Gmbh Deutsche Schutzstruktur für integrierte Schaltungen
US5646808A (en) * 1994-08-05 1997-07-08 Kawasaki Steel Corporation Electrostatic breakdown protection circuit for a semiconductor integrated circuit device
US5872376A (en) * 1997-03-06 1999-02-16 Advanced Micro Devices, Inc. Oxide formation technique using thin film silicon deposition

Also Published As

Publication number Publication date
TW373315B (en) 1999-11-01
KR970077370A (ko) 1997-12-12
EP0807977A3 (de) 2000-03-15
EP0807977A2 (de) 1997-11-19
US6071768A (en) 2000-06-06

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