JPH1056072A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To always provide an I/O block demanded by a user at an optimum driving capacity and reduce the possibility of occurrence of a pad neck from occurring by making the I/O block have a means for dividing the driving capacity of itself. SOLUTION: Transistors 105 and 106 are connected with each other by wiring 129, using terminals 113 and 114, and the transistor 106 and a transistor 107 are connected with each other by wiring 130, using terminals 118 and 119, and the transistors 107 and a transistor 108 are connected with each other by wiring 131, using terminals 115 and 116. Likewise, transistors 109 and 110 are connected with each other by wiring 133, using terminals 121 and 122, and the transistor 110 and a transistor 111 are connected with each other by wiring 134, using terminals 126 and 127. The transistor 111 and a transistor 112 are connected with each other, using terminals 123 and 124, and the transistors 108 and 109 are connected with each other by wiring 132, using terminals 120 and 125.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a standard cell type custom LSI.

[0002]

2. Description of the Related Art Custom LSI of standard cell type
Among them, a custom LSI called “CPU core method” is a CPU, R, and R which are prepared in advance by an LSI manufacturer.
By combining large-scale logic functions such as OM, RAM, I / O port, serial I / O, and timer, and basic gate cells, a user can freely configure an IC suitable for a unique purpose. IC for "Cell Base I
C ”).

[0003] When a user designs the above-mentioned cell-based IC, the user needs a CPU, ROM,
Using a symbol representing a RAM or the like, or a symbol representing a basic gate cell, a circuit diagram interconnecting them by using E
It is created by using CAD mounted on WS (Engineering Workstation).

[0004] At the same time, the user, in accordance with the application and specifications of the IC to be designed, and another IC on the substrate on which the IC is mounted.
Consider I / O blocks interconnected with switches and switches.

However, I / Os prepared by LSI manufacturers
In the O block, I / O of the driving ability desired by the user
If the block has not been prepared, the user uses an I / O block exceeding the desired drive capability to satisfy the desired drive capability, or uses an external terminal of the I / O block adjacent to the I / O block. The external terminals of unused I / O blocks are short-circuited (such a method is called “pad bridge”) to satisfy the driving capability.

[0006] Specifically, the LSI maker has a 4 mA
When an I / O block having a driving capability of 8 mA and 12 mA is prepared, and a user requests an I / O block having a driving capability of 9 mA, an I / O block having a driving capability of 12 mA is used.
You will use blocks.

Also, I / Os prepared by LSI manufacturers
If the block is an I / O block with a driving capability of 2 mA, 4 mA, 6 mA, and 8 mA, the user can use 12 mA.
When a driving capability of 6 is requested, as shown in FIG.
The I / O blocks 307 and 308 having a driving capability of mA are arranged adjacent to each other, and the unused I / O block 308 and the external terminal 301 are pad-bridged via the metal wiring 304 to realize a driving capability of 12 mA. However, it has been designed to satisfy the driving ability desired by the user.

[0008]

The first problem of the above-mentioned conventional system is that since the specifications of the user have been diversified, the I / O of the optimum driving capability required by the user is required on the LSI maker side. It is becoming increasingly difficult to provide blocks.

For this reason, it is difficult to satisfy all the driving capabilities required by the user only with the I / O blocks prepared in advance by the LSI maker.

[0010] The second problem is that the chip size becomes large.

The reason is that the number of external terminals may determine the size of the IC dominantly because the specifications of the user are complicated and the performance is high.
Just arranging the / O blocks may exceed the target IC size and may necessitate increasing the size of the IC (such a situation is referred to as "pad neck").

As described in the above prior art, a plurality of I
This is because, when pad bridging is performed using an / O block, the possibility of occurrence of the pad neck is further increased.

Accordingly, the present invention has been made in view of the above circumstances, and has as its object to realize a semiconductor device which realizes an I / O block having an optimum driving capability with respect to diversifying specifications of users. It is to provide an integrated circuit.

[0014]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention is characterized in that the I / O block has means for dividing the driving capability of the I / O block. I do.

The outline of the present invention will be described below. The present invention is characterized in that, in an I / O block prepared in advance by an LSI maker, there is provided a means for changing a dimension of a gate of a transistor for determining a driving capability according to a user's request. It is.

According to the present invention, the driving capability of the I / O block can be changed in multiple stages in accordance with the driving capability requested by the user. Therefore, a plurality of I / O blocks having the driving capability are arranged. There is no need for pad bridging.

Further, it is not necessary for the LSI maker to prepare all the I / O blocks having the driving capability that the user may use.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a mask layout diagram showing the configuration of the first embodiment of the present invention. FIG. 1 shows the gates, terminals,
Only the wiring is shown. For simplicity, only the gate, terminal, and wiring of the transistor are shown.

In FIG. 1, reference numeral 103 denotes an I / O block, and reference numerals 105 to 108 denote gates of transistors that determine the driving capability of the I / O block 103. Reference numerals 113 to 120 denote the gates 105 of the transistors, respectively.
And terminals for interconnecting the gates of adjacent transistors.

Similarly, reference numeral 104 denotes an I / O block;
Reference numerals 109 to 112 denote gates of transistors that determine the driving capability of the I / O block 104. Also, 12
1 to 128 are gates 109 to 112 of the transistors, respectively.
The terminal arranged above is a terminal for interconnecting gates of adjacent transistors.

In this embodiment, the gates 105 to 108 and 109 to 112 of the transistor all have the same driving capability, and the driving capability (current driving capability) is, for example, 2 mA.

Next, an example illustrating a specific example of the embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 1, a maximum of 2 mA × 4
The I / O blocks 103 and 104 with the driving capability of mA are LS
If the user requests an I / O block having a driving capability of 16 mA when the I maker prepares the transistor gates 105 and 106, the terminals 113 and 114 are used for the transistor gates 105 and 106. 107
Are interconnected by wiring 130 using terminals 118 and 119, and transistor gates 107 and 108 are connected to terminals 11 and 119.
5 and 116 are interconnected by a wiring 131, and the transistor gates 109 and 110 are similarly connected to the terminals 121 and 12
2 and the transistor gates 110 and 111 are connected to each other by the wiring 134 using the terminals 126 and 127, and the transistor gates 111 and 1 are connected to each other.
12 are interconnected by wiring 135 using terminals 123 and 124, and transistor gates 108 and 109 are
0 and 125 are interconnected by a wiring 132 and all of the transistor gates 105 to 112 are connected, so that the I / O of the driving capability of 16 mA required by the user is achieved.
An O block can be realized.

Also, as an embodiment of the present invention, even when the LSI maker prepares only the I / O block of the type of the I / O block 103, the user requests the I / O block having the driving capability of 16 mA. Is I / O block 1
03 and 104 are arranged adjacent to each other and the transistor gate 1
05 interconnects 108, 109-112, and interconnects the transistor gates 108 and 109, thereby realizing an I / O block with a driving capability of 16 mA.

As described above, by interconnecting the transistor gates of the I / O block, it is possible to easily realize an I / O block having the driving capability required by the user.

Next, another embodiment of the present invention will be described in detail with reference to FIG. FIG. 2 shows a mask layout diagram of an I / O block according to a second embodiment of the present invention.
FIG. 2 shows only gates, terminals, and wirings of the transistors to facilitate understanding of the present invention.

In FIG. 2, reference numeral 205 denotes an I / O block, and reference numerals 208 to 211 denote gates of transistors that determine the driving capability of the I / O block 205. Also, 22
0 to 227 are transistor gates 208 to 211, respectively.
A terminal arranged above, which is a terminal for interconnecting gates of adjacent transistors.

Similarly, reference numeral 206 denotes an I / O block;
Reference numerals 212 to 215 denote gates of transistors that determine the driving capability of the I / O block 206. 228-2
Reference numeral 35 denotes terminals arranged on the gates 212 to 215 of the transistors, and terminals for interconnecting the gates of adjacent transistors.

Similarly, reference numeral 207 denotes an I / O block.
Reference numerals 216 to 219 denote gates of transistors that determine the driving capability of the I / O block 207. Also, 236-2
43 is a terminal arranged on each of the gates 216 to 219 of the transistor, and is a terminal for interconnecting the gates of adjacent transistors.

In this embodiment, the gate 20 of the transistor
8 to 211, 212 to 215, and 216 to 219 all have the same driving capability, and the driving capability is, for example, 2 mA.

Here, as shown in FIG. 2, 2 mA × 4
I / O blocks 205, 2 with a drive capacity of up to 8 mA
If the LSI maker prepares the I / O blocks 205, 206, and 207 consecutively, and if the user requests two I / O blocks with a driving capability of 12 mA, Gates 208 to 213 are connected to wiring 24
4 to 248 to realize a driving capability of 12 mA, and connect gates 214 to 219 to wirings 249 to 253.
And realize a driving capability of 12 mA.

As described above, by dividing and using the driving capability of the I / O block 206 that is not directly connected to the external terminal, one space for three I / O blocks can be used.
Since it is possible to arrange two I / O blocks having a driving capability of 2 mA, in the conventional technology, four I / O blocks having a driving capability of 6 mA are used, and an I / O block having a driving capability of 12 mA is used. While two O blocks are realized, the total number of I / O blocks arranged around the IC can be reduced.

For this reason, the present embodiment can reduce the possibility of occurrence of a pad neck.

[0035]

As described above, according to the present invention,
The following effects are obtained.

(1) The first effect is that an I / O block having a driving capability requested by a user can always be provided with an optimum driving capability.

The reason is that, in the present invention, the dimension of the gate of the transistor which determines the drive capability of the I / O block can be changed according to the user's request.

(2) The second effect is that the possibility of occurrence of a pad neck can be reduced.

The reason is that, in the present invention, the driving capability of the I / O block can be divided and used.
This is because the total number of / O blocks can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 3 is a diagram showing an example of a pad bridge of a conventional I / O block.

[Explanation of symbols]

101 External Terminal of IC 102 External Terminal 101 of IC and I / O Block 103
103-104 I / O blocks 105-112 Gates of transistors that determine the drive capability of I / O blocks 113-128 Terminals for interconnecting the gates of transistors 129 Interconnecting terminals 113 and 114 Wiring 130 Wiring for interconnecting terminals 118 and 119 131 Wiring for interconnecting terminals 115 and 116 132 Wiring for interconnecting terminals 120 and 125 133 Wiring for interconnecting terminals 121 and 122 134 Interconnecting for terminals 126 and 127 Wiring 135 Wiring for interconnecting terminals 123 and 124 201, 202 External terminal of IC 203 External terminal 201 of IC and I / O block 205
For interconnecting the IC 204 The external terminal 202 of the IC and the I / O block 207
205 to 107 I / Os 208 to 219 Gates of transistors that determine the driving capability of the I / O block 220 to 243 Terminals for interconnecting the gates of the transistors 244 Wirings for interconnecting the terminals 220 and 221 245 Wiring interconnecting terminals 225 and 226 246 Wiring interconnecting terminals 222 and 223 247 Wiring interconnecting terminals 227 and 232 248 Wiring interconnecting terminals 228 and 229 249 Wiring interconnecting terminals 230 and 231 250 Wiring for interconnecting terminals 235 and 240 251 Wiring for interconnecting terminals 236 and 237 252 Wiring for interconnecting terminals 241 and 242 253 Wiring for interconnecting terminals 238 and 239 301, 302 External terminal of IC 303 External terminal 301 and I / O Rock 307
Wiring 304 for connecting the external terminals 301 of the IC and the I / O block 308
305 The external terminal 302 of the IC and the I / O block 309
306 interconnect the external terminal 302 of the IC and the I / O block 310
307-310 I / O block

Claims (4)

[Claims] 2. The semiconductor integrated circuit according to claim 1, wherein said I / O block has means for dividing a driving capability of said I / O block. 2. An I / O block comprising means for variably setting a dimension of a gate of a transistor for determining a driving capability of the I / O block.
A semiconductor integrated circuit, wherein the driving capability of an O block is changed in multiple stages. 3. The semiconductor integrated circuit according to claim 2, wherein a driving capability of an I / O block not directly connected to an external terminal is used separately according to a required driving capability. circuit. 4. The semiconductor integrated circuit according to claim 2, wherein terminals are arranged on gates of said transistors, and gate terminals of a plurality of transistors are interconnected according to required driving capability.