JPH03238917A - semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To revise the load driving capability responding to the utilizing state by including a buffer control means forming selectively a state in which plural output buffers are connected in common to a same terminal. CONSTITUTION:The state of output buffers 18, 19 connected in common to a same terminal is formed to the tip position by controlling the combination of control signals I1-I4 and the load driving capability is increased in response to the user operating state. Moreover, plural switching elements 21-26 are provided on the input/output sides of the output buffers 18, 19 and the combination of the on/off state of the plural switching elements is controlled. Thus, the state of the output buffers 18, 19 connected in common to a same terminal is formed selectively simply.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuit technology and further to a semiconductor integrated circuit that enables parallel connection of output buffers, such as a network processing unit (NPU).
Concerning techniques that are effective when applied to

[Conventional technology]

In logic LSIs such as gate arrays formed by the master slicing method, this technology is used to increase the drive capacity of output buffers without increasing the chip size.
One disclosed in Japanese Patent Application Laid-Open No. 169021/1983 is known. According to this, a first cell for configuring an input buffer circuit and a second cell for configuring an output buffer are provided corresponding to each bonding pad, and selectively input data using a master slice method. In a logic integrated circuit to which a buffer circuit or an output buffer circuit is connected, elements in an unused second cell adjacent to elements in the output buffer 7 circuit are connected in parallel.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology increases the output sofa driving capacity by connecting the elements in the unused second cells in parallel, and this is fixed and is affected in the semiconductor integrated circuit manufacturing process. The inventor of the present invention has discovered that the completed semiconductor integrated circuit has a problem in that the load driving capability cannot be changed depending on the usage status of the user.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit whose load driving capability can be changed according to user usage conditions.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the semiconductor integrated circuit includes buffer control means for selectively forming a state in which a plurality of output buffers are commonly connected to the same terminal.

In addition, in order to easily realize the selective formation of such states, it is possible to provide a plurality of switching elements on the input side and output side of the output buffer, and to control the combination of on/off states of these switching elements. good.

[For production]

According to the above-mentioned means, a state in which a plurality of output sofas are commonly connected to the same terminal is formed under the control of the buffer control means, and this makes it possible to change the load driving capacity according to the user's usage state. It acts on

〔Example〕

FIG. 2 shows an NP (network processing unit) which is an embodiment of the present invention. N P U 1 shown in the figure is 1 by known semiconductor technology.
It is formed on a semiconductor substrate such as a single crystal silicon substrate.

Although the NPUI shown in FIG. 2 is not particularly limited,
Dynamic memory access controller (DMAC) centered on PU24. Multiprotocol Serial Communication Interface (MSCI) 5
, an asynchronous serial communication interface (ASCI) 6, a timer 7, an interrupt control section 8, and other peripheral circuits are installed in an application-specific manner. Each of these functional modules is coupled to a common internal bus 3 including an address bus, a data bus, and a control bus, so that common signals such as data, address signals, and control signals can be exchanged between them. Especially the above MSCI5 and AS
The CI 6 is coupled to a communication line, and data communication using the communication line is possible in a network to which the NPUI is applied.

An example of the individual signals exchanged between the functional modules typically shown in FIG. 2 is an interrupt request signal for the CPU 2.
They are indicated by RQ to IRQ4.

Interrupt request signals IRQL to IRQ4 are output when a predetermined event such as a data transfer error occurs in each functional module, and when they are input to the interrupt control section 8, the CPU 2 performs predetermined interrupt processing.

FIG. 1 shows the configuration of the transmission system in MSCI5. As shown in the figure, the MS CI 5 includes two transmission sections 10.11 and corresponding output buffers 18.11.
19. On the input and output sides of the output buffers 18 and 19, a group of switch elements 12 capable of connecting and disconnecting the signal transmission path are provided.
．． 13 is provided, and the output signal from the transmitter 10.11 is transmitted to a bonding pad (PAD) 14.15 via this switch element group 12.13.

The first switch element group 12 is an N-channel MO8FET provided between the transmitter 10 and the output buffer 18.
21, N-channel type MO5FE-723 provided between the transmitter 11 and the output buffer 19, and those MO5Fs
X installed to bridge the output side of ET21.23
The second switch element group 13 includes an X-channel MOSFET 2 provided between the output buffer 18 and the bonding pad 4.
5. It includes an X-channel type MOSFET 26 provided between the output buffer ↓9 and the bonding pad 15, and an N-channel type MOSFET 24 provided to bridge the output sides of the output buffers 18 and 19.

Furthermore, in order to make the load driving ability programmable, the MSCI 5 includes a control circuit 17 that outputs a 4-bit control signal It-I4 by executing instructions from the CPU 2, and 4-bit control signal circuits 1 to 1 from the control circuit 17. ■According to 4, the drive signals φl to φ of the switch element group 12.13 are
and a drive circuit 16 that generates 6. The drive signal φt is M
The drive signal φ2 is supplied to the OSFET25, and the drive signal φ2 is
The drive signal φ3 is supplied to the MOSFET 26, the drive signal φ4 is supplied to the MOSFET 2, the drive signal φ5 is supplied to the MOSFET 22, and the drive signal φ6 is supplied to the MOSFET 23.

FIG. 3 shows a detailed configuration of the drive circuit 16.

The drive circuit 16 includes NOT circuits 30, 32, 33°35 and OR circuits 31,34. The drive signal φ4 is generated by inverting the control signal ■1 by the knot circuit 30,
The drive signal φ6 is generated by inverting the control signal 2 by the NOT circuit 32, and the drive signal φ5 is generated by obtaining the logical sum of the control signals II and I2 by the OR circuit 3t.

Furthermore, the control signal 13 is inverted by the NOT circuit 33 to generate the drive signal φ1, the control signal I4 is inverted by the NOT circuit 35 to generate the drive signal φ3, and the control signal 13. By obtaining the logical sum of I4 in the OR circuit 34, the drive signal φ2 is generated.

Figure 4 shows the combination of control signals ■↓ to I4 and drive signal φ.
The relationship between φ6 and φ6 is shown.

When all of the control signals 11 to 2 are O (low level),
Drive signal φ1. φ3. φ4. φ6 is set to 1 (high level), and the drive signal φ2. φ5 is set to O. At this time, M
OSFET25, 26°21.23 is turned on,
The output signal from the transmitter 10 is sent to the MOSFET 21. The output signal is transmitted to the bonding pad 14 via the output sofa 18° MOSFET 25, and the output signal from the transmitter 11 is transmitted to the MOSFET 23. Output buffer 19. MOSFET2
6 to the bonding pad 15. That is, in this state, the output signals from the transmitting sections 10.11 can be individually transmitted to the outside via the output terminals.

When the combination of control signals 1 to 4 is 0101, the drive signal φ1. φ2. φ4. φ5 is set to 1, and the drive signal φ3
．． φ6 is set to O. At this time, MOSFET25,2
4, 21, and 22 are turned on, and the output buffers 18.
19 is in a state where it is commonly connected to the bonding pad 4. In other words, the cover sofa 18. '19 are connected in parallel to each other, and the output signal from the transmitter 10 is transmitted to the bonding pad 14 via output buffers 18 and 19. In this state, external output from the transmitter 1↓ is impossible, but the load driving ability at the output terminal corresponding to the bonding pad 14 is
When the driving capacities of the output buffers 18 and 18 are equal to each other, the ratio is increased by a factor of 2 in the case of only the output buffer 18.

When the combination of control signals 1 to I4 is Fool, drive signals φ2 to φ5 are set to 1, and drive signals φl and φ6 are set to O. At this time, MOSFET24.26, 21.2
2 is turned on, and the output buffers 18 and 19 are commonly connected to the bonding pad 15.

That is, output buffers 18 and 19 are connected in parallel, and the output signal from the transmitter 11 is transmitted to the bonding pad 15 via the output buffer sofa 18 and 19. In this state, external output from the transmitter 10 is disabled, but the load driving capability at the output terminal corresponding to the bonding pad 15 is doubled compared to the case where only the output buffer 19 is used. .

When the combination of control signals ■↓ to ■4 is O↓10, the drive signals φ↓, ψ2. φ5. It is assumed that φ6 is (, and the drive signal ψ3
．． φ4 is set to O. At this time, MO5FET25,2
4, 22, and 23 are turned on, and the cover sofa 18.
19 are commonly connected to the bonding pad L4, and in this state, the external output from the transmitter 11 is sent to the bonding pad 1 via the output buffer (8, ↓9).
-14. In this case as well, transmitter 1
Although external output from 0 is impossible, the load driving capability at the output terminal corresponding to the bonding pad 14 is doubled compared to the case where only the output buffer 8 is used.

When the combination of control signals 11 to 4 is 1010, the drive signal φ2. φ3. φ5. φ6 is set to Y, and the drive signal φl
, φ4 is set to O. At this time, MO5FET24,2
6, 22, and 23 are turned on, and the output buffers 18.
19 are commonly connected to the bonding pad 5, and in this state, the output signal from the transmitter 11 is transmitted to the bonding pad 15 via the output sofa 18 and 19. In this case as well, the transmitter 10
However, the load driving capability at the output terminal corresponding to the bonding pad 15 is doubled compared to the case of only the output buffer 19.

Although there are other combinations of control signals 1 to I4, only the combinations described above are used, and the rest are unused.

According to the above embodiment, the following effects can be obtained.

(1) By controlling the combination of control signals ■↓ to step 4, it is possible to selectively create a state in which the output buffers 18 and 19 are commonly connected to the same terminal, and the load driving capacity can be used by the user. It can be increased depending on the situation.

(2) Due to the effect of (1) above, the load driving capacity can be increased depending on the user's usage conditions, which is advantageous in the design and manufacture of NP-mounted boards.

(3) A plurality of switch elements 21, 22.23 and 24.25.2 on the input side and output side of the output sofa 18.19.
6 is provided, and by controlling the combination of on/off states of the plurality of switch elements, it is possible to easily realize selective formation of a state in which the output buffers 18 and 19 are commonly connected to the same terminal. I can do it.

(4) Furthermore, in an application-specific NPU where the only specification that can be changed is whether or not to use a standard module, by making the load driving ability programmable, it is possible to satisfy the user's requirements regarding the load driving ability.

(5) If there is no need to further increase the load driving capacity, the output buffer circuits can be operated individually, so when the elements in the output buffer circuit are connected in parallel using a master slice as in the conventional technology. The output terminals can be used more effectively than in the previous case.

Although the invention achieved by the present inventor has been specifically described above based on examples, it is to be noted that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Not even. For example, in ASCI 6 as well, the load driving capacity may be set programmably as in the above embodiment. Also, 2 in the same module
an output buffer 18 corresponding to the transmission section 10.11 of the system;
Instead of 19 parallel connections, output buffers in other modules may be used to realize parallel connection of the output sofas. Furthermore, three or more output buffers may be programmably connected in parallel.

In the above explanation, the invention made by the present inventor was mainly applied to NPU, which is the background application field, but it is not limited to this, and examples include CPU (Central Processing Unit) and microcomputer. It can also be widely applied to semiconductor integrated circuits such as. The present invention can be applied to conditions that include at least an output buffer.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, a state in which a plurality of output sofas are commonly connected to the same terminal can be created under the control of the buffer control means, and thereby the load driving capacity can be changed according to the user's usage state.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of an NP which is an embodiment of the present invention. Fig. 2 is an overall configuration block diagram of an NPU that is an embodiment of the present invention, Fig. 3 is a detailed circuit diagram of the drive circuit shown in Fig. 1, and Fig. 4 is a combination of control signals. FIG. 3 is an explanatory diagram of the relationship between and a drive signal. 1...NPU, 2...CPU, 5...MSC1,
6.ASCI, to, 11...transmission section, 12.13...
・Switch element group, 14.15...Bonding panel. 16... Drive circuit, 17... Control circuit, 18.19
...Output buffer, 21, 22, 23, 24, 25+
26・MOSFET, ll-I4-・Control signal, φ1
~φ6... Drive signal, 30, 32, 33.35... Not circuit, 31.34... OR circuit 5th, Figure 1

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit comprising a plurality of output buffers arranged to individually correspond to output terminals, and in which signals are transmitted via the output buffers, a plurality of output 1. A semiconductor integrated circuit comprising buffer control means for selectively forming a state in which buffers are commonly connected to the same terminal. 2. A plurality of switch elements capable of connecting and disconnecting signal transmission paths are provided on the input side and output side of the output buffer, and the combination of on/off states of the switch elements is controlled by the buffer control means. 2. The semiconductor integrated circuit according to claim 1, wherein the output buffers are commonly connected to the same terminal. 3. The semiconductor integrated circuit according to claim 1 or 2, which is formed by an application specific method.