JPH1069401A - Emulator device - Google Patents

Abstract

(57) [Summary] [Problem] There is a problem that it is not easy to grasp a program execution path to a current address indicated by a program counter when a program execution is broken. SOLUTION: Trace information storing means for storing various kinds of information when a branch instruction is executed, detecting the execution of the branch instruction and execution of a return instruction, and detecting the trace information when the execution of the return instruction is detected A branch / return instruction execution detection circuit for deleting the latest various information stored in the storage means from the trace information storage means, and a request from the host computer for the various information stored in the trace information storage means And a trace information reference circuit that makes it possible to refer to the information based on the trace information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator device capable of efficiently developing a microcomputer system.

[0002]

2. Description of the Related Art In microcomputer system program development, an emulator device is used as a support system for finding and correcting errors in a program. FIG. 4 is a system configuration diagram showing the configuration of a conventional emulator device. In the figure, reference numeral 1 denotes a host computer for controlling the emulator device 3; and 2, a communication for transmitting and receiving commands and data to and from the host computer 1. A cable 3, an emulator device for debugging by executing a program operating on the target system 4, a target system 4, which constitutes a microcomputer, and a probe device 5, connected between the target system 4 and the emulator device 3. is there. The tip of the probe device 5 has the same shape as a CPU (microcomputer) package on the target system 4 and is connected to a socket of the CPU.

FIG. 5 is a block diagram showing the internal configuration of the emulator device 3. In the figure, reference numeral 11 denotes an emulation microcomputer, and 12 denotes an emulation for storing an object program in a machine language converted from a source program by a host computer 1. Memory. 13 is a system bus, 14 is a monitor circuit that interprets commands issued from the host computer 1 and performs processing according to the interpretation, and controls each unit of the emulator device 3, and 15 is a monitor circuit for controlling the system bus 13. It is a bus control circuit.

This emulator has a function of executing a program and a function of referring to a state of a target system and an internal state of a microcomputer. The program execution function is a function capable of executing a program created by the host computer on the target system without storing a program for operating the target system in the ROM. Further, the function of referring to the state of the target system or the internal state of the microcomputer allows the program to be executed intermittently by using a break function that stops the execution of the program halfway, and the state of the target system or the register of the microcomputer to be executed. It is a function to monitor the internal state such as.

Next, the operation will be described. First, debug software operating on the host computer 1 is started, and the emulator device 3 is controlled by performing an operation using the debug software. At this time, an object program converted from a source program created using a compiler into a machine language is stored in the host computer 1. When a command is issued from the host computer 1 by an operation of the debug software, the monitor circuit 14 interprets the command,
The processing according to the interpretation is executed. In this process, an object program converted into a machine language sent from the host computer 1 is received and stored in the emulation memory 12. Then, the conditions set in advance by the user in the host computer 1 are set in the respective circuits. Thereafter, the program stored in the emulation memory 12 is transferred to the emulation microcomputer 1.
1 and the user proceeds with debugging while breaking the program execution as necessary. At this time, the monitor circuit 14 controls the system bus 1 by the bus control circuit 15.
3 is controlled.

[0006]

Since the conventional emulator device is configured as described above, the program operation through any path up to the current address indicated by the program counter when the program execution is broken is described. There is a problem that it is not easy to confirm whether the process has progressed.

For this reason, when a program is stopped in a subroutine called from a plurality of places, it is necessary to determine the execution state of the stopped subroutine from where the program is called from the stack. Estimation from the return address stored in the stack is necessary.Especially when the stack format such as the arrangement of the return address stored in the stack and the offset from the pointer pointing to the top of the stack is different for each subroutine, There is a problem that the estimating operation is not easy and it is difficult to know a correct return address.

Further, in order to obtain a branch address when branching to a subroutine by the above-mentioned estimating operation, a calculation inferring from a return address stored in a stack is required, and the calculation is difficult depending on an instruction set of a microcomputer. There was a problem that became.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and makes it easy to grasp the execution path of a program based on trace information on subroutine branches and interrupt branches, thereby efficiently debugging. An object is to obtain an emulator device.

[0010]

According to an embodiment of the present invention, there is provided an emulator device for storing a memory for sequentially storing various information when a branch instruction is executed, and detecting execution of the branch instruction and execution of a return instruction. The various information is stored in the memory based on the detection of the execution of the branch instruction, and the latest various information stored in the memory at that time is stored in the memory based on the detection of the execution of the return instruction. And a trace information reference circuit that enables the various information stored in the memory to be referred to based on a request from the host computer. .

According to a second aspect of the present invention, there is provided an emulator for executing a subroutine branch instruction, executing an interrupt branch instruction, executing a return instruction from a subroutine branch destination, and detecting execution of a return instruction from an interrupt branch destination. A return instruction execution detection circuit is provided.

According to a third aspect of the present invention, there is provided an emulator device comprising an address bus, a data bus,
Branch / return instruction execution detection that monitors the instruction fetch signal and the instruction execution signal to detect execution of a subroutine branch instruction, execution of an interrupt branch instruction, execution of a return instruction from a subroutine branch destination, and execution of a return instruction from an interrupt branch destination. A circuit is provided.

The emulator device according to the present invention, when detecting the execution of a branch instruction, executes various addresses such as an execution address at the time of execution of a subroutine branch instruction and an interrupt branch instruction and index data stored at a predetermined address. When information is stored in a memory and execution of a return instruction from a subroutine branch or execution of a return instruction from an interrupt branch is detected, the latest execution address at the time of execution of the subroutine branch instruction and the interrupt branch instruction stored in the memory. And a branch / return instruction execution detection circuit for deleting the index data.

According to a fifth aspect of the present invention, when the execution address of the branch instruction when the execution of the subroutine branch instruction or the interrupt branch instruction is detected is in the address range set by the monitor circuit, the branch is executed. If the address of the instruction is stored in the memory and the data storage designation information set in the address comparison circuit indicates that various information is stored in the memory, the writing to the address set in the address comparison circuit is read. The data stored in the data storage register is stored in the memory as index data upon detection by the write signal comparison circuit, and the address when the execution of the return instruction is detected is within the address range and the data storage designation If the information indicates that the various information is stored in the memory, the data storage A history data storage circuit having a branch / return instruction execution detection circuit for deleting the address of the latest branch instruction and the index data from the memory based on index data matching the data stored in the register; It is like that.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing the configuration of the history data storage circuit of the emulator device according to the first embodiment. The system configuration of the emulator of the first embodiment is the same as the system configuration of the conventional emulator shown in FIG. 4, and the system configuration of the emulator of this embodiment will be described with reference to FIG. FIG.
In the figure, 31 is an address comparison circuit, 32 is a read / write signal comparison circuit, 33 is a data saving register, 34 is a branch / monitor for monitoring a system bus and status signal lines to detect a subroutine branch instruction or an interrupt branch instruction.
The return instruction execution detection circuit 35 is a memory for storing branch history data. A memory area 36 stores data stored in the data storage register 33.
It is provided within. 36a, 36b, 36c
.. 36g is a memory area for storing data stored in the data storage register 33, and is provided in the memory 35. 37a, 37b, 37c ... 37g
A memory area for storing a program counter value at the time of execution of a subroutine branch execution instruction or an interrupt branch execution instruction, which is provided in the memory 35. 39 is memory 3
5, a monitor circuit (trace information reference circuit) having a function of referring to various information such as the branch history data stored in the host computer 1 based on a request from the host computer 1; A history data storage circuit including a write signal comparison circuit 32, a data storage register 33, a branch / return instruction execution detection circuit 34, and a memory 35.

Next, the operation will be described. First, as initial setting processing before execution of a program, data stored in the memory areas 36a to 36g of the memory 35 when a branch instruction of the program is executed. The situation above (for example,
The emulator device can specify code (numerical value) data (hereinafter referred to as index data) indicating the status of the input / output of the I / O port or the status of the task type when the multitask processing is performed. Is set in the address comparison circuit 31 as a reference for the operation. The reference data is a previously specified memory address where the index data is stored when the branch instruction is executed. For example, a task ID in a program using a real-time OS, a port ID for input / output setting, It may be an address of a control word register of RAM or I / O in which a control word or the like is stored. It is also possible to specify that the index data is not stored in the memory areas 36a to 36g, which is specified by data storage specification information provided from the host computer 1. These data are set in the address comparison circuit 31 by the monitor circuit 39. Further, an address range for detecting execution of a subroutine branch / return instruction or an interrupt branch / return instruction is set from the host computer 1 to the emulator device. This address range is set in the branch / return instruction execution detection circuit 34 by the monitor circuit 39.

After the above-mentioned initialization is completed, the program is executed. During execution of this program, if it is specified that the index data is to be stored in the memory area, the address comparison circuit 31 and the read / write signal comparison circuit 32 monitor the system bus and set the index data in the address comparison circuit 31. When it is detected that the memory has been written to the address, the index data written to the address is transferred to the data storage register 33.

The branch / return instruction execution detection circuit 34 executes a branch instruction when a subroutine branch instruction or an interrupt branch instruction is detected and an address at which the branch instruction is executed is within the set address range. The addresses are stored in the memory areas 37a to 37g, and when index data is specified to be stored, the index data transferred to and stored in the data storage register 33 is simultaneously stored in the memory areas 36a to 36g. In this case, the index data stored in the memory areas 36a to 36g and the address of the executed branch instruction stored in the memory areas 37a to 37g are sequentially stored below the memory 35.

A branch / return instruction execution detection circuit 34
Determines whether an address at which the return instruction is executed is within the set address range when a subroutine return instruction or an interrupt return instruction is detected. As a result, when the address at which the return instruction is executed is within the address range and the instruction to store the index data in the memory area is specified, the latest data that matches the index data stored in the data storage register 33 is used. Memory contents (in this case, the memory contents of the memory areas 36g and 37g)
Is deleted from the memory 35. When it is not specified to store the index data in the memory area, the latest data is deleted.

Therefore, in a program structure in which the nest is deepened by repeating the subroutine branch as shown in FIG. 2, the index data and the address of the branch instruction as shown in FIG. The content (branch address) is deleted. That is, the address "branch C" of the branch instruction to the subroutine S3 stored in the memory 35 is deleted by executing the return instruction "return A" in the subroutine S3, and the address of the branch instruction to the subroutine S2 stored in the memory 35 is deleted. Address "branch B" is a return instruction "return B" in subroutine S2.
Is executed, and the address "branch A" of the first branch instruction stored in the memory 35 is stored in the subroutine S1.
And the address "branch D" of the branch instruction stored in the memory 35 is deleted by executing the return instruction "return D" in the program. The index data in this case is stored in the memory 35 because the data storage specification information specifies that the index data is stored in the memory area. For example, an internal state that is given on a program for a register specified by the reference data,
For example, it is I / O input / output state identification data (for example, “input” when “01”, “output” when “02”), and a state that the user pays attention to when trying to grasp a branch route. Is the information indicating.

When the program breaks at the break point BrP, the memory 35 stores the branch address A and the branch address B above the break point BrP shown in FIG. 3 and the index data thereof. The branch address C has been deleted by the "return instruction A". Therefore, the branch path of the program from the index data or the branch address stored in the memory 35 to the break point BrP can be easily grasped.

Next, a description will be given of a program execution function until returning from a function (subroutine or interrupt routine) whose execution is currently stopped. In this case, when the branch instruction is first executed before executing the program, designation that the index data is not stored in the memory area is performed by the data storage designation information. This designation may be a designation to store the index data in the memory area. In addition, all addresses are set from the host computer 1 to the branch / return instruction execution detection circuit 34 of the emulator device as a range of addresses for detecting execution of the subroutine branch instruction and the subroutine return instruction, or the execution of the interrupt branch instruction and the interrupt return instruction.

After the above initial setting, a break is made in an arbitrary function. Thereafter, the execution of the program until returning from the function whose execution has stopped is performed by acquiring the latest branch address from the memory 35 and executing the program until immediately before executing the first address next to the instruction at that address. Become. That is, the break point is Br in FIG.
If it is P, the latest branch address “branch B” is obtained from the memory 35 and the program is executed until immediately before the execution of the next head address of the instruction at that address.

Next, the function of acquiring the subroutine branch history for each task on the program using the real-time OS by the emulator device of FIG. 1 will be described. First, before executing the program, as an initial setting, the address where the task ID of the currently executing task of the real-time OS is stored is set from the host computer 1 to the address comparison circuit 31 of the emulator device. Also, as an address range for detecting execution of a subroutine branch instruction and a subroutine return instruction, or an interrupt branch instruction and an interrupt return instruction, an address range other than the kernel of the real-time OS is detected from the host computer 1 by the branch / return instruction execution of the emulator device. Set to circuit 34. And
When the interrupt branch instruction and the interrupt return instruction are executed, designation is made that index data is stored in the memory area.

After performing the above initial settings, a break is made in an arbitrary function. At this time, the program counter value at the time of execution of the subroutine branch instruction or the interrupt branch instruction is stored in the memory 35 from the memory area 37a. Further, the task ID that has executed the subroutine branch instruction or the interrupt branch instruction is stored in the memory 35 from the memory area 36a as index data. Therefore, the subroutine branch history and the interrupt branch history for each task can be acquired from the memory 35 for each task number from the program counter value stored in the memory 35 from the memory area 37a.

[0026]

As described above, according to the first aspect of the present invention, a memory for sequentially storing various information when a branch instruction is executed, and an execution of the branch instruction and an execution of a return instruction are detected. Storing the various types of information in the memory based on the detection of the execution of the branch instruction, and retrieving the latest various types of information stored in the memory at that time based on the detection of the execution of the return instruction from the memory. A branch / return instruction execution detection circuit to be deleted, and a trace information reference circuit that makes it possible to refer to the various information stored in the memory based on a request from the host computer. The program execution path when the execution of the program in which the branch operation and the return operation by the branch instruction and the return instruction are complicatedly repeated is broken in the middle of the execution of the program is stored in the memory. Easily can be grasped on the basis of the various types of information,
In particular, the above-mentioned various information when the branch instruction is executed when returning from the branch destination is deleted as the latest various information, and the various information stored in the memory is not returned from the branch destination. Since the various information at the time when the branch instruction is executed is stored in order,
There is an effect that the program execution path during the return can be easily grasped from the various information stored in the memory.

According to the second aspect of the present invention, execution of a subroutine branch instruction, execution of an interrupt branch instruction, execution of a return instruction from a subroutine branch, and execution of a return instruction from an interrupt branch are executed by a branch / return instruction execution detection circuit. Is configured to detect a program execution path when a break in the execution of a program that repeatedly repeats a branch operation by a subroutine branch and an interrupt branch and a return operation from the subroutine branch and the interrupt branch in the middle is performed by the memory. Can be easily grasped based on the various information stored in the subroutine branch and the various information when the branch instruction is executed when returning from the interrupt branch destination is executed as the latest various information. The various types of information deleted and stored in the memory are:
Since various information at the time of execution of a branch instruction that is not returning from the branch destination is stored in order, by referring to the various information stored in the memory, the subroutine branch and the There is an effect that the program execution path during the return from the interrupt branch destination can be easily grasped.

According to the third aspect of the present invention, when the execution of a subroutine branch instruction or the execution of an interrupt branch instruction is detected by monitoring an address bus, a data bus, an instruction fetch signal and an instruction execution signal during execution of a program, various types of information are obtained. When the execution of a return instruction from a subroutine branch or the execution of a return instruction from an interrupt branch is detected, the latest various information stored in the memory at that time is deleted from the memory. With the configuration including the instruction execution detection circuit, the memory is stored in the memory based on the detection of the execution of the subroutine branch instruction or the detection of the execution of the interrupt branch instruction by the address bus, the data bus, the instruction fetch signal and the instruction execution signal during the program execution. According to the various information stored, the subroutine branch instruction and the interrupt branch instruction A program execution path can be easily grasped when a program breaks in the middle of execution of a program in which a branch operation, a subroutine branch destination, and a return operation by the return instruction from the interrupt branch destination are complicatedly performed. In particular, the subroutine branch and the interrupt branch destination can be easily grasped. The various information at the time of execution of the branch instruction when returning from is deleted as the latest various information, and the various information stored in the memory is a branch which is not returned from the branch destination. Since the various information at the time of execution of the instruction is stored in order, the program execution during the return from the subroutine branch or the interrupt branch destination can be performed by referring to the various information stored in the memory. There is an effect that the route can be easily grasped.

According to the present invention, a memory for sequentially storing, as various information, an execution address when a subroutine branch instruction and an interrupt branch instruction are executed and index data stored at a predetermined address, Monitoring the address bus, data bus, instruction fetch signal and instruction execution signal during execution of the program to execute the subroutine branch instruction, execute the interrupt branch instruction,
Detecting the execution of the return instruction from the subroutine branch destination and the execution of the return instruction from the interrupt branch destination, and storing the various information in the memory when detecting the execution of the branch instruction;
When the execution of the return instruction is detected, a branch / return instruction execution detection circuit that deletes the latest various information stored in the memory at that time from the memory is provided. A program execution path when a break in the execution of a program that repeats the branch operation by the interrupt branch instruction and the return operation by the return instruction from the subroutine branch destination and the interrupt branch destination in a complicated manner is stored in the memory. Can be easily grasped on the basis of various information such as the execution address and the index data, and in particular, the various information at the time of execution of the branch instruction when returning from the subroutine branch or the interrupt branch destination is updated. Are deleted as various types of information and stored in the memory, Since the various information at the time of execution of the branch instruction in a state not returning from the state is stored in order, the subroutine branch and the interruption can be performed by referring to the various information stored in the memory. There is an effect that the program execution path during the return from the branch destination can be easily grasped.

According to the invention described in claim 5, when the execution address of the subroutine branch instruction or the execution of the interrupt branch instruction is detected within the address range set by the monitor circuit when the execution of the branch instruction is detected, When the address is stored in the memory, and the data storage designation information set in the address comparison circuit indicates that various information is stored in the memory, writing to the address set in the address comparison circuit is read / write. The data stored in the data storage register is stored in the memory as index data by detection by the signal comparison circuit, and the address when the execution of the return instruction is detected is in the address range and the data storage designation information is When indicating that the various information is stored in the memory, the information is stored in the data storage register. And a history data storage circuit having a branch / return instruction execution detection circuit for deleting the address of the latest branch instruction and the index data from the memory based on the index data matching the data. Therefore, the program execution path at the time of a break during the execution of a program that repeats the branch operation by the branch instruction and the return operation by the return instruction in a complicated manner is determined by the address of the branch instruction stored in the memory and the index data. Can be easily grasped on the basis of various information such as the operating state of the system indicated by the above, and in particular, the various information at the time of execution of the branch instruction when returning from the subroutine branch or the interrupt branch destination is updated. The various information stored in the memory is not restored from the branch destination. Since the various information at the time of execution of the branch instruction in the current situation is sequentially stored, the return from the subroutine branch or the interrupt branch destination can be performed by referring to the various information stored in the memory. There is an effect that the program execution path on the way can be easily grasped.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a history data storage circuit of an emulator device according to Embodiment 1 of the present invention.

FIG. 2 is an explanatory diagram showing a program structure for explaining an operation of the emulator device according to the first embodiment of the present invention;

FIG. 3 is an explanatory diagram showing various information such as index data and branch addresses stored in a memory of the emulator device according to the first embodiment of the present invention.

FIG. 4 is a system configuration diagram showing a conventional emulator device.

FIG. 5 is a block diagram showing an internal configuration of a conventional emulator device.

[Explanation of symbols]

1 host computer, 3 emulator devices, 31
Address comparison circuit, 32 read / write signal comparison circuit, 33 data storage register, 34 branch / return instruction execution detection circuit, 35 memory, 39 monitor circuit (trace information reference circuit).

Claims (5)

[Claims] 1. An emulator for searching for an error in a program applied to a microcomputer system under the control of a host computer, a memory for sequentially storing various information when a branch instruction is executed, The execution and return instructions are detected, the various information is stored in the memory based on the detection of the execution of the branch instruction, and the information is stored in the memory at that time based on the detection of the execution of the return instruction. A branch / return instruction execution detection circuit for deleting the latest various information from the memory, a trace information reference circuit for enabling the various information stored in the memory to be referred based on a request from the host computer; An emulator device comprising: 2. The execution of a branch instruction detected by a branch / return instruction execution detection circuit is the execution of a subroutine branch instruction and the execution of an interrupt branch instruction. The execution of a return instruction detected by the branch / return instruction execution detection circuit is 2. The emulator according to claim 1, wherein execution of a return instruction from a subroutine branch and execution of a return instruction from an interrupt branch are performed. 3. A branch / return instruction execution detection circuit monitors an address bus, a data bus, an instruction fetch signal and an instruction execution signal during execution of a program and detects various types of execution of a subroutine branch instruction or an interrupt branch instruction. When information is stored in a memory and execution of a return instruction from a subroutine branch or execution of a return instruction from an interrupt branch is detected, the latest various types of information stored in the memory at that time are deleted from the memory. Claim 1.
Or the emulator device according to claim 2. 4. Various information stored in a memory when a branch / return instruction execution detection circuit detects execution of a branch instruction is:
The execution address at the time of execution of a subroutine branch instruction and an interrupt branch instruction, and index data stored at a predetermined address. The branch / return instruction execution detection circuit executes a return instruction from a subroutine branch or returns from an interrupt branch. 4. The method according to claim 1, wherein the various information stored in the memory to be deleted when the execution of the instruction is detected are the latest execution address and the index data at the time of execution of the subroutine branch instruction and the interrupt branch instruction. 3. The emulator device according to 3. 5. An address comparison circuit for setting data storage designation information provided from a host computer indicating whether or not various information is stored in a memory and a predetermined address where index data is stored, and a system. A read / write signal comparison circuit for monitoring a read / write signal on the bus; and a write to the address when the read / write signal comparison circuit detects writing to the address set in the address comparison circuit. When the execution of a subroutine branch instruction or an interrupt branch instruction is detected and the address of the executed branch instruction is within a preset address range, the address of the branch instruction is stored. Storing in the memory, the data storage designation information storing the various information in the memory Indicates that the data stored in the data storage register is stored in the memory as index data, and the address when the execution of the return instruction is detected is in the address range, and the data storage designation information is When indicating that information is stored in the memory, the latest address of the branch instruction and the index data thereof are deleted from the memory based on the index data matching the data stored in the data storage register. A history data storage circuit having a branch / return instruction execution detection circuit for executing each execution of a subroutine branch instruction and a return instruction returning from the subroutine branch destination, or an interrupt branch instruction and a return instruction returning from the interrupt branch destination. The address range when the branch / return instruction execution detection circuit detects Emulator device according to claim 1, characterized in that a monitor circuit for setting to the branch-return instruction execution detection circuit.