JPH11111978A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the standby current of an LSI and achieve high integration. SOLUTION: In a MOS structure, a gate insulating film (1) is provided.
The thickness of 5) is less than 3 nm, and the gate electrode (16) is formed of a silicon film containing a heavily doped p-type impurity regardless of the conductivity type of the transistor. Direct tunneling leak current can be reduced, and standby current can be reduced even in the case of high integration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOS transistor suitable for operation under a low power supply voltage.

[0002]

2. Description of the Related Art From the viewpoints of portability and energy saving of electronic devices, there is an increasing demand for reducing power consumption. For this reason, semiconductor devices operating at low voltage have been developed. As one solution, the gate insulating film 3
It has been proposed to apply insulation of a region where a so-called direct tunneling current occurs below nm to a MOS transistor. For example, the author H.S. S. Momose
Other, Source IEDM technology digest, pp. 593-5
96, 1994, or the same author's source IEEE Bulletin, Electronic Devices (Electron Devices),
vol. 43, no. 8, pp. 1233-1242,
1996 and the like.

In such a MOS structure, although the gate current decreases as the gate length becomes shorter, the channel current increases. Conversely, it is known that a normal transistor operation can be performed even with a MOSFET having a fine gate length. .

In the devices described in these reports, the gate electrode is made of n ⁺ type polysilicon. this is,
This is because threshold control in the n-channel MOSFET is easy.

FIGS. 4 and 5 show the characteristics of a MOSFET employing a conventional n ⁺ gate. FIG. 4 is a graph showing the gate current of the n-channel MOSFET when the drain voltage is changed using the gate voltage as a parameter. FIG. 5 is a graph showing the gate current of the p-channel MOSFET when the drain voltage is changed using the gate voltage as a parameter. It is a graph.

[0006]

However, as is apparent from FIGS. 4 and 5, in the conventional fine MOSFET using such n ⁺ -type polysilicon, although the gate current is reduced, the power supply voltage is not increased. When a voltage of 0.5 V is used, a leakage current of about 5 × 10 ⁻⁹ A / μm exists even in a device having a gate length on the order of 0.1 μm. This leak current has a problem that when a large number of such fine MOSFETs are integrated to form an LSI, a standby current is increased and integration is difficult.

The present invention has been made to solve such a problem, and an object of the present invention is to reduce the standby current of a fine transistor and enable high integration.

[0008]

According to the present invention, there is provided a gate electrode formed on a semiconductor substrate via a gate insulating film, and a gate electrode formed on both sides of a channel forming region located immediately below the gate electrode. Wherein the thickness of the gate insulating film is less than 3 nm in terms of a silicon oxide film, and the gate electrode is made of a silicon oxide film containing a p-type impurity. Is what you do.

Preferably, the semiconductor device is a p-channel MOS transistor or a complementary MOS semiconductor device in which the source / drain regions are p-type impurity diffusion layers.

The gate insulating film is a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a tantalum oxide film,
It is preferable to use any one of the strontium titanate films or a laminated film thereof.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below.

FIG. 1 shows the structure of a MOS transistor according to a first embodiment of the present invention, which has a CMOS structure. A p-well 12 and an n-well 13 are formed on the surface of the p-type semiconductor substrate 11, and an element isolation film 14 is formed on a boundary between these.

A part of the surface of each well has a thickness of 2.5 nm.
A gate electrode 16 made of polysilicon containing boron ions at a high concentration is formed via a gate oxide film 15 of this type. Impurity diffusion serving as a source / drain is formed on both sides of a channel region in the semiconductor substrate immediately below the gate. A region is formed. That is, in the p well 12, n ⁺ impurity diffusion regions 17 serving as a source and a drain, respectively,
18 are formed so as to be separated from each other by a channel region to form an n channel M
An OS transistor is formed, and ap ⁺ impurity diffusion region 1 serving as a source and a drain is formed in the n well 13.
9 and 20 are formed to be separated from each other by a channel region to form a p-channel MOS transistor. Note that a high melting point metal silicide film 21 may be formed on the upper surface of the gate electrode 16 to reduce the resistance.

Although such a positional relationship is similar to that of the conventional MOS transistor, in this embodiment, the thickness Tox of the gate oxide film is less than 3 nm in terms of a silicon oxide film, and the gate electrode is It is characterized in that it contains p ⁺ -type impurities irrespective of the conductivity type of the transistor.

The semiconductor device shown in FIG. 1 can be manufactured as follows using a well-known manufacturing technique.

After a p-well and an n-well are formed on the surface of a p-type silicon substrate, LOCOS, which is a selective oxidation method, is used.
Element isolation is performed by a method, and an impurity is introduced into a region where a channel is to be formed so that a desired threshold voltage is obtained.

Next, gate oxidation is performed. In order to obtain a thin gate oxide film, gate oxidation is performed by a rapid lamp heating method (RT
O: Rapid Thermal Oxidation). The oxidation conditions are, for example, the following conditions: Tox = 2.5 nm at 900 ° C. for 5 seconds Tox = 2.8 nm at 900 ° C. for 20 seconds Tox = 1.5 nm at 800 ° C. for 10 seconds Gate oxidation of less than 3 nm, such as Tox = 1.5 nm A film is obtained.

Next, a polysilicon film is deposited to a thickness of 100 nm by CVD or the like while containing boron (B). In order to contain such impurities, for example, C
When depositing polysilicon by the VD method, it can be realized by mixing an appropriate amount of a doping gas such as diborane (B ₂ H ₆ ).

Next, if a resist is applied and patterned, and the polysilicon film is etched using the patterned resist as an etching mask, a p + type gate electrode is formed.

Thereafter, using the obtained gate electrode as an ion implantation mask, n-type and p-type impurities are introduced into the source / drain regions of the NMOS and the PMOS at a high concentration by ion implantation, and a heat treatment for activation is performed. Thus, source / drain regions are formed.

Subsequently, an interlayer insulating film is deposited, a contact hole is opened in each electrode portion, and a wiring is formed. This wiring is usually made of polysilicon in which impurities are diffused, but high-speed operation at high frequencies is achieved by lowering the resistance using a technique of attaching a metal on the wiring or forming a high-melting-point metal film and then silicidation. Enables operation.

In the present invention, a gate current is reduced by employing a p-type silicon gate electrode in such a minute gate structure.

FIG. 2 shows an n-channel MOS transistor (N
FIG. 3 is a graph showing a change in gate current with respect to a gate length when a gate electrode is an n ⁺ gate electrode and a p ⁺ gate electrode for each of a p-channel MOS transistor (P-MOSFETS) and a p-channel MOS transistor (P-MOSFETS);
Is a graph showing the ratio (Ig / Id) of the gate current to the drain current when the gate length is changed for the same combination, that is, the change in the leak current.

According to these graphs, in a fine device having a gate width of 0.15 μm, an n-channel MOS
In the transistor, a leakage current on the order of 0.1 μA / μm is observed. However, in the p-channel MOS transistor, the leakage current level is very small, on the order of 1 pA / μm, and there is a difference of about 5 digits in the same transistor as compared with the n-channel MOS transistor. This is because the direct tunneling associated with the thin gate oxide film prevents electrons in the n-channel MOS transistor from flowing into the drain, thereby reducing the overall leakage current. In addition, the reason why the p-type silicon electrode is used is that a current does not easily flow because the band gap is different from that in the case of the n-type silicon electrode, and the leak current is further reduced.

In the above embodiment, a CMOS type semiconductor device has been described as an example.
The present invention can be applied to a semiconductor device in which only one of a transistor and a p-channel MOS transistor is formed. In either of these cases,
The thickness of the gate insulating film is less than 3 nm, and the gate electrode is made of p-type polysilicon.

Although a silicon oxide film is used as the gate insulating film in the embodiment, an insulating film having the same gate capacitance can be used. Examples of such an insulating film include a silicon nitride film (Si ₃ O ₄ ), a silicon nitride oxide film (SiO _x N _y ), and a laminated film of a silicon nitride film and an oxide film (for example, SiO ₂ / Si ₃ N ₄ , Si ₃ N ₄ / Si
O ₂ , SiO ₂ / Si ₃ N ₄ / SiO ₂ , Si ₃ N ₄ /
SiO ₂ / Si ₃ N ₄ ), tantalum oxide (TaO _x ), strontium titanate (TiSr)
_x O _y ), a stacked film of these and a silicon oxide film or a silicon nitride film, or the like can be used. It is necessary that the capacitance of these insulating films is less than 3.0 nm in terms of a silicon oxide film. The conversion to the silicon oxide film can be easily obtained by substituting the dielectric constant of the material into a well-known conversion formula.

Of these various films, a silicon oxide film is the most common and is easy to manufacture, a silicon nitride film is second only to this, and a tantalum oxide film can be formed thick because of its high dielectric constant. The reliability and yield of the film can be improved.

In the above embodiment, the n-channel MOSFE
Although the thickness of the gate insulating film is the same between T and the p-channel MOSFET, it can be changed to optimize the characteristics. For example, 1000 p-channel MOSFETs
After obtaining a gate insulating film pressure of approximately 3.0 nm under the condition of 10 ° C. and 10 seconds, the gate insulating film is peeled off only in the n-channel MOSFET formation region, and for example, Tox = 1.5 nm is obtained under the condition of 800 ° C. and 10 seconds. You can do so. This is because the effect of direct tunneling is remarkable in the p-channel MOSFET.

[0029]

As described above, according to the present invention, the MOS
In the structure, the thickness of the gate insulating film is less than 3 nm, and the gate electrode is formed of a silicon film containing a p-type impurity doped at a high concentration irrespective of the conductivity type of the transistor. The band structure between the silicon substrates changes, so that the direct tunnel leak current can be reduced, and the standby current can be reduced even in the case of high integration.

[Brief description of the drawings]

FIG. 1 is an element cross-sectional view showing one embodiment of a semiconductor device according to the present invention.

FIG. 2 shows that the gate of each of an n-channel MOS transistor and a p-channel MOS transistor is n ⁺
6 is a graph showing the effect of adopting a p ⁺ gate in the present invention by showing a change in gate current with respect to a gate length when a gate electrode and a p ⁺ gate are used.

FIG. 3 is a graph showing the effect of adopting the p ⁺ gate in the present invention by showing the ratio of the gate current to the drain current when the gate length is changed, that is, the change in the leak current.

FIG. 4 is a graph showing a gate current of an n-channel MOSFET when a drain voltage is changed using a gate voltage as a parameter.

FIG. 5 is a graph showing a gate current of a p-channel MOSFET when a drain voltage is changed using a gate voltage as a parameter.

[Explanation of symbols]

Reference Signs List 11 p-type semiconductor substrate 12 p-well 13 n-well 14 element isolation film 15 gate insulating film 16 gate electrode 17, 18 n ⁺ diffusion layer 19, 20 p ⁺ diffusion layer 21 metal silicide film

Claims (4)

[Claims] 1. A semiconductor comprising: a gate electrode formed on a semiconductor substrate via a gate insulating film; and a source / drain region formed in the substrate on both sides of a channel formation region located immediately below the gate electrode. In the apparatus, the thickness of the gate insulating film is 3 nm in terms of a silicon oxide film.
And the gate electrode is made of a polysilicon oxide film containing a p-type impurity. 2. The semiconductor device according to claim 1, wherein said semiconductor device is a p-channel MOS transistor in which said source / drain region is a p-type impurity diffusion layer. 3. The semiconductor device according to claim 1, wherein the p-channel MOS transistor whose source / drain region is a p-type impurity diffusion layer and the n-channel MOS transistor whose source / drain region is an n-type impurity diffusion layer are on the same substrate. 2. The semiconductor device according to claim 1, wherein the complementary MOS semiconductor device is provided above, and each of the conductive MOS transistors has a gate electrode made of a polysilicon oxide film containing a p-type impurity. apparatus. 4. A gate insulating film comprising a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a tantalum oxide film,
4. The semiconductor device according to claim 1, wherein the semiconductor device is made of one of a strontium titanate film and a laminated film thereof.