JPH11119992A - Trace controller for firmware - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a trace controller for firmware which can flexibly deal with the change of trace data or trace system to be sampled, capable of sampling a large number of trace data and can easily analyze a factor when some faults occur in a firmware. SOLUTION: This device is provided with 1st and 2nd mode registers 12 and 14 for storing mode data, while receiving the service of a service processor 20, the fault detecting signal of a hardware fault detect circuit 15 is inputted to the 2nd mode register 14, a trace interrupting instruction is transmitted from an interrupt register 13 to a firmware 11 together with the mode data in the 1st mode register 12, and an instruction and the fault detecting signal stored in the 2nd mode register 14 related to communication trace or target trace are transmitted. A data storage area in a main storage device 30 can be used while selecting either divided use or occupied use. When the fault detecting signal is reported, the firmware 11 stops trace processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a firmware trace control device for performing a trace process on firmware for controlling an input / output control device of a computer.

[0002]

2. Description of the Related Art At present, HIPPI is used as an interface for an input / output device of a supercomputer. By using this as a PCI bus, it is possible to connect an interface card for a general-purpose interface and peripheral devices to the supercomputer. It becomes possible. On the other hand, the control of the input / output control device is performed by stored firmware, and when a specific process is executed, the operation status of the firmware is monitored and checked. The trace processing stored in the main storage device is performed.

If it becomes possible to connect a peripheral device for a general-purpose interface, the control of the input / output device becomes complicated and the amount of trace processing increases. For this reason, it is required that a large amount of trace data can be collected, and that it is possible to flexibly cope with changes in the trace data to be collected and the trace method. Incidentally, as a conventional firmware tracing method of this type, there is a method described in Japanese Patent Application Laid-Open No. 2-230335.

The firmware tracing method described in the above publication discloses a save area for temporarily saving instructions, a first holding area for holding an address of firmware for starting a trace routine, and a plurality of types of trace routines. A second holding area for holding a plurality of branch instructions for branching, a plurality of types of trace routines, first means for detecting when the start or end of the trace is instructed by the service processor; Second means for judging whether or not to stop the subsequent tracing according to the content of the collected data, and when the first means detects an instruction to start tracing, the address from the first holding area is read from the first holding area. To read the instruction stored at the address, and write the instruction to the save area. By reading the first branch instruction branching from the second holding area to the first trace routine and writing the first branch instruction to the address read from the first holding area, When the first means detects an instruction to end the trace, or when the second means determines to stop the trace, the instruction written in the save area is executed. It is configured to read and write to the area indicated by the address held in the first holding area.

That is, when the start of tracing is started from the service processor, a predetermined address in the firmware is rewritten to a branch instruction for executing a trace routine stored in the second holding area. Store the instruction in the save area. When the branch instruction is executed by executing the program, a trace routine corresponding to the branch instruction is executed. When the end of the trace is instructed from the service processor, the instruction stored in the save area is executed to end the trace. Then, the type of a subsequent trace is changed according to the trace data collected during the execution of the trace routine.

[0006]

However, in the above-described conventional firmware tracing method, a plurality of types of tracing routines are provided in advance, and one of the tracing routines is executed and collected by an instruction from the service processor. Since a trace routine to be further executed is selected according to the trace data obtained, only trace data related to the predetermined trace data can be collected. There is a possibility that flexible responses cannot be made. Further, when a failure occurs in the firmware program, the trace is stopped, the trace data collected so far is stored, and the analysis is performed for the failure, but the hardware has failed. In this case, since the collection of trace data is continued, it is not possible to cope with the failure, and it may be impossible to analyze the cause of the failure. That is,
Since the trace data is stored continuously only in a predetermined area of the storage device, only a certain amount of data can be held. Therefore, if a failure occurs and the tracing process is stopped,
There is a possibility that the trace data required for the analysis of the failure is overwritten, and a sufficient analysis cannot be performed.

Accordingly, a first object of the present invention is to make it possible to easily change the type of trace and to flexibly cope with a change in trace data to be collected or a change in a trace method. It is a second object of the present invention to collect trace data that can cope with a hardware failure. Further, a third object is to ensure that even if a large amount of trace data is required, the trace data can be collected and held, so that it is possible to reliably cope with the analysis of the cause of the failure.

[0008]

According to a first aspect of the present invention, there is provided a firmware trace control apparatus, comprising: mode data relating to interrupt processing input from a service processor; And a second mode register for storing mode data relating to trace processing input from the service processor and outputting a trace processing signal to the firmware.
A mode register, an interrupt register to which mode data stored in the first mode register is input and outputting an interrupt signal to firmware, and a trace data sampled based on a trace processing instruction of the second mode register are stored. And a trace data storage device.

The trace mode is changed by changing the trace processing instruction input to the second mode register. For this reason, the trace data to be collected and the trace method can be changed by an input operation from the outside, and it is possible to flexibly respond to these changes.

The firmware trace control device according to the second aspect of the present invention provides a firmware trace control device according to the second aspect of the present invention so that when a hardware failure occurs, the cause of the failure can be analyzed. A hardware failure detection circuit that detects a hardware failure and sends a hardware failure occurrence signal to the second mode register; when the hardware failure occurrence signal is input, the firmware The tracing process is stopped.

When a hardware failure occurs,
When the occurrence of a failure is detected by the hardware failure detection circuit and a hardware failure occurrence signal is input to the second mode register, the second mode register instructs the firmware to stop the tracing process and executes the firmware. Stop all trace processing that is being performed.
Therefore, the trace data collected up to the time when the hardware failure occurs is retained, and can be used for analyzing the cause of the failure occurrence.

Further, in order to be able to cope with a large amount of trace data, the firmware trace control device according to the present invention, wherein the trace data storage device includes a plurality of trace data storage devices provided in a main storage device. An area and a trace data storage memory, and select part or all of the trace data storage area of the main storage device by an interrupt signal of the first mode register and trace the selected area to the selected storage area. Data is stored, and when the trace data storage area of the main storage device cannot be used, the trace data is stored in the trace data storage memory.

That is, the trace data storage area allocated to each control target for which trace data is to be collected in the main storage device can be used only for a single target as required. As a result, a large storage area can be used according to the control target from which trace data is to be collected, and a large amount of trace data can be collected and held. Further, when the main storage device cannot be used, the trace data is stored in the trace data storage memory, so that the trace data can be reliably collected and held.

According to a fourth aspect of the present invention, there is provided a trace control device for firmware, wherein a first mode register for storing mode data relating to interrupt processing input from the service processor, and a mode data relating to trace processing input from the service processor. A second mode register that outputs a trace processing signal to the firmware; an interrupt register that receives the mode data stored in the first mode register and outputs an interrupt signal to the firmware; Detect
A hardware failure detection circuit for sending a hardware failure occurrence signal to the second mode register; an appropriate number of trace data storage areas allocated in the main storage device for storing collected trace data; A trace data storage memory for storing the trace data when the data cannot be stored in the storage device, wherein a divided use in which the trace data storage area is used for each area and an exclusive use in which all the areas are occupied are used. When the hardware failure occurrence signal is input, the firmware stops all the trace processing being executed.

By changing the mode data input from the service processor to the second mode register, it is possible to change the trace data to be collected and the trace method. Further, when the hardware failure is detected by the hardware failure detection circuit, the tracing process is stopped, so that the trace data collected so far can be retained, and the cause of the failure can be analyzed. Furthermore, by selecting whether to divide or occupy the trace data storage area allocated inside the main storage device, a large area can be used according to the control target of the trace processing, and a large amount of trace data can be collected. , Can be held.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a firmware trace control device according to the present invention will be specifically described based on the illustrated preferred embodiments.

FIG. 1 is a block diagram schematically showing a hardware configuration of a firmware trace control device according to the present invention. The firmware trace control device includes a firmware control device 10 including firmware 11 for controlling the input / output control device, a service processor 20 for input from the outside, and a trace data storage area for partially storing trace data. And a main storage device 30 provided with

The firmware controller 10 includes the firmware 11, a first mode register 12, an interrupt register 13, a second mode register 14, a hardware fault detection circuit 15, and a trace data storage memory 16. First
The mode register 12 receives a mode data signal relating to interrupt processing sent from the service processor 20. The first mode register 12 holds the mode data signal and sends it to the interrupt register 13. When the mode data signal is input to the interrupt register 13, a trace interrupt occurs and instructs the firmware 11 to perform a trace interrupt process. The second mode register 14 receives the mode data signal relating to the trace processing transmitted from the service processor 20 and the hardware failure detection signal transmitted from the hardware failure detection circuit 15. Holds these signals and sends them to the firmware 11. The hardware failure detection circuit 15 sends the hardware failure detection signal to the second mode register when a failure such as a failure occurring in the hardware of the firmware control device 10 is detected.
Send to 14. The trace data storage memory 16 stores the trace data collected by the trace processing executed on the firmware 11 instead of the main storage device 30.

The trace data storage area provided in the main storage device 30 is allocated to each input / output control device controlled by the firmware 11, as shown in FIG. For example, the trace data at the time of executing the control for the first device is stored in the first device trace data storage area 31, the trace data at the time of executing the control for the second device is stored in the second device trace data storage area 32, and the third data is stored in the third device. For the device, the third device trace data storage area 33
Meanwhile, the data for the fourth device is stored in the fourth device trace data storage area 34, and when the area is designated and the trace data is collected, the other area is not used. Even in this case, the data is stored only in the designated trace data storage area. As shown in FIG. 5B, all of the trace data storage areas 31 to 34 can be used only for storing trace data in a certain device. For example, all of the trace data storage areas 31 to 34 can be used only for storing the trace data of the first device. In this case, the trace data executed and collected for the second to fourth devices are respectively The trace data cannot be stored in the trace data storage area, and these trace data are stored in the trace data storage memory 16.

When the service processor 20 issues a trace start instruction, the first mode register 12 and the second mode register 12
Mode data is input to and stored in each of the mode registers 14. The first mode register 12 stores a trace data storage area of the main storage device 30 with respect to the input / output control device (first device) which is a control target for performing the trace processing.
Whether only 31 to 34 are occupied and used, ie, exclusive use, or all use of the trace data storage area is prohibited, ie, use is prohibited, and only the first device trace data storage area 31 is used. The trace area setting instruction, whether to use the divided data, the trace data transfer instruction for transferring the trace data stored in the trace data storage memory 16 to the main storage device 30, and the hardware information. HW to be transferred to main storage 30
The information transfer instruction is stored. Further, the second mode register 14 includes a communication trace instruction for executing a trace on communication data with the input / output control device, and firmware information on the execution of the predetermined processing of the firmware 11 as a trace target. The target trace instruction to be collected and the process number of the process targeted for the target trace are stored.

The operation of the firmware trace control device according to the present invention configured as described above will be described with reference to the flowcharts of FIGS.

FIG. 2 is a flowchart of the interrupt processing of the firmware 11. If there is a timer interrupt in the interrupt register 13, the timer interrupt is read (step 201), and an instruction to generate a timer interrupt is issued (step 202). It is executed (Step 203). When an instruction relating to the trace processing is sent from the service processor 20, mode data is stored in each of the first mode register 12 and the second mode register 14. When mode data is stored in the first mode register 12, the interrupt register
13, a trace interrupt is generated and read out (step 201), and it is determined whether or not trace interrupt processing has occurred (step 204). This determination is affirmed, and the first mode register processing relating to the trace is executed (step 201). 205).

When the first mode register process is started,
As shown in FIG. 3, the instruction stored in the first mode register 12 is read (Step 302). It is determined whether or not the trace area has been changed (step 303). If so, a trace area setting process for setting whether or not the specified trace area can be used is executed (step 30).
4) After resetting the interrupt factor (step 31)
1), the process ends (step 312). If the determination in step 303 is negative, it is determined whether the trace area is occupied (step 305). If the trace area is occupied, the trace data and the HW information stored in the trace data storage memory 16 are determined. Trace data transfer processing (step 306) for transferring
After performing the log transfer process (step 307) and resetting the interrupt factor (step 311), the process ends (step 312). If the determination in step 305 is negative, the trace data storage area is to be divided and used, so it is determined whether or not the instruction is a transfer instruction for trace data (step 308). If so, the transfer processing for transferring the trace data to the designated trace data storage area in the main storage device 30 is performed (step 309), the interrupt factor is reset (step 311), and the processing ends (step 312). ). If the instruction is not a trace data transfer instruction, the instruction is an HW information transfer instruction, so that HW log transfer processing for transferring HW information to a designated trace data storage area is performed (step 310), and after resetting an interrupt factor (step 310). Step 311), and the process ends (Step 312).

When an interrupt process relating to a trace process occurs in the interrupt register 13, the occurrence of the interrupt process is determined (steps 206 and 209), and a trace information collecting process is executed (steps 207 and 210). FIG. 4 shows a flowchart of the trace information collecting process. When the trace information collection process is started, the firmware 11 reads the contents stored in the second mode register 14.
It is determined whether or not the read mode data is a communication trace instruction (step 402). If the mode data is a communication trace instruction, a communication trace for collecting communication data with the input / output control device and trace data during communication processing. An information collection process is executed (Step 403). At this time, trace data relating to other processes is not collected. If it is not a communication trace instruction in step 402, it is determined whether or not it is a target trace instruction (step 404). If the instruction is a target trace instruction, target trace information collection processing is executed (step 405). In this target trace information collecting process, the process number to be traced is read from the second mode register 14, and if the process being executed at that time is a process corresponding to this process number, the trace data at that time is collected. If not, the process ends without executing the trace processing. If the instruction is not a target trace instruction, it is determined whether or not the information read from the second mode register 14 is hardware failure occurrence information (step 406). All trace processing is stopped (step 407). If it is not hardware failure occurrence information, trace data is collected in all processes (step 408).

Then, the steps 403 and 4
05, if the trace data is collected in any of the steps 408, it is determined whether or not the trace data storage area of the main storage device 30 can be used (step 409). If the trace data storage area can be used, the collected trace data is designated. Transferred to the specified trace data storage area
After being stored in the trace data storage memory 16 (step 41), the collected trace data is transferred and stored in the trace data storage memory 16 (step 41).
1), the process ends (step 412).

When the trace information collecting process is completed,
An interrupt process corresponding to the interrupt instruction (steps 206 and 209) is executed (steps 208 and 211).

[0027]

As described above, according to the firmware trace control device of the first aspect of the present invention, it is possible to change the trace processing instructed by changing the mode data input to the mode register. Therefore, it is possible to easily change the trace data and trace method to be collected by an external input operation,
It is possible to flexibly deal with various trace processes.

Further, according to the firmware trace control device of the present invention, when a failure occurs in the hardware, all the trace processes executed by the firmware are stopped. The trace data collected is stored without being overwritten, and can be used for failure analysis.

According to the third aspect of the present invention, the trace data storage area in the main storage device can be changed and used for divided use and exclusive use. When the trace data storage area cannot be used, the trace data storage memory can be used, so that a large amount of trace data can be collected and held.

Further, according to the firmware trace control device of the present invention, the trace data to be collected and the trace method can be easily changed, and even if a hardware failure occurs, the trace until the failure occurs can be traced. The data can be retained and used for analysis of the cause of the failure, and even if a large amount of trace data can be collected and retained.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing hardware of a firmware trace control device according to the present invention.

FIG. 2 is a flowchart of a firmware interrupt process.

FIG. 3 is a flowchart of a firmware trace interrupt process.

FIG. 4 is a flowchart of firmware trace processing.

5A and 5B are diagrams showing a trace data storage area provided in the main storage device. FIG.
Indicates the case of exclusive use.

[Explanation of symbols]

 10 Firmware controller 11 Firmware 12 First mode register 13 Interrupt register 14 Second mode register 15 Hardware failure detection circuit 16 Trace data storage memory 20 Service processor 30 Main memory 31 Trace data storage area for first device 32 Second device Trace data storage area for device 33 Trace data storage area for third device 34 Trace data storage area for fourth device

Claims (4)

[Claims] 1. A first mode register for storing mode data relating to interrupt processing input from a service processor, and a second mode register for storing mode data relating to trace processing input from a service processor and outputting a trace processing signal to firmware. A mode register; an interrupt register to which the mode data stored in the first mode register is input and outputting an interrupt signal to firmware; and a trace data collected based on a trace processing instruction of the second mode register. And a trace data storage device. 2. A hardware failure detecting circuit for detecting a hardware failure and sending a hardware failure occurrence signal to the second mode register is provided. When the hardware failure occurrence signal is input, the firmware is executed. 2. The firmware trace control device according to claim 1, wherein all trace processing is stopped. 3. The trace data storage device includes a plurality of trace data storage areas provided in a main storage device and a trace data storage memory, and the trace data in the main storage device is generated by an interrupt signal of the first mode register. Select part or all of the storage area and store the trace data in the selected storage area. If the trace data storage area of the main storage device cannot be used, the trace data is stored in the trace data storage memory. 2. The firmware trace control device according to claim 1, wherein 4. A first mode register for storing mode data relating to interrupt processing inputted from the service processor, and a second mode register for storing mode data relating to trace processing inputted from the service processor and outputting a trace processing signal to the firmware. A mode register, an interrupt register to which mode data stored in the first mode register is input and outputting an interrupt signal to firmware, a hardware failure detected, and a hardware failure occurrence signal transmitted to the second mode register. A hardware failure detection circuit to be sent to the main storage device, an appropriate number of trace data storage areas allocated in the main storage device for storing collected trace data, and a trace data storage device when the trace data cannot be stored in the main storage device. Trace data storage memo to be stored And selectively allowing divided use in which the trace data storage area is used for each area and exclusive use in which all areas are occupied, and when the hardware failure occurrence signal is input, A firmware trace control device, wherein the firmware stops all trace processing being executed.