JPH01158541A - Program travelling route collecting system - Google Patents

Abstract

PURPOSE:To freely refer with a trouble processing program by a arithmetic processing unit by preserving the travelling route of a program until an abnormality occurs at the program execution with the arithmetic processing unit, into a main memory. CONSTITUTION:A trace memory 4 composed of plural words to respond to the access from an arithmetic processing unit 1 to a main memory 2 and store the information related to the access is connected onto a processor bus 3 to connect the arithmetic processing unit 1 and the main memory 2. A means 5 to stop the storing of the information to a trace memory 4 with a signal 9 sent from the arithmetic processing unit 1 and transfer the information stored into the trace memory 4 through the processor bus 3 to the main memory 1 is provided. Thus, without limiting the type and quantity of the information necessary to analyze the program travelling route, and at the time of analyzing travelling route, the constitution to be able to refer freely with the trouble processing program, etc., executed in a data processor can be adopted and the program trouble can be efficiently analyzed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention 4 relates to a method for collecting program running routes.

[Conventional technology]

Conventionally, a well-known method for collecting this type of program running route is to connect a program running route tracing device such as a logic analyzer to the outside of the data processing device and save the program running route offline. It is being

[Problem that the invention seeks to solve]

The conventional method described above has a configuration in which the tracing device is connected to the outside of the data processing device, so there are physical limitations such as a limit on the number of lead wires for connection and a limit on the length of the lead wires. However, the drawback was that only the minimum amount of information needed to analyze the program travel route could be collected.

In addition, since the collected information itself is in a device completely separate from the data processing device, when analyzing the program running route, comparison with the program executed in the data processing device can only be performed offline. There were also drawbacks, such as the need for highly skilled engineers to perform the analysis.

[Means to solve the problem]

The system of the present invention is a multi-word processor that is connected to a processor bus that connects an arithmetic processing unit and a main memory, responds to access from the arithmetic processing unit to the main memory, and cyclically stores information related to the access. and a means for interrupting the storage of information in the trace memory by a signal sent from the arithmetic processing unit and transferring the information stored in the trace memory to the main storage device via the processor bus. are doing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a data processing device that is an embodiment of the present invention.

In this data processing device, an arithmetic processing unit 1 and a main storage device 2 are connected by a processor bus 3, and a trace memory 4 and a trace memory control circuit 5 are further connected to the processor bus 3.

The trace memory control circuit 5 includes a trace memory 4 and a memory address line 6 . It is connected by a memory write enable line 7 and a memory read enable line 8, and is further connected to the arithmetic processing unit 1 by a trace interruption instruction line 9.

FIG. 2 is a block diagram illustrating the trace memory control circuit 5 in more detail.

In FIG. 2, a trace memory control circuit 5 includes a trace condition determining circuit 51 connected to the processor bus 3 and instructing writing to the trace memory 4 via a memory write enable line 7; A trace memory address register 52 that supplies the memory address line 6 to the processor bus 3 is connected to the trace interrupt instruction line 9 from the arithmetic processing unit 1.
The processor bus control circuit 53 controls the transfer of trace information stored in the trace memory 4 to the main storage device 2 via the processor bus control circuit 53 . The processor bus control circuit 53 also supplies the trace memory read enable line 8 to the trace memory j, and also supplies the +1 increment amount 54b to the trace memory address register 52. Furthermore, the trace interruption instruction line 9 is also connected to the trace condition determination circuit 51, and instructs the writing of trace information to the trace memory 4 to be interrupted.

Next, the operation of the embodiment will be explained with reference to FIGS. 1 and 2.

In the data processing device, the arithmetic processing device 1 retrieves programs stored in the main storage device 2 one by one and executes them. memory address.

Read data or arithmetic processing unit 1 to main storage unit 2
Data to be written to the main memory 2 of the arithmetic processing unit 1 as well as an access type identification signal to the main memory 2 of the arithmetic processing unit 1 are transmitted and received.

This access type identification signal includes instructions such as
The operand store execution middle includes access identification such as when a jump destination instruction is being fetched, and the access type identification signal is subjected to a condition judgment in the trace condition judgment circuit 51, and if the data is necessary for analyzing the program running route. The data on the processor bus 3 is written into the trace memory 4 by turning on the memory write enable line 7 only.

When the write operation to the trace memory 4 is completed, the trace condition determination circuit 51 outputs a +1 increment signal 54a to the trace memory address register 52, and increments the memory address line 6 supplied to the trace memory 4 by +1. This prepares for writing the next trace information.

By repeatedly writing trace information to the trace memory 4 in this way, the trace memory consisting of multiple words becomes full, but unless the trace interrupt instruction line 9 is turned on, writing to the trace memory 4 will not be possible. will continue. That is, when the trace memory 4 becomes full, the trace memory address register 52 returns to its initial value, and trace information is written from address O of the trace memory 4.

With this configuration, the contents of the trace memory 4 consisting of a plurality of words are always updated to the latest program running route information. That is, the information corresponding to the storage capacity of the trace memory 4 from the memory address indicated by the trace memory address register 52 is the running route information of the latest program.

Program execution occurs when a program failure interrupt occurs during program execution in the arithmetic processing unit 1, or when the operation of the entire data processing unit is in an abnormal state and an emergency control operation such as system reconfiguration is activated. When an abnormality occurs, the arithmetic processing unit 1 turns on the trace interruption instruction line 9.

By turning on this trace interruption instruction line 9, the trace condition determination circuit 51 prohibits determination of trace conditions occurring after this point, and keeps the memory write enable line 7 to the trace memory 4 in the off state. do.

On the other hand, the processor bus control circuit 53 that has received the trace interruption instruction line 9 outputs the address information of the main storage device 2 for transferring trace information to the processor bus 3, and also outputs the memory read enable line 8 to the trace memory 4. By turning on the trace memory 4 and outputting read data from the trace memory 4 onto the processor bus 3, a write operation to the main memory device 2 is executed.

When the write operation for one word of the trace memory 4 to the main memory device 2 is completed, a +1 increment signal 54b is output, and the trace memory address register 52 is incremented by +1. By executing this operation for the number of words in the trace memory 4, it is possible to store in the main storage device 2 the running route of the program up to the point immediately before an abnormality occurred in program execution in the arithmetic processing unit 1.

That is, the running route of the program until an abnormality occurs in program execution in the arithmetic processing unit 1 is stored in the main memory 2.
The information is stored in the computer and can be freely referenced in the troubleshooting program of the arithmetic processing unit 1.

〔Effect of the invention〕

As explained above, the present invention consists of a plurality of words that respond to an access from the arithmetic processing unit to the main memory and store information related to this access on the processor bus that connects the arithmetic processing unit and the main memory. Providing means for connecting the trace memory, interrupting the storage of information in the trace memory by a signal sent from the arithmetic processing unit, and transferring the information stored in the trace memory to the main memory via the processor bus. This allows you to analyze program travel routes without limiting the type or amount of information required.
In addition, when analyzing a program running route, a configuration can be adopted that can be freely referenced by a fault processing program executed within a data processing device, and an efficient means for analyzing program faults can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram illustrating details of the trace memory control circuit of FIG. 1. 1... Arithmetic processing unit, 2... Main storage device, 3...
Processor memory, 4...Trace memory, 5...
Trace memory control circuit, 6... memory address line,
7...Memory write enable line, 8...Memory read enable line, 9...Trace interruption instruction line, 51
. . . Trace condition determination circuit, 52 . . . Trace memory address register, 53 . . . Processor bus control circuit, 54a, 5i4b-+1 increment signal.

Claims (1)

[Scope of Claims] A data processing device comprising an arithmetic processing unit and a main storage device connected by a processor bus, the data processing device being connected to the processor bus and responding to accesses from the arithmetic processing device to the main storage device. a trace memory consisting of a plurality of words that cyclically stores information related to the access; and a signal sent from the arithmetic processing unit to interrupt the storage of the information in the trace memory, and means for transferring information to the main storage device via the processor bus, the data characterized in that a running route of a program executed in the arithmetic processing unit is stored in the main storage device. A method for collecting program running routes in a processing device.