JPH11142478A - Semiconductor integrated circuit and its usage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test a semiconductor integrated circuit at the actual operating clock cycle without using an LSI tester by controlling the slow data signal inputted from the outside and the clock signal with the clock setting signal, multiplying the speed of the inside of the semiconductor integrated circuit N times, and outputting the result. SOLUTION: The clock signal (a) inputted from a clock signal input terminal 105 is multiplied N times in a clock N-multiplying circuit 111 by the clock setting signal f) inputted from a clock setting signal input terminal 1 04 and is outputted as the clock signal (c). The data signal (b) from a data input terminal 103 is multiplied N times in a data N-multiplying circuit 110 by the setting signal (f) and is outputted as the data signal (d). A logical operation is made with the signals (c), (d) in flip-flops 112, 115 and a combinational circuit 113, and the output signal (e) is outputted to an output terminal 106. The signal (e) is inputted to the data buffer 114 of an LSI tester 102 through a data input terminal 108. The signal (c) is inputted to a data buffer 114 through the clock input terminal 109 of a tester 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit and a method of using the same, and more particularly, to a semiconductor integrated circuit capable of operating by multiplying an external clock cycle by N.

[0002]

2. Description of the Related Art In recent years, large-scale integration of semiconductor integrated circuits,
The increased number of terminals has made it more prominent, and complex logic functions can be integrated at higher densities.However, due to the complexity of circuits and the speed of semiconductor integrated circuits, large-scale logic function tests can be performed at high speed. Is becoming more difficult.

On the other hand, while the clock cycle of a device equipped with this semiconductor integrated circuit is accelerated, the clock cycle of an LSI tester for testing the logic function of this semiconductor integrated circuit is stable with respect to a multi-terminal semiconductor integrated circuit. It is difficult to supply high-speed signals.

Conventional methods for testing the logic function of a semiconductor integrated circuit are disclosed in Japanese Patent Application Laid-Open Nos.
No. 51104, for example.

FIG. 5 is a block diagram showing a conventional semiconductor integrated circuit. 5, 117 denotes a semiconductor integrated circuit, 103 denotes a data input terminal, 105 denotes a clock signal input terminal, 106 denotes a data output terminal, 112 and 115 denote flip-flops, and 113 denotes a combinational circuit.

FIG. 6 is a timing chart showing the operation of the conventional semiconductor integrated circuit of FIG. The operation of the conventional example will be described with reference to FIGS. Data input terminal 103
And the data signal b is input to the flip-flop 112 on the input side. The clock signal a input from the clock signal input terminal 105 is supplied to all flip-flops 112 and 115 in the semiconductor integrated circuit 117. The data signal b is taken in by the clock signal a from the clock signal input terminal 105, and the logical operation is performed through the combinational circuit 113. As a result, the output signal e is output from the data output terminal 106 via the flip-flop 11 on the output side. Is output.

In order to test all signal terminals of such a conventional semiconductor integrated circuit at the same high-speed clock cycle as in an actual device, a high-performance and expensive LSI tester is required.

[0008]

A first problem is that a conventional semiconductor integrated circuit cannot sufficiently perform a logic function test of the semiconductor integrated circuit in consideration of actual operation.
As a result, a problem arises in that a problem cannot be found in the semiconductor integrated circuit unit test process, and the semiconductor integrated circuit having a problem in characteristics proceeds to the device test process.

The reason is that, in a semiconductor integrated circuit unit test process, the capability of the tester cannot sufficiently cope with the actual operation speed, and the test cannot be performed in the same high-speed clock cycle as in the actual device.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problem that a conventional logic function test of a semiconductor integrated circuit in consideration of actual operation cannot be sufficiently performed, to find a problem at an early stage in a semiconductor integrated circuit unit test process, and to improve characteristics. An object of the present invention is to provide a semiconductor integrated circuit with improved reliability so that a problematic semiconductor integrated circuit does not proceed to a device test process.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
A clock N multiplying circuit (111 in FIG. 1) for multiplying a clock signal (a in FIG. 1) input from the outside by N in response to a clock setting signal (f in FIG. 1) input from the outside is provided.

A semiconductor integrated circuit according to the present invention is a clock N multiplying circuit (FIG. 1) for multiplying an externally input clock signal (FIG. 1a) by N in response to an externally input clock setting signal (FIG. 1f). 1, 111) and a data signal input from the outside corresponding to the clock setting signal (b in FIG. 1).
And a data N multiplying circuit (110 in FIG. 1) for multiplying N by N.

The semiconductor integrated circuit according to the present invention has an N-multiplied clock signal (FIG. 2A) obtained by multiplying an externally input clock signal (FIG. 2A) by N in response to an externally input clock setting signal (FIG. 2F). 2) c) a clock N-multiplier circuit (111 in FIG. 2) and an internal circuit operated by the N-multiplied clock signal (112, 113, 115 in FIG. 2)
And a buffer (118 in FIG. 2) that takes in the signal output from the internal circuit with the N-multiplied clock signal and outputs the signal with the clock signal.

The semiconductor integrated circuit according to the present invention is an N-multiplied clock signal (FIG. 2A) obtained by multiplying an externally input clock signal (FIG. 2A) by N in response to an externally input clock setting signal (FIG. 2F). 2c) that outputs the clock signal (111 in FIG. 2), and an N-multiplied clock signal (FIG. 2) obtained by multiplying an externally input data signal (b in FIG. 2) by N in response to the clock setting signal. D) to output d)
A multiplying circuit (110 in FIG. 2), an internal circuit (112, 113, 115 in FIG. 2) that receives the N-multiplied data signal and operates by the N-multiplied clock signal, and outputs a signal output from the internal circuit to the N A buffer (118 in FIG. 2) which takes in with the multiplied clock signal and outputs with the clock signal.

In the above-described semiconductor integrated circuit, the clock setting signal is a signal obtained by shifting the clock signal by a quarter period, and the clock N multiplying circuit outputs a clock that outputs an inverted clock signal obtained by inverting the clock signal. A signal-side inverter circuit, and a clock signal-side selector for selecting and outputting the clock signal when the clock setting signal is in a first state and selecting and outputting the inverted clock signal when the clock setting signal is in a second state. And a circuit for outputting a doubled clock signal obtained by doubling the clock signal, and the data N multiplying circuit outputs a data signal-side inverter circuit that outputs an inverted data signal obtained by inverting the data signal (FIG. 4).
604), when the clock setting signal is in the first state, the data signal is selected and the clock setting signal is set to the second state.
In the state (1), a data signal side selector circuit (605 in FIG. 4) for selecting and outputting the inverted data signal may be provided to output a doubled data signal obtained by doubling the data signal. it can.

According to the method of using the semiconductor integrated circuit of the present invention, when the above-described semiconductor integrated circuit is connected to a tester for testing, the clock N-multiplier circuit outputs the N-multiplied clock signal or the double-multiplied clock signal. The clock setting signal for causing the data N multiplying circuit to output the N multiplied data signal or the 2 multiplied data signal is input to the semiconductor integrated circuit.

The semiconductor integrated circuit of the present invention controls a slow data signal and a clock signal input from the outside by a clock setting signal, causes the inside of the semiconductor integrated circuit to operate at N times high speed, and outputs the result. For this reason, a unit test can be performed in an actual operation clock cycle of a semiconductor integrated circuit without using a high-speed and expensive LSI tester.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, a semiconductor integrated circuit 101 includes a data input terminal 103, a clock setting signal input terminal 104, a clock signal input terminal 105,
Data output terminal 106 and clock signal output terminal 107
, Data N communication circuit 110, and clock N communication circuit 1
11, flip-flops 112 and 115, and a combinational circuit 113.

The data signal b input from the data input terminal 103 is connected to the first terminal of the data N multiplying circuit 110, and the clock setting signal f input from the clock setting signal input terminal 104 is connected to the data N multiplying circuit 110. The clock signal a connected to the second terminal and input from the clock signal input terminal 105 is input to the first terminal of the clock N multiplication circuit 111,
The clock setting signal f is input to the terminal of
From the third terminal of the multiplication circuit 111, the data N multiplication circuit 1
10 third terminals and each flip-flop 112,1
The clock signal c is input to the 15 second terminals.

From the fourth terminal of the data N multiplying circuit 110, the data signal d is supplied to the first terminal of the flip-flop 112.
And the third terminal of the flip-flop 112 is connected to the combinational circuit 113. The output from the combinational circuit 113 is connected to the first terminal of the flip-flop 115, and the third terminal of the flip-flop 115 outputs the data signal e to the data output terminal 106. Clock N
The third terminal of the multiplication circuit 111 is a clock signal output terminal 1
07 is also connected. The data output terminal 106 is connected to the LSI tester-side data input terminal 108 of the LSI tester 102. The clock signal output terminal 107 is connected to the LS of the LSI tester 102.
It is connected to the I tester side clock input terminal 109. LS
I tester side data input terminal 108 is LSI tester 102
Is connected to the first terminal of the data buffer 114 within
The SI tester side clock input terminal 109 is connected to the second terminal of the data buffer 114 in the LSI tester.

FIG. 3 is a timing chart showing the operation of the semiconductor integrated circuit 101 of FIG. The operation of the present embodiment will be described with reference to FIGS.

The timing chart of FIG. 3 shows an example in which N = 2 in the N multiplication circuits 110 and 111, that is, the external clock of the semiconductor integrated circuit is multiplied by 2 to operate internally at high speed. The clock signal a input from the clock signal input terminal 105 is doubled in the clock N-multiplier circuit 111 by the clock setting signal f input from the clock setting signal input terminal 104, and the clock signal c is doubled.
Is output as On the other hand, in the data N multiplying circuit 110, the data signal b input from the data input terminal 103
Is similarly doubled by the clock setting signal f and output as the doubled data signal d.

In the flip-flops 112 and 115 and the combination circuit 113, a logical operation is performed by the clock signal c and the data signal d multiplied by 2, and as a result, the output signal e
Is output to the data output terminal 106. The output signal e output from the data output terminal 106 is output to the LSI tester 10
2 to the LSI tester side data input terminal 108,
The data is input to the data buffer 114 in the LSI tester.
The clock signal c doubled in the semiconductor integrated circuit 101
Is input to the LSI tester-side clock input terminal 109 of the LSI tester 102 through the clock signal output terminal 107, is input to the data buffer 114 in the LSI tester, and outputs the output signal e from the semiconductor integrated circuit by the clock signal pulse. Take it into the buffer 114.

FIG. 2 is a block diagram showing another embodiment of the present invention. The difference from the embodiment shown in FIG. 1 is that in the embodiment shown in FIG.
While the data is taken into the data buffer 114 in the tester 102, in the embodiment of FIG.
6, a data buffer 118 is prepared, an output signal e is taken in, and a data output terminal 106 of the semiconductor integrated circuit 116 is provided.
The output signal e output from is a slow clock cycle before being multiplied by N in the semiconductor integrated circuit 116.

FIG. 4 is a block diagram showing details of the data N multiplying circuit 110 in FIGS. 1 and 2.

The data signal b input from the data input terminal 103 is inverted by the inverter circuit 604 to obtain an inverted data signal g, and the selector circuit 605 controls the clock signal f input from the terminal 104 to control the data signal b and the inverted signal. One of the signals g is selected and output as a data signal d. The selector circuit 605 selects the data signal b when the clock setting signal f has a value of “1”, and selects the inverted data signal g when the clock setting signal f has a value of “0” to output the data signal d. In the integrated circuits shown in FIGS. 1 and 2, a clock setting signal f delayed by a quarter period from the clock signal a and the data signal b is input from the terminal 104, so that the data N multiplying circuit 110 converts the data signal b into two. A multiplied data signal d is obtained.

Since the clock setting signal f is always a steady signal consisting of "1", the data N multiplying circuit 11
It can be set so that 0 outputs the same data signal d as the data signal b.

As the clock N multiplying circuit 111, a circuit similar to the circuit shown in FIG. 4 can be used, and the clock signal a can be multiplied by 2 or 1 by the clock setting signal f and output as the clock signal c. .

In the semiconductor integrated circuit shown in FIGS. 1 and 2, when testing with an LSI tester, relatively low frequency data signal b and clock signal a are input from data input terminal 103 and clock signal input terminal 105. These signals a and b are doubled by a data N multiplication circuit 110 and a clock N multiplication circuit 111 to obtain a high-frequency data signal d and a clock signal c. 112 and 115 and the combinational circuit 113 are operated, and a relatively low-speed signal is received from the LSI tester, so that the internal flip-flop circuits 112 and 115 and the combinational circuit 113 operate at the same speed as when they are actually operated at high speed. Operation can be tested.

At the time of actual operation on the actual device, the data N
A data signal d having the same speed as the external signal speed, where the multiplication number of the multiplication circuit 110 and the clock N multiplication circuit 111 is 1
And the flip-flop circuit 112 with the clock signal c,
115 and the combinational circuit 113 can be operated.

According to the present invention, the data N multiplying circuit 110 and the clock N multiplying circuit 111 are not limited to those which multiply the frequency of a signal by 2 or 1 as shown in FIG. Needless to say.

[0033]

According to the present invention, as described above,
Performs a logic function test of a semiconductor integrated circuit in consideration of actual operation without using a high-performance and expensive LSI tester, and reliably finds a problem early in the semiconductor integrated circuit unit test process, and has a problem in characteristics. Can improve the reliability of the semiconductor integrated circuit so that the process does not proceed to the device test process.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 3 is a timing chart illustrating an operation of the semiconductor integrated circuit illustrated in FIG. 1;

FIG. 4 is a block diagram showing details of a data N multiplying circuit 110 in FIGS. 1 and 2;

FIG. 5 is a block diagram showing an example of a conventional semiconductor integrated circuit.

6 is a timing chart illustrating an operation of the semiconductor integrated circuit illustrated in FIG.

[Explanation of symbols]

 Reference Signs List 101 semiconductor integrated circuit 102 LSI tester 103 data input terminal 104 clock setting signal input terminal 105 clock signal input terminal 106 data output terminal 107 clock signal output terminal 108 LSI tester side data input terminal 109 LSI tester side clock input terminal 110 data N multiplication circuit 111 Clock N Multiplying Circuit 112 Flip-Flop 113 Combination Circuit 114 Data Buffer 115 Flip-Flop 116 Semiconductor Integrated Circuit 117 Semiconductor Integrated Circuit 118 Data Buffer 605 Selector Circuit

Claims (8)

[Claims] 1. A semiconductor integrated circuit comprising a clock N multiplying circuit for multiplying a clock signal input from the outside by N in response to a clock setting signal input from the outside. 2. A clock N multiplying circuit for multiplying a clock signal input from the outside by N in response to a clock setting signal input from the outside, and multiplying a data signal input from the outside by N corresponding to the clock setting signal. A semiconductor integrated circuit comprising: a data N multiplying circuit. 3. A clock N-multiplier circuit for outputting an N-multiplied clock signal obtained by multiplying a clock signal input from the outside by N in response to a clock setting signal input from the outside, and an internal circuit operated by the N-multiplied clock signal. A buffer which takes in a signal output from the internal circuit with the N-multiplied clock signal and outputs the signal with the clock signal. 4. A clock N multiplying circuit for outputting an N-multiplied clock signal obtained by multiplying a clock signal input from the outside by N in response to a clock setting signal input from the outside, and an input from the outside corresponding to the clock setting signal N to output an N-multiplied clock signal obtained by multiplying the data signal to be N by N
A multiplying circuit, an internal circuit that receives the N-multiplied data signal and operates by the N-multiplied clock signal, and a buffer that takes in the signal output by the internal circuit with the N-multiplied clock signal and outputs the clock signal. A semiconductor integrated circuit characterized by the above. 5. The clock setting signal is a signal obtained by shifting the clock signal by a quarter period. The clock N multiplying circuit outputs an inverted clock signal obtained by inverting the clock signal; And a selector circuit for selecting and outputting the clock signal when the setting signal is in the first state and selecting and outputting the inverted clock signal when the clock setting signal is in the second state. 4. The semiconductor integrated circuit according to claim 1, wherein the multiplied double clock signal is output. 6. The clock setting signal is a signal obtained by shifting the clock signal by a quarter period. The clock N multiplying circuit includes a clock signal side inverter circuit that outputs an inverted clock signal obtained by inverting the clock signal. A clock signal-side selector circuit that selects the clock signal when the clock setting signal is in the first state and selects and outputs the inverted clock signal when the clock setting signal is in the second state. The data N multiplying circuit outputs a data signal-side inverter circuit that outputs an inverted data signal obtained by inverting the data signal, and the clock setting signal is a first clock setting signal.
And a data signal-side selector circuit for selecting and outputting the inverted data signal when the clock setting signal is in the second state when the data signal is in the second state. 5. The semiconductor integrated circuit according to claim 2, wherein a doubled data signal is output. 7. When the semiconductor integrated circuit according to claim 1, 3 or 5 is connected to a tester for testing, the clock N multiplying circuit outputs the N multiplied clock signal or the 2 multiplied clock signal. A method of using a semiconductor integrated circuit, comprising: inputting a clock setting signal to the semiconductor integrated circuit. 8. When the semiconductor integrated circuit according to claim 2, 4 or 6 is connected to a tester for testing, the clock N-multiplier circuit outputs the N-multiplied clock signal or the 2-multiplied clock signal. The method of using a semiconductor integrated circuit, wherein the clock setting signal for causing the data N-multiplier circuit to output the N-multiplied data signal or the doubled data signal is input to the semiconductor integrated circuit.