JPH1117059A - Ball grid array substrate and its continuum - Google Patents
Ball grid array substrate and its continuumInfo
- Publication number
- JPH1117059A JPH1117059A JP17041597A JP17041597A JPH1117059A JP H1117059 A JPH1117059 A JP H1117059A JP 17041597 A JP17041597 A JP 17041597A JP 17041597 A JP17041597 A JP 17041597A JP H1117059 A JPH1117059 A JP H1117059A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- external connection
- film
- film carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】
【課題】 パッケージの多端子化、高集積化及び小型化
を実現し、さらに、半導体素子搭載から樹脂封止、外部
接続用バンプ形成及び検査までの連続処理を実現するB
GA基板を提供することである。
【解決手段】 金属基板11上に絶縁層と導体配線層を
順次積層して、最上層に接続電極18を形成したビルド
アップ型の多層配線回路基板100と長尺のポリイミド
フィルムからなるベースフィルムのロの字型ベースフィ
ルム22上に形成された配線層24、外部接続端子25
及びリード23からなるフィルムキャリアはロの字型絶
縁基板31を介して接着層32、33にて固定し、一体
化される。さらに、フィルムキャリアの外部接続端子2
5はリード23にて多層配線回路の接続電極18と電気
的に接続されてBGA基板及びその連続体が得られる。
(57) [Problem] To realize a multi-terminal package, high integration and miniaturization of a package, and to realize continuous processing from mounting of a semiconductor element to resin sealing, formation of external connection bumps and inspection.
It is to provide a GA substrate. SOLUTION: A build-up type multilayer wiring circuit board 100 in which an insulating layer and a conductor wiring layer are sequentially laminated on a metal substrate 11 and a connection electrode 18 is formed on an uppermost layer, and a base film made of a long polyimide film. Wiring layer 24 formed on square base film 22, external connection terminal 25
The film carrier including the leads 23 is fixed by bonding layers 32 and 33 via a square-shaped insulating substrate 31 and integrated. Furthermore, the external connection terminal 2 of the film carrier
The lead 5 is electrically connected to the connection electrode 18 of the multilayer wiring circuit by the lead 23 to obtain a BGA substrate and its continuum.
Description
【0001】[0001]
【発明の属する技術分野】本発明はLSI、VLSI等
に代表される半導体集積回路の実装に用いられる、いわ
ゆるボールグリッドアレイ基板に係わり、さらに詳しく
はパッケージの多端子化、高集積化、小型化を実現させ
るボールグリッドアレイ基板(以下、BGA基板と称
す)に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called ball grid array substrate used for mounting a semiconductor integrated circuit typified by an LSI, a VLSI, etc., and more specifically to a multi-terminal package, high integration, and miniaturization of a package. (Hereinafter, referred to as a BGA substrate).
【0002】[0002]
【従来の技術】従来のマルチチップモジュール基板は、
図3に示すような、エポキシ、BTレジン等の銅貼り絶
縁基板41の片面に絶縁層と導体配線層を交互に積層し
て形成された多層配線回路の最下層の第1配線層44
と、もう一方の面に形成された外部接続端子43とがス
ルーホール42で電気的に接続されているBGA基板
と、さらに、図4に示すような、特に放熱性向上の目的
で金属基板51上の片面に絶縁層と導体配線層を順次積
層して形成された多層配線回路と、予めエポキシ、BT
レジン等のロの字型絶縁基板61に外部接続端子64と
接続電極63がスルーホール62で電気的に接続された
ロの字型配線回路基板とが接着層71で貼り合わされ、
多層配線回路基板の最上層の配線層57の接続電極58
とロの字型配線回路基板の接続電極63とは溶融接合に
て電気的に接続されているBGA基板とがある。2. Description of the Related Art Conventional multi-chip module substrates are:
As shown in FIG. 3, a lowermost first wiring layer 44 of a multilayer wiring circuit formed by alternately laminating insulating layers and conductor wiring layers on one surface of a copper-bonded insulating substrate 41 made of epoxy, BT resin, or the like.
And an external connection terminal 43 formed on the other surface, and a BGA substrate electrically connected to the external connection terminal 43 through a through hole 42. Further, as shown in FIG. A multilayer wiring circuit formed by sequentially laminating an insulating layer and a conductor wiring layer on one side of the upper surface;
An external connection terminal 64 and a square-shaped wiring circuit board in which the connection electrodes 63 are electrically connected through through holes 62 are bonded to a square-shaped insulating substrate 61 such as a resin with an adhesive layer 71,
Connection electrode 58 of uppermost wiring layer 57 of multilayer wiring circuit board
There is a BGA substrate electrically connected to the connection electrode 63 of the square-shaped wiring circuit board by fusion bonding.
【0003】上記のようなBGA基板では、ドリルで機
械的にスルーホールが開けられるため穴径が最小200
μm程度と大きく、BGA基板の多端子化、高集積化、
小型化が不可能といった問題があった。また、金属板上
に絶縁層と導体層とを積層した形態の場合は、多層配線
回路基板とロの字型配線回路基板とを貼り合わせる際、
接続電極部が目視不可能なために、外部接続端子の大き
さをさらに大きくする必要があった。また、半導体素子
搭載、樹脂封止及び外部接続用バンプ形成は、一つ一つ
の基板が1つのケースから各工程ごとに別々に取り出し
収納されるので、工程及び検査間の連続処理が不可能で
あった。[0003] In the above-mentioned BGA substrate, a through hole is mechanically opened by a drill, so that the hole diameter is at least 200 mm.
μm large, multi-terminal BGA board, high integration,
There was a problem that miniaturization was impossible. Also, in the case of a form in which an insulating layer and a conductor layer are laminated on a metal plate, when bonding a multilayer wiring circuit board and a square-shaped wiring circuit board,
Since the connection electrode portion is not visible, it is necessary to further increase the size of the external connection terminal. In addition, since the mounting of the semiconductor element, the resin sealing, and the formation of the bumps for external connection are performed, each substrate is separately taken out from one case and stored in each step, so that continuous processing between the steps and the inspection is impossible. there were.
【0004】[0004]
【発明が解決しようとする課題】本発明は、前記問題点
を鑑みなされたものであり、その目的とするところは、
パッケージの多端子化、高集積化及び小型化を実現し、
さらに、半導体素子搭載から樹脂封止、外部接続用バン
プ形成及び検査までの連続処理を実現するBGA基板を
提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object the following:
Realization of multi-terminal package, high integration and miniaturization of package,
It is still another object of the present invention to provide a BGA substrate that realizes continuous processing from mounting of a semiconductor element to resin sealing, formation of external connection bumps, and inspection.
【0005】[0005]
【課題を解決するための手段】本発明に於いて上記課題
を解決するために、まず請求項1においては、金属基板
あるいは絶縁基板上に絶縁層と導体配線層とを順次積層
して形成した多層配線回路と外部接続端子からなるボー
ルグリッドアレイ基板において、前記外部接続端子がフ
ィルムキャリアで構成されており、前記多層配線回路の
最上層の接続電極とリードで接続されていることを特徴
とするボールグリッドアレイ基板としたものである。Means for Solving the Problems In order to solve the above-mentioned problems in the present invention, first, in claim 1, an insulating layer and a conductor wiring layer are sequentially laminated on a metal substrate or an insulating substrate. In a ball grid array substrate composed of a multilayer wiring circuit and external connection terminals, the external connection terminals are formed of a film carrier, and are connected to the uppermost connection electrodes of the multilayer wiring circuit by leads. This is a ball grid array substrate.
【0006】また、請求項2においては、前記フィルム
キャリアは半導体素子搭載から、樹脂封止、又は外部接
続用バンプ形成まで連続に処理可能なフィルムキャリア
連続体で構成されていることを特徴とする請求項1記載
のボールグリッドアレイ基板の連続体としたものであ
る。According to a second aspect of the present invention, the film carrier is formed of a film carrier continuum that can be continuously processed from mounting of a semiconductor element to resin sealing or formation of external connection bumps. A continuous body of the ball grid array substrate according to claim 1.
【0007】[0007]
【発明の実施の形態】以下、本発明の実施の形態につき
説明する。図1(a)に本発明のBGA基板の断面図
を、図1(b)に本発明のBGA基板の部分拡大断面図
を、さらに図2(a)にはフィルムキャリアの平面図
を、図2(b)にはフィルムキャリアの断面図をそれぞ
れ示す。Embodiments of the present invention will be described below. 1A is a sectional view of the BGA substrate of the present invention, FIG. 1B is a partially enlarged sectional view of the BGA substrate of the present invention, and FIG. 2A is a plan view of a film carrier. FIG. 2B shows a cross-sectional view of the film carrier.
【0008】本発明のBGA基板は、パッケージの多端
子化、高集積化及び小型化を実現し、さらに、半導体素
子搭載から、樹脂封止、外部接続用バンプ形成及び検査
までの連続処理を実現するBGA基板を提供するために
考案されたもので、金属基板又は絶縁基板上に絶縁層と
導体配線層を順次積層して形成したビルドアップ型の多
層配線回路基板100はロの字型絶縁基板31を介して
接着層32、33にてフィルムキャリア200と固定さ
れ、一体化される。さらに、フィルムキャリア200の
外部接続端子25はリード23にて多層配線回路の接続
電極18と電気的に接続されてBGA基板が作製され
る。さらに、フィルムキャリア200は連続したフィル
ムで形成されている。以下BGA基板の各構成について
説明する。The BGA substrate of the present invention realizes multi-terminal package, high integration and miniaturization of the package, and further realizes continuous processing from mounting of semiconductor elements, resin sealing, formation of bumps for external connection and inspection. A build-up type multilayer wiring circuit board 100 formed by sequentially laminating an insulating layer and a conductor wiring layer on a metal substrate or an insulating substrate is a square-shaped insulating substrate. It is fixed to the film carrier 200 by the adhesive layers 32 and 33 via 31 and is integrated. Further, the external connection terminals 25 of the film carrier 200 are electrically connected to the connection electrodes 18 of the multilayer wiring circuit by the leads 23, and a BGA substrate is manufactured. Further, the film carrier 200 is formed of a continuous film. Hereinafter, each configuration of the BGA substrate will be described.
【0009】まず、金属基板11上に樹脂(例えば、フ
ィラ入りBCB(ベンゾシクロブテン;ダウケミカル社
製))溶液を塗布し、熱乾燥して第1絶縁層12を形成
する。First, a resin (for example, a filler-containing BCB (benzocyclobutene; manufactured by Dow Chemical Co., Ltd.)) solution is applied on a metal substrate 11 and dried by heat to form a first insulating layer 12.
【0010】次に、エキシマレーザにより第1絶縁層1
2の所定位置にビアホール形成孔を形成し、第1絶縁層
12上に銅をスパッタして薄膜導体層を形成する。Next, the first insulating layer 1 is formed by an excimer laser.
Then, via-holes are formed at predetermined positions 2 and copper is sputtered on the first insulating layer 12 to form a thin-film conductor layer.
【0011】次に、基板両面に感光性樹脂を塗布、乾燥
して、膜厚15μmの感光層を形成し、薄膜導体層上の
感光層に所定のパターンを露光、現像、硬化処理してレ
ジストパターンを形成し、他方の面の感光層は全面露
光、硬化処理してめっきレジスト層とする。Next, a photosensitive resin is coated on both sides of the substrate and dried to form a photosensitive layer having a thickness of 15 μm. The photosensitive layer on the thin-film conductor layer is exposed, developed and cured by a predetermined pattern. A pattern is formed, and the photosensitive layer on the other surface is exposed and cured to form a plating resist layer.
【0012】次に、硫酸銅めっき液を使った電解めっき
にて、レジストパターンをマスクにして電流密度5A/
dm2 で10μm厚の銅の導体パターン層及びビアホー
ルを形成し、専用の剥離液によりレジストパターンを剥
離し、導体パターン層をマスクにして薄膜導体層をエッ
チングして第1配線層13を形成する。Next, the current density is 5 A / electrode by electrolytic plating using a copper sulfate plating solution, using the resist pattern as a mask.
A 10 μm-thick copper conductor pattern layer and a via hole are formed at dm 2 , the resist pattern is peeled off using a dedicated stripper, and the thin film conductor layer is etched using the conductor pattern layer as a mask to form the first wiring layer 13. .
【0013】さらに、上記工程を必要回数繰り返すこと
により、絶縁層と導体配線層を順次積層したビルドアッ
プ型の多層配線回路基板100を作成する。Further, the above steps are repeated as many times as necessary to produce a build-up type multilayer wiring circuit board 100 in which insulating layers and conductor wiring layers are sequentially laminated.
【0014】一方、長尺のポリイミドフィルムからなる
ベースフィルム21の片面に接着フィルムを貼り合わせ
た後金型にて打ち抜き加工を施して、スプロケットホー
ル26、キャラクタホール27及びロの字型ベースフィ
ルム22を形成した後銅箔を貼り合わせる。さらに、ロ
の字型ベースフィルム22上に外部接続端子25を作製
した後銅箔をパターニング処理してリード23及び配線
層24を形成してフィルムキャリア200を作製する。On the other hand, after bonding an adhesive film to one side of a base film 21 made of a long polyimide film, the base film 21 is punched with a die to form a sprocket hole 26, a character hole 27 and a square base film 22. After forming, a copper foil is attached. Further, after the external connection terminals 25 are formed on the square base film 22, the copper foil is patterned to form the leads 23 and the wiring layers 24, thereby manufacturing the film carrier 200.
【0015】次に、フィルムキャリア200はロの字型
絶縁基板31を介して接着層32、33にて多層配線回
路基板100の所定位置に貼り合わせ固定して一体化す
る。さらに、フィルムキャリア200の外部接続端子2
5をリード23にて多層配線回路基板100の接続電極
18と溶融接合等の方法で接合することにより本発明の
BGA基板を作製する。Next, the film carrier 200 is bonded and fixed to a predetermined position of the multilayer printed circuit board 100 with adhesive layers 32 and 33 via a square-shaped insulating substrate 31 to be integrated. Furthermore, the external connection terminal 2 of the film carrier 200
5 is joined to the connection electrode 18 of the multilayer wiring circuit board 100 by the lead 23 by a method such as fusion bonding, thereby producing the BGA substrate of the present invention.
【0016】[0016]
【実施例】以下実施例により本発明を詳細に説明する板
厚0. 20mmのCu合金からなる金属基板11の片面
に樹脂(BCB(商品名);ダウケミカル)溶液を塗布
し、100℃・15分、150℃・15分、210℃・
30分間加熱乾燥して12μm厚の第1絶縁層12を形
成した。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the following examples. A resin (BCB (trade name); Dow Chemical) solution is applied to one surface of a metal substrate 11 made of a 0.20 mm-thick Cu alloy at 100 ° C. 15 minutes, 150 ° C, 15 minutes, 210 ° C
The first insulating layer 12 having a thickness of 12 μm was formed by heating and drying for 30 minutes.
【0017】次に、エキシマレーザ(ビーム強度30m
j、周波数500Hz)にて、第1絶縁層12の所定位
置にビアホール形成孔を形成した。Next, an excimer laser (beam intensity 30 m
j, frequency of 500 Hz), a via hole forming hole was formed at a predetermined position of the first insulating layer 12.
【0018】次に、ビアホール形成孔を形成した絶縁層
上12に銅をスパッタして3000Å厚の薄膜導体層を
形成した。さらに、金属基板11の両面に感光性樹脂
(AZ(商品名);ヘキスト)を塗布し、90℃30分
乾燥して15μm厚の感光層を形成した。Next, copper was sputtered on the insulating layer 12 in which the via hole forming hole was formed to form a thin film conductor layer having a thickness of 3000 mm. Further, a photosensitive resin (AZ (trade name); Hoechst) was applied to both surfaces of the metal substrate 11, and dried at 90 ° C. for 30 minutes to form a photosensitive layer having a thickness of 15 μm.
【0019】次に、金属基板11の片面の感光層に所定
のパターンを露光・焼き付け、現像処理し、100℃、
30分加熱してレジストパターンを形成し、もう一方の
面の感光層は全面露光、硬化処理してめっきレジスト層
とした。Next, a predetermined pattern is exposed and baked on the photosensitive layer on one side of the metal substrate 11 and developed, and the pattern is formed at 100 ° C.
Heating was performed for 30 minutes to form a resist pattern, and the photosensitive layer on the other side was exposed and cured to form a plating resist layer.
【0020】次に、硫酸銅めっきを使った電解めっきに
て、上記レジストパターンをマスクにして電流密度5A
/ dm2 で10μm厚の銅の導体パターン層及びビアホ
ールを形成し、専用の剥離液によりレジストパターンを
剥離し、導体パターン層をマスクにして薄膜導体層をエ
ッチングして第1配線層13を形成した。Next, by electroplating using copper sulfate plating, using the resist pattern as a mask, a current density of 5 A
A 10 μm thick copper conductor pattern layer and a via hole are formed at / dm 2 , the resist pattern is stripped with a dedicated stripper, and the thin film conductor layer is etched using the conductor pattern layer as a mask to form a first wiring layer 13. did.
【0021】次に、上記工程を必要回数繰り返すことに
より、絶縁層と導体配線層を積層した多層配線回路が形
成され、最上層の配線層及び接続電極に無電解ニッケル
めっきにて5μm厚のニッケル層と無電解Auめっきに
て0. 5μmのAu膜を形成し、多層配線回路基板10
0を作製した。Next, the above process is repeated as many times as necessary to form a multilayer wiring circuit in which an insulating layer and a conductor wiring layer are laminated, and the uppermost wiring layer and the connection electrode are formed by electroless nickel plating to form a nickel wiring having a thickness of 5 μm. A layer and a 0.5 μm Au film are formed by electroless Au plating.
0 was produced.
【0022】一方、48mm幅、厚さ75μmの長尺ポ
リイミドフィルムからなるベースフィルム21の片面に
エポキシ系半硬化接着フィルムをラミネートし、金型に
て打ち抜き加工してスプロケットホール26、キャラク
タホール27及びロの字型ベースフィルム22を形成し
た。On the other hand, an epoxy-based semi-cured adhesive film is laminated on one surface of a base film 21 made of a long polyimide film having a width of 48 mm and a thickness of 75 μm, and is punched with a die to form sprocket holes 26, character holes 27 and A square base film 22 was formed.
【0023】次に、打ち抜き加工したベースフィルム2
1に厚さ18μmの銅箔を貼り合わせた。Next, the punched base film 2
1 was laminated with a copper foil having a thickness of 18 μm.
【0024】次に、銅箔を貼り合わせたベースフィルム
の両面に、感光性ドライフィルム(フォテック(商品
名);日立化成製)をラミネートし、40μm厚の感光
層を形成した。Next, a photosensitive dry film (Photec (trade name); manufactured by Hitachi Chemical Co., Ltd.) was laminated on both sides of the base film to which the copper foil was attached to form a photosensitive layer having a thickness of 40 μm.
【0025】次に、エキシマレーザ(ビーム強度30m
j、周波数500Hz)により、銅箔を貼り合わせたロ
の字型ベースフィルムと感光層面の所定位置にビアホー
ル形成孔を形成した。Next, an excimer laser (beam intensity 30 m
j, frequency 500 Hz), a via hole forming hole was formed at a predetermined position on the photosensitive layer surface with the square base film to which the copper foil was bonded.
【0026】次に、硫酸銅めっきを使った電解めっきに
て、電流密度5A/ dm2 で上記ビアホール形成孔に銅
めっきを行い、専用の剥離液により感光層を剥離し、ロ
の字型ベースフィルム22に外部接続用端子25を形成
した。Next, by electroplating using copper sulfate plating, copper plating was performed on the via hole forming hole at a current density of 5 A / dm 2 , and the photosensitive layer was peeled off with a dedicated peeling solution, and the square base was formed. External connection terminals 25 were formed on the film 22.
【0027】次に、銅箔が貼り合わされたベースフィル
ムの両面に感光性樹脂(AZ(商品名);ヘキスト)を
塗布し、90℃30分加熱して10μm厚の感光層を形
成した。Next, a photosensitive resin (AZ (trade name); Hoechst) was applied to both sides of the base film on which the copper foil was bonded, and heated at 90 ° C. for 30 minutes to form a 10 μm thick photosensitive layer.
【0028】次に、上記感光層に所定のパターンを露光
・焼き付けして、専用の現像液にて現像処理を行い、水
洗後100℃、30分加熱してレジストパターンを形成
し、塩化第2鉄溶液を用い銅箔のエッチングを行った後
専用の剥離液によりレジストパターンを剥離し、配線層
24及びリード23を形成した。Next, a predetermined pattern is exposed and baked on the photosensitive layer, developed with a dedicated developer, washed with water and heated at 100 ° C. for 30 minutes to form a resist pattern. After the copper foil was etched using an iron solution, the resist pattern was stripped off using a dedicated stripping solution to form a wiring layer 24 and leads 23.
【0029】次に、外部接続端子25の表面に無電解S
uメッキにより3μm厚のSu膜を形成しフィルムキャ
リア200を作製した。Next, the surface of the external connection terminal 25 is electroless S
A 3 μm thick Su film was formed by u-plating to produce a film carrier 200.
【0030】一方、両面にエポキシ系の接着層32、3
3が形成されたBT樹脂からなるロの字型絶縁基板31
を介して、フィルムキャリア200と多層配線回路基板
100とを接着させ、多層配線回路基板100の所定位
置にフィルムキャリア200を固定した。さらに、多層
配線回路基板100の接続電極18とフィルムキャリア
200のリード23の先端を熱圧着にて溶融接合するこ
とで、本発明のボールグリッドアレイ基板及びその連続
体を作製した。On the other hand, epoxy adhesive layers 32, 3
Square-shaped insulating substrate 31 made of BT resin with 3 formed thereon
The film carrier 200 and the multilayer printed circuit board 100 were adhered to each other via the substrate, and the film carrier 200 was fixed at a predetermined position of the multilayer printed circuit board 100. Furthermore, the connection electrodes 18 of the multilayer wiring circuit board 100 and the tips of the leads 23 of the film carrier 200 were melt-bonded by thermocompression bonding to produce the ball grid array substrate of the present invention and its continuous body.
【0031】[0031]
【発明の効果】上記したように、本発明に係わるボール
グリッドアレイ基板及びその連続体によると、外部接続
端子を有するフィルムキャリアと多層配線回路基板をそ
れぞれ別工程で作製し最後の工程で一体構造とするた
め、配線から外部接続端子まで微細加工プロセスが適用
でき、多端子化、高集積化、小型化が可能となる。さら
に、半導体素子搭載から、樹脂封止、外部接続用バンプ
形成及び検査までの連続処理が実現でき製造コスト及び
時間を削減できる。As described above, according to the ball grid array substrate and the continuum thereof according to the present invention, the film carrier having the external connection terminals and the multilayer wiring circuit board are manufactured in separate steps, and the integrated structure is formed in the last step. Therefore, a microfabrication process can be applied from wiring to external connection terminals, and multi-terminals, high integration, and miniaturization can be achieved. Furthermore, continuous processing from mounting of a semiconductor element to resin sealing, formation of bumps for external connection, and inspection can be realized, and manufacturing cost and time can be reduced.
【図1】(a)は、本発明に係わるボールグリッドアレ
イ基板の構成を示す断面図である。(b)は、本発明に
係わるボールグリッドアレイ基板の構成を示す部分拡大
断面図である。FIG. 1A is a cross-sectional view illustrating a configuration of a ball grid array substrate according to the present invention. (B) is a partial enlarged sectional view showing the configuration of the ball grid array substrate according to the present invention.
【図2】(a)は、本発明に係わるボールグリッドアレ
イ基板に用いるフィルムキャリア連続体の構成を示す平
面図である。(b)は、本発明に係わるボールグリッド
アレイ基板に用いるフィルムキャリア連続体のX−X'
線切断断面図であるFIG. 2A is a plan view showing a configuration of a continuous film carrier used for a ball grid array substrate according to the present invention. (B) is the XX ′ of the film carrier continuum used for the ball grid array substrate according to the present invention
It is a sectional view taken along a line
【図3】従来のボールグリッドアレイ基板の一構成を示
す断面図である。FIG. 3 is a cross-sectional view showing one configuration of a conventional ball grid array substrate.
【図4】従来のボールグリッドアレイ基板の他の構成を
示す断面図である。FIG. 4 is a cross-sectional view illustrating another configuration of a conventional ball grid array substrate.
11、51……金属基板 12、45、52……第1絶縁層 13、44、53……第1配線層 14、47、54……第2絶縁層 15、46、55……第2配線層 16、56……第3絶縁層 17、48、57……第3配線層 18、58、63……接続電極 21……ベースフィルム 22……ロの字型ベースフィルム 23……リード 24……配線層 25、43、64……外部接続端子 26……スプロケットホール 27……キャラクタホール 31、61……ロの字型絶縁基板 32、33、71……接着層 41……絶縁基板 42、62……スルーホール 100……多層配線回路基板 200……フィルムキャリア 11, 51 metal substrate 12, 45, 52 first insulating layer 13, 44, 53 first wiring layer 14, 47, 54 second insulating layer 15, 46, 55 second wiring Layers 16, 56 Third insulating layer 17, 48, 57 Third wiring layer 18, 58, 63 Connection electrode 21 Base film 22 Square-shaped base film 23 Lead 24 ... wiring layers 25, 43, 64 ... external connection terminals 26 ... sprocket holes 27 ... character holes 31, 61 ... square shaped insulating substrates 32, 33, 71 ... adhesive layers 41 ... insulating substrates 42 62 through-hole 100 multilayer wiring circuit board 200 film carrier
Claims (2)
体配線層とを順次積層して形成した多層配線回路と外部
接続端子からなるボールグリッドアレイ基板において、
前記外部接続端子はフィルムキャリアで構成されてお
り、前記多層配線回路の最上層の接続電極とリードで接
続されていることを特徴とするボールグリッドアレイ基
板。A ball grid array substrate comprising a multilayer wiring circuit formed by sequentially laminating an insulating layer and a conductor wiring layer on a metal substrate or an insulating substrate and external connection terminals,
The ball grid array substrate, wherein the external connection terminal is formed of a film carrier, and is connected to a connection electrode on an uppermost layer of the multilayer wiring circuit by a lead.
ら、樹脂封止又は外部接続用バンプ形成まで連続に処理
可能なフィルムキャリア連続体で構成されていることを
特徴とする請求項1記載のボールグリッドアレイ基板の
連続体。2. The ball grid according to claim 1, wherein the film carrier is formed of a film carrier continuum that can be continuously processed from mounting of a semiconductor element to resin sealing or formation of external connection bumps. Array substrate continuum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17041597A JPH1117059A (en) | 1997-06-26 | 1997-06-26 | Ball grid array substrate and its continuum |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17041597A JPH1117059A (en) | 1997-06-26 | 1997-06-26 | Ball grid array substrate and its continuum |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1117059A true JPH1117059A (en) | 1999-01-22 |
Family
ID=15904510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17041597A Pending JPH1117059A (en) | 1997-06-26 | 1997-06-26 | Ball grid array substrate and its continuum |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1117059A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538310B2 (en) | 2000-03-15 | 2003-03-25 | Nec Corporation | LSI package with internal wire patterns to connect and mount bare chip to substrate |
| US6623567B2 (en) | 2000-05-12 | 2003-09-23 | Nakamura Industrial Co., Ltd. | Method for high concentration carburizing and quenching of steel and high concentration carburized and quenched steel part |
| WO2022230910A1 (en) * | 2021-04-30 | 2022-11-03 | 日東電工株式会社 | Method for manufacturing wiring circuit board |
-
1997
- 1997-06-26 JP JP17041597A patent/JPH1117059A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538310B2 (en) | 2000-03-15 | 2003-03-25 | Nec Corporation | LSI package with internal wire patterns to connect and mount bare chip to substrate |
| US6653168B2 (en) | 2000-03-15 | 2003-11-25 | Nec Corporation | LSI package and internal connecting method used therefor |
| US6623567B2 (en) | 2000-05-12 | 2003-09-23 | Nakamura Industrial Co., Ltd. | Method for high concentration carburizing and quenching of steel and high concentration carburized and quenched steel part |
| WO2022230910A1 (en) * | 2021-04-30 | 2022-11-03 | 日東電工株式会社 | Method for manufacturing wiring circuit board |
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