JPH01128493A - Manufacture of multilayer interconnection substrate - Google Patents
Manufacture of multilayer interconnection substrateInfo
- Publication number
- JPH01128493A JPH01128493A JP62286205A JP28620587A JPH01128493A JP H01128493 A JPH01128493 A JP H01128493A JP 62286205 A JP62286205 A JP 62286205A JP 28620587 A JP28620587 A JP 28620587A JP H01128493 A JPH01128493 A JP H01128493A
- Authority
- JP
- Japan
- Prior art keywords
- conductive pattern
- resin
- film
- metal foil
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000011347 resin Substances 0.000 claims abstract description 33
- 229920005989 resin Polymers 0.000 claims abstract description 33
- 239000011888 foil Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 5
- 238000009713 electroplating Methods 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 17
- 239000011889 copper foil Substances 0.000 abstract description 12
- 238000004080 punching Methods 0.000 abstract description 2
- 238000002788 crimping Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は多層配線基板の製造方法に関し、特に第２層目
の導電パターンの形成を改良した多層配線基板の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a multilayer wiring board, and more particularly to a method for manufacturing a multilayer wiring board in which the formation of a second layer conductive pattern is improved.
（ロ）従来の技術
従来の多層配線基板の製造方法を第２図Ａ乃至第２図Ｃ
を参照して説明する。(b) Conventional technology The conventional method for manufacturing a multilayer wiring board is shown in Figures 2A to 2C.
Explain with reference to.
先ず第２図Ａに示す如く、絶縁基板（１１）上に第１の
導電パターン（１２）’を形成する。絶縁基板（１１）
としてはセラミックス等を用い、基板（１１〉全面に銅
箔を貼着した後所望のパターンにエツチングして形成さ
れる。First, as shown in FIG. 2A, a first conductive pattern (12)' is formed on an insulating substrate (11). Insulating substrate (11)
It is formed by using ceramics or the like as a material, and by adhering copper foil to the entire surface of the substrate (11) and then etching it into a desired pattern.
続いて第２図Ｂに示す如く、第１の導電パターン（１２
）を被覆する様に居間絶縁膜（１３〉を形成し、所望の
第１の導電パターン（１２）上にスルーホール（１４）
を形成している。層間絶縁膜（ｘ３＞とじてはポリイミ
ド層あるいは永久ホトレジスト后等を用いる。Next, as shown in FIG. 2B, a first conductive pattern (12
), and a through hole (14) is formed on the desired first conductive pattern (12).
is formed. A polyimide layer or a permanent photoresist layer is used as the interlayer insulating film (x3).
更に第２図Ｃに示す如く、層間絶縁膜（１３）上に無電
解銅又はニッケルメッキにより第２の導電パターン（１
５）を形成する。第２の導電パターン（１５）はスルー
ホール（１４）を介して第１の導電パターン（１２）と
接続され、多層構造を実現する。Furthermore, as shown in FIG. 2C, a second conductive pattern (1) is formed on the interlayer insulating film (13) by electroless copper or nickel plating.
5) Form. The second conductive pattern (15) is connected to the first conductive pattern (12) via a through hole (14) to realize a multilayer structure.
なお断る多層配線基板の製造方法は特開昭６０−１０６
９７号に開示されている。The manufacturing method of the multilayer wiring board that is refused is disclosed in Japanese Patent Application Laid-open No. 1986-106.
It is disclosed in No. 97.
（ハ）発明が解決しようとする問題点
斯上の従来の方法では第２の導電パターンを銅又はニッ
ケルの無電解メッキで形成するので導電路とするために
厚さを３０μ以上に形成するのに２４時間以上要する問
題点があった。(c) Problems to be solved by the invention In the above conventional method, the second conductive pattern is formed by electroless plating of copper or nickel, so it must be formed to have a thickness of 30 μm or more in order to form a conductive path. There was a problem that it took more than 24 hours to complete the process.
（ニ）問題点を解決するための手段
本発明は上述した問題点に鑑みて為されたものであり、
絶縁基板上に第１の導電パターンを形成する工程と、第
１の導電パターン上に導電パターンの一部分を囲む樹脂
コート膜を形成する工程と、樹脂コート膜に対応する開
口部及びバイアホール用の孔を金属箔付き樹脂層に設け
た後、金属箔付き樹脂層を第１の導電パターン上に貼着
する工程と、バイアホールに電気メッキを施し第１の導
電パターンと前記金属箔とを接続する工程と、金属箔を
エツチングして第２の導電パターンを形成する工程とを
具備して解決する。(d) Means for solving the problems The present invention has been made in view of the above-mentioned problems.
a step of forming a first conductive pattern on an insulating substrate; a step of forming a resin coat film surrounding a part of the conductive pattern on the first conductive pattern; and a step of forming an opening and a via hole corresponding to the resin coat film. After providing a hole in the resin layer with metal foil, a step of pasting the resin layer with metal foil on the first conductive pattern, and electroplating the via hole to connect the first conductive pattern and the metal foil. and a step of etching the metal foil to form a second conductive pattern.
（＊）作用
この様に本発明に依れば第１の導電パターン上にパター
ンの一部分を囲む樹脂コート膜を形成し、樹脂コート膜
に対応する開口部及びバイアホール用の孔を金属箔付き
樹脂に設けて第１の導電パターン上に貼着することによ
り、金属箔をエツチングして第２の導電パターンを形成
することができ短時間で第２の導電パターンを形成する
ことができる。(*) Function As described above, according to the present invention, a resin coat film surrounding a part of the pattern is formed on the first conductive pattern, and openings and via holes corresponding to the resin coat film are coated with metal foil. By providing the metal foil on resin and pasting it on the first conductive pattern, the second conductive pattern can be formed by etching the metal foil, and the second conductive pattern can be formed in a short time.
（へ）実施例
以下に第１図Ａ乃至第１図Ｈに示した実施例に基づいて
本発明の詳細な説明する。(F) Example The present invention will be described in detail below based on the example shown in FIGS. 1A to 1H.
先ず第１図Ａに示す如く、絶縁基板（１）Ｌに第１の導
電パターン（２）を形成する。絶縁基板（１）としては
セラミックスあるいは表面を酸化膜で被覆したアルミニ
ウム等を用い、第１の導電パターン（２）は基板（１）
全面に銅箔を貼着した後所望のパターンにエツチングし
て形成される。First, as shown in FIG. 1A, a first conductive pattern (2) is formed on an insulating substrate (1)L. The insulating substrate (1) is made of ceramic or aluminum whose surface is coated with an oxide film, and the first conductive pattern (2) is the substrate (1).
It is formed by pasting copper foil over the entire surface and then etching it into the desired pattern.
次に第１図Ｂに示す如く、第１の導電パターン（２）上
に第１の導電パターン（２）の一部分を囲む樹脂コート
膜（３）を形成する。樹脂コート膜（３）は、エポキシ
樹脂等の樹脂を第１の導電パターン（２）と重畳する様
に印刷形成する。即ち、第１の導電パターン（２）の半
導体素子が固着されるパッド（２′）の周囲の第１の導
電パターン（２）と重畳する様に且つ半導体素子が固着
されるバッド（２゛）の周囲を囲む様枠状に形成する。Next, as shown in FIG. 1B, a resin coat film (3) surrounding a portion of the first conductive pattern (2) is formed on the first conductive pattern (2). The resin coat film (3) is formed by printing a resin such as epoxy resin so as to overlap the first conductive pattern (2). That is, the pad (2') to which the semiconductor element of the first conductive pattern (2) is fixed is overlapped with the first conductive pattern (2) around the pad (2') to which the semiconductor element of the first conductive pattern (2) is fixed. It is formed into a frame shape surrounding the area.
樹脂コート膜（３）の厚み及び幅は任意に選択すること
ができ本実施例では厚みは１５μ、幅は約ｉ、ｓｍｎに
形成するものとする。The thickness and width of the resin coat film (3) can be arbitrarily selected, and in this example, the thickness is 15 μm and the width is approximately i, smn.
次に第１図Ｃに示す如く、樹脂フート膜（３）に対応す
る開口部（４）及びバイアホール用の孔（５）を金属箔
付き樹脂（６）に設けた後、金属箔付き樹脂Ｗ！Ｊ（６
）を絶縁基板（１）上に貼着する。金属箔付き樹Ｗｊ（
６）はポリイミド樹脂等の絶縁樹脂（８）とｆｉ４箔（
７）とが一体化された、いわゆるフレキシブルシートを
用いる。この金属箔付き樹脂（６）にはあらかじめパン
チング等により、枠状に形成された樹脂コート膜（３）
と対応する開口部（４）及び第１の導電パターン（２）
と多層配線するためのバイアホール用の孔（５）が形成
されており、基板（１）全面上に熱圧着する。このとき
金属箔付き樹脂（６）の開口部（４）内の終端辺は樹脂
コート（３）上の中央付近に位置する様に考慮する。Next, as shown in FIG. W! J(6
) on the insulating substrate (1). Tree Wj with metal foil (
6) is made of insulating resin (8) such as polyimide resin and fi4 foil (
7) A so-called flexible sheet is used which is integrated with the above. This resin coated film (3) with metal foil (6) has a frame-shaped resin coat film (3) formed in advance by punching, etc.
an opening (4) and a first conductive pattern (2) corresponding to
A hole (5) for a via hole for multilayer wiring is formed and bonded by thermocompression on the entire surface of the substrate (1). At this time, consideration is given so that the end edge of the resin with metal foil (6) inside the opening (4) is located near the center on the resin coat (3).
次に第１図りに示す如く、基板（１）上にドライフィル
ム（９）を約８０〜１００″Ｃで熱圧着して基板（１）
全面に付着する。Next, as shown in the first diagram, a dry film (9) is thermocompressed onto the substrate (1) at about 80 to 100"C, and the substrate (1) is
Adheres to the entire surface.
次に第１図Ｅに示す如く、多層配線用の孔（５）及び周
辺のドライフィルム（９）を写真蝕刻法により除去しバ
イアホールを形成する。Next, as shown in FIG. 1E, the multilayer wiring hole (5) and the surrounding dry film (9) are removed by photolithography to form a via hole.
次に第１図Ｆに示す如く、バイアホールに電気メッキを
施し、第１の導電パターン（２）と銅箔（７）とを接続
する。Next, as shown in FIG. 1F, the via hole is electroplated to connect the first conductive pattern (2) and the copper foil (7).
第１図Ｅの如く、バイアホール及びバイアホールの周辺
の銅箔（７）は露出され、銅の無電解メッキを行い、第
１の導電パターン（２）と銅箔（７）とを接続して、残
りのドライフィルム（９）を除去する。As shown in Figure 1E, the via hole and the copper foil (7) around the via hole are exposed, and electroless copper plating is performed to connect the first conductive pattern (2) and the copper foil (7). and remove the remaining dry film (9).
次に第１図Ｇ及び第１図Ｈに示す如く、銅箔り７）をエ
ツチングして笛２の導電パターン（１０）錯形成する。Next, as shown in FIGS. 1G and 1H, the copper foil 7) is etched to form a conductive pattern (10) of the flute 2.
ドライフィルム除去後、再び絶縁基板（１）全面にドラ
イフィルムを熱圧着して写真蝕刻法により、第１図Ｇの
如く、第２の導電パターン（１０）となる銅箔（７）上
及び樹脂コート膜（３）内の第１の導電パターン（２）
上のみにドライフィルム（９′）を残して他の部分を除
去した後、鋼箔（７〉をエツチングすることにより、第
１図Ｈの如く、第１の導電パターン（２）上に第２の導
電パターン（１０）を形成することができる。After the dry film is removed, the dry film is again hot-pressed onto the entire surface of the insulating substrate (1), and photolithography is applied to form the second conductive pattern (10) on the copper foil (7) and the resin. First conductive pattern (2) within coat film (3)
After leaving the dry film (9') only on the top and removing the other parts, the steel foil (7) is etched to form a second conductive pattern (2) on the first conductive pattern (2) as shown in Figure 1H. conductive pattern (10) can be formed.
第１図Ｇに示した工程において、樹脂コート膜（３）内
の第１の導電パターン（２）上にドライフィルム（９′
）を残す場合、写真蝕刻法により微細加工に形成するこ
とができるが、マスクの位置ズレ等でドライフィルム（
９゛）と絶縁樹脂（８）との間に微小に隙間が発生し銅
箔エツチング時に隙間からエッチャントが入り第１の導
電パターン（２）を蝕刻する恐れがあるが本発明では樹
脂コート膜（３）が形成されているので第１の導電パタ
ーン（２）が蝕刻される恐れはない。In the step shown in FIG. 1G, a dry film (9'
) can be finely processed by photolithography, but the dry film (
There is a possibility that a minute gap is generated between the resin coated film (9') and the insulating resin (8), and the etchant enters through the gap during etching of the copper foil and etches the first conductive pattern (2). 3), there is no fear that the first conductive pattern (2) will be etched.
（ト）発明の効果
以上に詳述した如く、本発明に依れば、第２の導電パタ
ーンを銅箔により形成することができ、第２の導電パタ
ーンの断線を防止することができる。(g) Effects of the Invention As detailed above, according to the present invention, the second conductive pattern can be formed of copper foil, and disconnection of the second conductive pattern can be prevented.
また本発明では開口部が設けられているため、第１の導
電パターン上に回路素子を固着することができるので、
熱抵抗を損なうことなく発熱を有する回路素子を搭載す
ることができる。Further, in the present invention, since the opening is provided, the circuit element can be fixed on the first conductive pattern.
Circuit elements that generate heat can be mounted without impairing thermal resistance.
第１図Ａ乃至第１図Ｈは本発明の実施例を示す断面図、
第２図Ａ乃至第２図Ｃは従来例を示す断面図である。
（１）・・・絶縁基板、 （２）・・・第１の導電パタ
ーン、（３）・・・樹脂コート膜、 （４）・・・開口
部、 （５）・・・孔、 （６）・・・金属箔付き樹脂
、 （７）・・・銅箔、（８）・・・絶縁樹脂、（９）
（９’）・・・ドライフィルム、（１０）・・・第２の
導電パターン。1A to 1H are cross-sectional views showing embodiments of the present invention,
FIGS. 2A to 2C are sectional views showing a conventional example. (1)... Insulating substrate, (2)... First conductive pattern, (3)... Resin coat film, (4)... Opening, (5)... Hole, (6 )...Resin with metal foil, (7)...Copper foil, (8)...Insulating resin, (9)
(9')...Dry film, (10)...Second conductive pattern.
Claims (1)
と、前記第１の導電パターン上に前記パターンの一部分
を囲む樹脂コート膜を形成する工程と、前記樹脂コート
膜に対応する開口部及びバイアホール用の孔を金属箔付
き樹脂層に設けた後、前記金属箔付き樹脂層を前記絶縁
基板上に貼着する工程と、前記孔から形成されたバイア
ホールに電気メッキを施し前記第１の導電パターンと前
記金属箔とを接続する工程と、前記金属箔をエッチング
し第２の導電パターンを形成する工程とを具備すること
を特徴とする多層配線基板の製造方法。(1) A step of forming a first conductive pattern on an insulating substrate, a step of forming a resin coat film surrounding a part of the pattern on the first conductive pattern, and an opening corresponding to the resin coat film. and after providing a hole for a via hole in the resin layer with metal foil, adhering the resin layer with metal foil on the insulating substrate, and electroplating the via hole formed from the hole. A method for manufacturing a multilayer wiring board, comprising the steps of: connecting a first conductive pattern and the metal foil; and etching the metal foil to form a second conductive pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62286205A JPH01128493A (en) | 1987-11-12 | 1987-11-12 | Manufacture of multilayer interconnection substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62286205A JPH01128493A (en) | 1987-11-12 | 1987-11-12 | Manufacture of multilayer interconnection substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01128493A true JPH01128493A (en) | 1989-05-22 |
| JPH0450760B2 JPH0450760B2 (en) | 1992-08-17 |
Family
ID=17701327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62286205A Granted JPH01128493A (en) | 1987-11-12 | 1987-11-12 | Manufacture of multilayer interconnection substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01128493A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036096A (en) * | 1989-06-02 | 1991-01-11 | Matsushita Electric Works Ltd | Circuit board |
| JPH04250694A (en) * | 1991-01-28 | 1992-09-07 | Matsushita Electric Works Ltd | Manufacture of multilayer circuit board |
-
1987
- 1987-11-12 JP JP62286205A patent/JPH01128493A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036096A (en) * | 1989-06-02 | 1991-01-11 | Matsushita Electric Works Ltd | Circuit board |
| JPH04250694A (en) * | 1991-01-28 | 1992-09-07 | Matsushita Electric Works Ltd | Manufacture of multilayer circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0450760B2 (en) | 1992-08-17 |
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