JPH11203232A - Information processing device and input/output control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of accesses by way of a system bus regarding input/output control information. SOLUTION: An input/output control memory 35 for retaining input/output control information is provided inside an input/output control device. Thus, an access to the input/output control information that is frequently generated from an input/output control circuit 36 can be performed without a data bus 5 and an address bus 6 intervened. Since a main storage device 2 is not made to store the input/output control information, central processing units 11 and 12 set an address of the input/output control memory 35 in an address register 32 and tries to access to the input/output control information. An address selection circuit 34 selects either the address register 32 or an address register 33 and supplies the input/output control memory 35 with it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to access to input / output control information.

[0002]

2. Description of the Related Art Referring to FIG.
A conventional technique described in Japanese Patent Application Laid-Open Publication No. H10-26095 will be described. This system includes a host computer 102, an input / output control device 10
1 and an input / output device 150 such as a magnetic disk device or a magnetic tape device. The input / output control device 101 includes a plurality of ports 110 corresponding to each host computer 102.
And a device control unit (device control unit) 120 for controlling the input / output device 150. The port 110 executes an interface circuit 114 connected to the host 102 through the host interface 103 and an interface (hereinafter abbreviated as [I / F]) with the host computer 102 through the protocol control processing path 161 and the like. A host I / F control logic unit 111; an input / output buffer memory 115 for storing input / output information such as command information issued by the host computer 102 and response information from the device control unit 120; Port I / that displays and manages the input status of
F register 113 and the input / output buffer memory 115
And a data transfer circuit 112 for transferring the input / output control information.

The device control unit 120 includes an MPU (microprocessor unit) 121 and, as its peripheral circuits, a device control circuit 140, a data buffer 130 for input / output data to / from the input / output device 150, It has a device data transfer circuit 122 for controlling data transfer between the buffers 130, a control path for the device control circuit 140, and a transfer control path 172. The input / output buffer 115 has a stack management address table 200, a command buffer 201 for storing commands from the host computer 102, and a response buffer 202 for storing responses from the device control unit 120.

As a feature of this example of the prior art, an input / output buffer 115 is provided for temporarily storing input / output control information such as commands and responses, and a port I / F register 113 is provided. , For displaying, setting, and managing the input state of the input / output buffer. The host I / F control logic unit 111 and the microprocessor 121 of each port are provided with independent buffer management logic units, respectively. The buffer management units of both the host I / F control logic unit and the microprocessor 121 The buffer state of the input / output buffer 115 is arbitrarily and independently managed through the I / F register 113. As a result, the host computer 1 is
The input / output processing on the 02 side and the input / output processing on the device control unit 120 side from the port 110 can be performed asynchronously with each other.

[0005]

In the conventional information processing apparatus described above, the input / output control information is held in a specific area of the main memory, and each PCU and the input / output control apparatus update / refer to the contents as needed. doing. However, the number of main memory accesses to input / output control information has been increasing due to an increase in the number of connected input / output devices and an improvement in CPU performance. On the other hand, the bus performance between the CPU and the main memory is approaching the technological limit, and if the performance of the CPU alone improves, the system performance cannot be improved due to the limit of the main memory bus. It could be.

An object of the present invention is to improve system performance by reducing the usage rate of a system bus in an information processing apparatus having a system bus as a component.

[0007]

According to the present invention, there is provided an information processing apparatus comprising a central processing unit, a main storage device, and an input / output device. An I / O control dedicated memory for storing I / O control information is provided between the CPU and the output control device, and an address that does not overlap with the address of the main storage device is assigned as an address of the I / O control dedicated memory. An access from the output control device to the input / output control dedicated storage is performed in the same manner as the access to the main storage device.

An input / output control device according to the present invention is an input / output control device used in the information processing device, wherein the input / output control device includes a first address register for storing an access address and a command from a central processing unit; A second address register for storing an access address and a command from a device, and an address / command selection circuit for selecting one of the first address register and the second address register depending on whether or not there is access from the input / output device When,
An output of the address / command selection circuit is supplied to the input / output control dedicated memory.

In the present invention, the input / output control information access from the central processing unit is performed to the input / output control information dedicated storage via the system bus, but the input / output control information access from the input / output control device is performed on the system bus. Do not use In general, when accessing I / O control information, the frequency of access from the I / O controller is higher than the frequency of access from the central processing unit. Thus, the degree of contention of the system bus at the time of accessing the main storage device is reduced, and as a result, the system performance can be improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of an information processing apparatus to which the present invention is applied. The information processing apparatus includes two central processing units 11 and 12, a main storage device 2, an input / output control device, and four input / output devices 41 to 44. .

The input / output device 3 is connected to the main storage device 2 and the input / output device 41 in accordance with an instruction from the central processing unit 11 or 12.
To 44 are controlled. The input / output control device 3 includes a bus control circuit 31, two address registers 32 and 33, an address selection circuit 34, an input / output control memory 35, an input / output control circuit 36, and seven buffers 37-3.
9, 310 to 313. The state of each of the input / output devices 41 to 44 is reflected in the input / output control memory 35,
All of the input / output control information conventionally stored in the main storage device 2 is stored therein, and can be referenced / updated from the central processing units 11, 12 and the input / output control circuit 36.

FIG. 2 shows a configuration example of the bus control circuit 31. The bus control circuit 31 includes two address comparators 31.
-1, 31-2, command selection circuit 31-3, command decoder 31-4, NOT circuit 31-5, four OR circuits 31-6 to 31-9, and eight AND circuits 31-1
0 to 31-17.

Next, the operation of this embodiment will be described in detail with reference to FIGS. 1, 2, and 3 (flow chart). When accessing the input / output control memory 35 from the central processing unit 11 or the central processing unit 12 (S
1, S2), the memory address is held in the address register 32 via the buffer 37. Address comparator 31
If the address is determined to be an address assigned to the input / output control memory 35 by -1, the instruction from the bus control circuit 31 (actually, the input / output control circuit 36 in FIG. The output of the address register 32 is selected by the address selection circuit 34 according to the signal input to S34 (S3 in FIG. 3). In the case of updating the memory (S4, S5), the data output from the central processing units 11, 12 is stored in the buffers 312, 3
The data is written to the address output from the address selection circuit 34 via the address 10 (S7). For memory references,
Data corresponding to the address of the output of the address selection circuit 34 in the input / output control memory 35 is stored in buffers 311, 31
3 to the central processing units 11 and 12 (S
6).

FIG. 2 shows the above control path, which indicates that the access from the central processing units 11 and 12 is based on the address comparator 31-1, the NOT circuit 31-5, and the OR circuits 31-6 and 31-7. And an AND circuit 31-18, and whether to update or refer to the memory is instructed by selecting the address register 32 by the command selecting circuit 31-3 and decoding the command by the command decoder 31-4. As a result, in the case of updating the memory, the AND circuit 31
-12, 31-13 and OR circuit 31-8, buffers 312, 310, and in case of memory reference, AND circuit 31-
14, 31-17 and the OR circuit 31-17 are respectively enabled.

In referring to and updating the input / output control memory 35 from the input / output control circuit 36 (S8, S9), the memory address is held in the address register 33. When it is determined by the address comparators 31 and 2 that the address is an address assigned to the input / output control memory 35, the output of the address register 33 is output from the address selection circuit 34 by the instruction from the bus control circuit 31. Selected (S10). Reference and updating of the input / output control memory 35 from the input / output control circuit 36 are performed as in the case of the central processing units 11 and 12 (S11 to S1).
4).

2 shows that the access from the input / output control circuit 36 corresponds to the address comparator 31-2, the AND circuit 31-10, and the OR circuit 3.
Instructed by 1-7, whether memory update or memory reference
Address register 33 by command selection circuit 31-3
And the command decoder 31-4 decodes the command. As a result, in the case of memory update, A
ND circuit 31-13, AND circuit 3 for memory reference
1-14 will be enabled respectively.

The input / output control circuit 36 is connected to the main storage 2
In FIG. 2, the output of the address comparator 31-2 becomes "0" in FIG.
The output of No. 11 becomes "1". As a result, the buffer 313 is provided by the AND circuit 31-16 and the OR circuit 31-9 in the case of memory update, and the AND circuit 31 in the case of memory reference.
The buffer 312 is enabled by the -15 and the OR circuit 31-8, respectively, so that a write path and a read path are formed between the input / output control circuit 36 and the main storage device 2.

The state of each of the input / output devices 41 to 44 is held in the input / output control memory 35, and each time an input / output operation is performed, the input / output device 41
The area corresponding to .about.44 is updated. For example, at the start of the input / output operation, the state of the input / output device is “operating”, and at the end of the input / output operation, “end interrupt pending”.

Since the channel program pointer and the pointer of the data transfer area are also reflected in the input / output control memory 35, the input / output control circuit 36 accesses the input / output control memory a plurality of times during the input / output operation. . In the present invention, in the input / output control memory access from the input / output control circuit 36, the bus (data bus 5) of the main storage device 2 is used.
And the address bus 6) is not used. Therefore, performance degradation of the central processing units 11 and 12 due to contention for access to the main storage device in input / output control is reduced as compared with the conventional method in which input / output control information is managed on the main storage device 2.

FIG. 4 shows an information processing apparatus according to another embodiment of the present invention. This embodiment is characterized in that a dedicated access path from the input / output control circuit 36 to the main storage device 2 is provided on the right side of the information processing apparatus shown in FIG. That is, when the main storage device 2 is accessed from the input / output control circuit 36, the main storage device 2 is connected to the address bus 6 through the route of the buffer 314, the address register 40, and the buffer 315.
The buffer 316 or 317 connects to the data bus 5.

As a result, access from the input / output control circuit 36 to the main storage device 2 and access from the central processing units 11, 12 or the input / output control circuit 36 to the input / output control memory 35 can be performed simultaneously.

[0022]

According to the information processing apparatus of the present invention, an input / output control dedicated memory for storing the input / output control information is provided in the input / output control apparatus, and the input / output control information conventionally existing on the main storage apparatus is provided. Is stored in the input / output control dedicated storage, so that the frequency of use of the system bus for input / output control information access can be reduced, and the system performance can be improved.

[Brief description of the drawings]

FIG. 1 is an embodiment of an information processing apparatus according to the present invention.

FIG. 2 is a detailed diagram of a bus control circuit in FIG. 1;

FIG. 3 is an operation flow in the information processing apparatus shown in FIG. 1;

FIG. 4 shows another embodiment of the information processing apparatus of the present invention.

FIG. 5 shows a conventional information processing apparatus.

[Explanation of symbols]

 11, 12 Central processing unit 2 Main storage device 3, 101 I / O control device 31 Bus control circuit 32, 33, 40 Address register 34 Address selection circuit 35 I / O control memory 36 I / O control circuit 37-39 Buffer 310-317 Buffer 31-1, 31-2 Address Comparator 31-3 Command Selection Circuit 31-4 Command Decoder 31-5 NOT Circuit 31-6-9 OR Circuit 31-10-17 AND Circuit 41-44 Input / Output Device 102 Host Computer 103 Host interface 110 Port 111 Host I / F control logic unit 112 Data transfer circuit 113 Port I / F register 114 Interface circuit 115 Input / output buffer memory 120 Device control unit 121 Microprocessor unit 122 Device data transfer Circuit 130 Data buffer 140 Device control circuit 150 Device control unit

Claims (4)

[Claims] 1. An information processing device comprising a central processing unit, a main storage device, and an input / output device, wherein each device is connected by a bus, wherein input / output control information is transferred between the bus and the input / output control device. A dedicated memory for input / output control for storage is provided,
An address that does not overlap with the address of the main storage device is assigned as the address of the I / O control dedicated storage, and access from the central processing unit and the I / O control device to the I / O control dedicated storage is performed in the same manner as the main storage device access. An information processing device characterized by performing. 2. The information processing apparatus according to claim 1, wherein the access from the input / output device to the main storage device is performed by a dedicated path provided separately from an access path to the input / output control dedicated storage. apparatus. 3. The input / output control device according to claim 1, wherein the first address register stores an access address and a command from the central processing unit, and an access address from the input / output device. A second address register for storing an address and a command, an address / command selection circuit for selecting one of the first address register and the second address register depending on whether or not there is access from the input / output device; An input / output control device for supplying an output of a command selection circuit to the input / output control dedicated storage. 4. An address comparison circuit for comparing outputs of the first address register and the second address register with predetermined values, respectively, and a plurality of buffers provided between the input / output control storage and the bus. 4. The input / output control device according to claim 3, wherein the buffer is opened / closed by a combination of outputs of the address / command selection circuit and the comparison circuit.