JPH11220094A - Input protection circuit - Google Patents

Abstract

(57) [Problem] To provide an input protection circuit capable of reducing a circuit layout area and suppressing an increase in input capacitance without lowering protection capability. A low-pass filter including a resistance element and a parasitic capacitance in a resistance section suppresses a peak level of a high-voltage pulse signal generated on an input pad due to static electricity or the like. When the peak level of the suppressed pulse signal exceeds the power supply voltage V _CC or when the peak level is lower than the ground potential GND, the voltage limiting circuit 30
a clamps the peak level of the pulse signal,
Because it is limited to approximately between the ground potential GND level and the power supply voltage V _CC level, the level of the signal applied to the input terminal of the input buffer 40 is limited to within this range, the input buffer 40 and the internal circuit due to static electricity Destruction is prevented. Further, the parasitic capacitance of the input pad can be reduced, and the layout area of the input protection circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC chip formed between an input pad of an IC chip and an input terminal of an internal circuit, which suppresses a peak voltage of a high voltage pulse generated at the input pad due to static electricity. The present invention relates to an input protection circuit that improves electrostatic withstand voltage and prevents damage to an IC chip due to static electricity.

[0002]

2. Description of the Related Art In recent years, as the speed of a semiconductor integrated circuit (IC circuit) has increased, the electrostatic breakdown voltage of an IC chip has been ensured without increasing the input capacitance and without causing a signal delay. It is becoming increasingly important to prevent the destruction of IC chips. In order to achieve this object, an input protection circuit is generally provided between an input pad of an IC chip and an input terminal of an internal circuit.

FIG. 6 shows an example of an input protection circuit generally formed on an IC chip. As illustrated, the input protection circuit of the present example includes an input pad 10, a resistance unit 20, a voltage limiting circuit 30, and an input buffer 40. The input pad 10 is made of, for example, aluminum (A
1) formed in the metal wiring layer. Resistance part 2
Numeral 0 denotes a resistance element R1 formed between the input pad 10 and the voltage limiting circuit 30, and the resistance element R1 is a parasitic resistance element formed by a normal wiring or a resistance element inserted by a diffusion layer. The voltage limiting circuit 30 includes a pMOS transistor 31 and an nMOS transistor 32. The gate electrode and the source diffusion layer of the pMOS transistor 31 are connected to the power supply voltage V _CC, nMOS
The gate electrode and the source diffusion layer of the transistor 32 are both connected to a common potential, for example, a ground potential GND. A signal line composed of, for example, a metal wiring 33 is formed between the resistance section 20 and the input terminal of the input buffer 40, and the drain diffusion layers of the pMOS transistor 31 and the nMOS transistor 32 are both connected to the metal wiring 33.

FIG. 7 shows an equivalent circuit of the above-mentioned input protection circuit. As shown, in the equivalent circuit,
A parasitic capacitance C is provided between the input pad 10 and the ground potential GND.
p1 exists, and a parasitic capacitance Cp2 exists between the resistance element R1 and the ground potential GND. Also, the voltage limiting circuit 3
0, the pMOS transistor 31 is connected to the metal wiring 3
3 toward the power supply voltage V _CC constitute the diode D1 as a forward direction, nMOS transistor 32 forms a diode D2 whose forward direction toward the metal wires 33 from the ground potential GND. Metal wiring 33 and power supply voltage V _CC
A parasitic capacitance Cp3 composed of the drain diffusion junction capacitance of the pMOS transistor 31 exists between the metal wiring 33 and the ground potential GND, and a parasitic capacitance Cp4 composed of the drain diffusion junction capacitance of the nMOS transistor 32 exists between the metal wiring 33 and the ground potential GND. . The input buffer 40 has pM
It comprises an OS transistor 41 and an nMOS transistor 42. The gate of the pMOS transistor 41 is connected to the metal wiring 33 together with the gate of the nMOS transistor 42. The source diffusion layer of the pMOS transistor 41 is connected to the power source voltage V _CC, the source diffusion layer of the nMOS transistor 42 is connected to the ground potential GND. Further, the pMOS transistor 41 and the nMOS
The drains of the transistors 42 are commonly connected, and the connection point is connected to an input terminal of an internal circuit (not shown).

FIGS. 8 and 9 show signal waveforms at various parts of the equivalent circuit shown in FIG. 7, and show the principle of the input protection circuit of this embodiment. As shown in FIG. 8, for example, a positive pulse signal having a high voltage is instantaneously generated at the input pad 10 due to static electricity or the like. Since a low-pass filter is formed by the resistance element R1 and the parasitic capacitances Cp3 and Cp4 of the voltage limiting circuit 30, high-frequency components of the pulse appearing on the input pad are suppressed, and the peak voltage of the pulse is suppressed.

When the peak voltage of the pulse suppressed by the low-pass filter is higher than the power supply voltage V _CC , the diode D1 is in a conductive state in the voltage limiting circuit 30, and the electric charge accumulated in the metal wiring 33 by the pulse becomes the diode D1.
1, the potential of the metal wiring 33 is clamped to the power supply voltage V _CC level.

Further, as shown in FIG. 9, when a negative pulse having a high voltage appears on the input pad 10 due to, for example, static electricity, a low-pass filter is formed by the resistor R1 and the parasitic capacitances Cp3 and Cp4 of the voltage limiting circuit 30. As a result, the high frequency component of the pulse generated at the input pad is suppressed, and the peak voltage of the pulse is suppressed. Further, when the potential of the negative pulse suppressed by the low-pass filter is lower than the ground potential GND, the diode D2 is in a conductive state, and the charges accumulated on the ground line side pass through the diode D2 to the metal wiring 33, so that the metal The potential of the wiring 33 is clamped to the ground potential GND level.

As described above, when a high-voltage positive or negative pulse is generated on the input pad 10 due to static electricity or the like, the pulse generated by the low-pass filter including the resistance element R1 and the parasitic capacitances Cp3 and Cp4. Is suppressed. Further, when the peak voltage of the suppressed pulse exceeds the power supply voltage V _CC , the diode D1
Is conducted, and the potential of the metal wiring 33 as an input signal line is clamped to the level of the power supply voltage V _CC . Alternatively, the peak voltage of the pulse suppressed by the low-pass filter is equal to the ground potential G.
When the voltage is lower than ND, the diode D2 conducts, and the potential of the input signal line is clamped to the level of the ground potential GND.

[0009]

By the way, in order to increase the protection capability of the above-mentioned conventional input protection circuit, it is necessary to increase the capacitance values of the parasitic capacitances Cp3 and Cp4 attached to the voltage limiting circuit 30, that is, to increase the pMOS transistor 31. It is effective to increase the size of the nMOS transistor 32 and increase the resistance value of the resistance element R1. However, increasing the resistance value of the resistance element R1 results in burning of the resistance itself or increasing the delay of an input signal, and there is a limit to the increase in the resistance value. It is necessary to increase the size of. On the other hand, the input capacitance of the circuit viewed from the input pad 10 is the sum of the capacitances of the parasitic capacitances Cp1 to Cp5. Since the input capacitance becomes a load capacitance when the external circuit drives the IC chip, it is desirable to make the input capacitance as small as possible. Therefore, in the conventional input protection circuit, there is a disadvantage that the size of the input protection circuit must be determined by a trade-off between the desired input protection capability and the allowable value of the input capacitance.

Furthermore, the input pad 10 needs a large area for performing bonding, probing, and the like.
A large parasitic capacitance occurs between the metal wiring and the substrate. This parasitic capacitance is added to the input capacitance as useless capacitance, and I
This causes an increase in the input capacitance of the C chip.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the layout area by making the parasitic capacitance of the input pad useless for the conventional input protection circuit to contribute to the input protection function. An object of the present invention is to provide an input protection circuit which can be reduced in size and can suppress an increase in input capacitance.

[0012]

In order to achieve the above object, an input protection circuit according to the present invention comprises a first substrate formed on a surface of a semiconductor substrate at least electrically separated from the semiconductor substrate.
An input protection circuit comprising: a metal wiring layer; and a second metal wiring layer formed on a surface of the first metal wiring layer so as to be electrically separated from the first metal wiring layer. An input pad formed in a layer, and below the input pad,
A metal wiring region formed in the first metal wiring layer according to the input pad; a metal wiring region formed in the first metal wiring layer; and an input pad formed in the second metal wiring layer. And a resistance element formed between them.

The input protection circuit according to the present invention further comprises a first metal wiring layer formed on the surface of the semiconductor substrate at least electrically separated from the semiconductor substrate, and a first metal wiring layer formed on the surface of the first metal wiring layer. An input protection circuit having a metal wiring layer and a second metal wiring layer electrically separated and formed, wherein the input pad formed on the second metal wiring layer, and the input pad below the input pad, A metal wiring region formed in the first metal wiring layer in accordance with the input pad; and a metal wiring region formed in the first metal wiring layer and the input pad formed in the second metal wiring layer. The semiconductor device includes a resistance element formed therebetween and an input buffer having an input terminal connected to the metal wiring region.

In the present invention, preferably, the metal wiring region formed in the first metal wiring layer is formed to be substantially the same size as the input pad or larger than the input pad.

Furthermore, in the present invention, preferably, the first
A first metal wiring layer having a metal wiring formed between the metal wiring region and the input terminal of the input buffer, an anode connected to the metal wiring, and a cathode connected to the power supply voltage; And a second diode having an anode connected to a common potential and a cathode connected to the metal wiring. The input buffer further includes a gate electrode connected to the metal wiring, a source A first conductivity type insulated gate field effect transistor having a diffusion layer connected to a power supply voltage; a gate electrode connected to the metal wiring; a source diffusion layer connected to a common potential; A second conductivity type insulated gate field effect transistor connected to the input terminal of the internal circuit together with the drain of the gate field effect transistor.

According to the present invention, the first surface is provided on the surface of the semiconductor substrate.
A metal wiring layer is formed, a second metal wiring layer is further formed on the surface thereof, an input pad is formed on the second metal wiring layer, and a first metal wiring layer below the metal pad has substantially the same size or input as the input pad. A metal wiring area larger than the pad is formed. A resistance element is formed between the metal wiring region and the input pad, and a signal line made of a metal wiring is formed between the metal region and the input terminal of the input buffer. The signal line and the power supply voltage or the signal line are formed. And a common potential, respectively, a diode is formed. A parasitic capacitance exists between the first metal wiring layer and the substrate or between the first metal wiring layer and the second metal wiring layer, and the parasitic capacitance exists between the resistance element and the parasitic capacitance between the first metal wiring layer and the substrate. When a low-pass filter is formed and a high-voltage pulse is generated on the input pad due to static electricity or the like, the high-frequency component of the pulse is attenuated by the low-pass filter, and the peak voltage of the pulse is suppressed. Further, when the peak level of the suppressed pulse is higher than the power supply voltage or lower than the common potential, the diode clamps the peak level of the pulse to approximately the power supply voltage or the common potential.

As a result, the input capacitance of the IC chip can be reduced without lowering the protection ability for preventing electrostatic breakdown, so that the load on the external drive circuit can be kept small and the operation speed can be improved. Further, the size of the MOS transistor constituting the diode can be reduced, and the circuit layout area can be reduced.

[0018]

FIG. 1 is a simplified plan view showing one embodiment of an input protection circuit according to the present invention. As shown,
In the input protection circuit of the present embodiment, a second metal wiring layer (second metal wiring layer) is formed on the surface of a first metal wiring layer (first metal wiring layer) formed on the surface of the semiconductor substrate 1. And
An input pad 10a is formed in the second metal wiring layer,
Further, a metal wiring region 5 having the same size as or larger than the input pad 10a is formed in the first metal wiring layer below the input pad 10a. An input pad window 9 is formed on the surface of the input pad 10a. During bonding, copper (Au) or aluminum (not shown) is provided between the input pad 10a and a lead frame (not shown) through the input pad window 9, for example. Al) is connected to the metal wire (wire). The metal wiring region 5 is connected to, for example, an input terminal of an input buffer via a signal line 6 also formed in the first metal wiring layer.

FIG. 2 is a simplified sectional view showing the configuration of the input protection circuit of the present embodiment. Hereinafter, the configuration of the input protection circuit according to the present embodiment will be described with reference to FIGS. The input pad 10a is connected to a minute wiring region 7b formed in the first metal wiring layer via a contact 8 formed between the second metal wiring layer and the first metal wiring layer.
Is connected to As shown in the figure, a polysilicon layer 2 made of, for example, polysilicon is formed between a first metal wiring layer and a substrate 1. Although not shown, an insulating layer made of, for example, silicon oxide (SiO ₂ ) is formed between the substrate 1 and the polysilicon layer 2.
Similarly, an insulating layer made of silicon oxide is formed between the first metal wiring layer and the substrate 1, and furthermore, for example, silicon oxide is formed between the first metal wiring layer and the second metal wiring layer. Is formed. Therefore, the polysilicon layer 2 is insulated from the substrate 1 or the first metal wiring layer, and similarly, the first metal wiring layer is insulated from the substrate 1 or the second metal wiring layer. As contacts are formed between these insulated layers, signal transfer occurs between the different layers through these contacts.

For example, as shown in FIG. 2, the fine wiring region 7b formed in the first metal wiring layer and the polysilicon layer 2
, A contact 4 is formed, and a fine wiring region 7 formed in the polysilicon layer 2 and the first metal wiring layer is further formed.
The contact 3 is formed between the contact 3a. Note that the minute wiring region 7 a formed in the first metal wiring layer is connected to the metal wiring region 5.

A signal input to the input pad 10a is transferred to the minute wiring region 7b formed in the second metal wiring layer via the contact 8, and further transferred to the polysilicon layer 2 via the contact 4. . As shown, the polysilicon layer 2 between the contacts 3 and 4 is formed in a predetermined shape. Therefore, the polysilicon layer 2 generates a predetermined resistance between the contact 3 and the contact 4. That is, in the present embodiment, a resistance element is constituted by the polysilicon layer 2. In the present embodiment, the resistance element formed on the polysilicon layer 2 is given as an example, but the present invention is not limited to this.
The elements that form the resistance between the input pad 10a and the metal wiring region 5 and the layout shape thereof are not particularly limited.

The signal transmitted to the minute wiring region 7b is transferred to the minute wiring region 7a formed in the second metal wiring layer via the resistor 3 and the contact 3 formed in the polysilicon layer 2, and Further, the data is transferred to the wiring area 5. Via a signal line 6 connected to the wiring region 5, for example,
The signal is input to an input terminal of an input buffer not shown in FIGS.

FIG. 3 is a simplified sectional view showing the wiring region 5 formed below the input pad 10a, the input pad 10a, and the parasitic capacitance between the wiring region 5 and the substrate 1. Less than,
The principle of the input protection circuit according to the present embodiment will be described with reference to FIG. There are, for example, parasitic capacitances Cp ₂₁ , Cp ₂₂ ,..., Cp _2n between the wiring region 5 and the substrate 1. Between the wiring region 5 and the input pad 10a, for example, the parasitic capacitance Cp
_11, Cp _12, ..., has a Cp _1m. As shown in FIG.
A polysilicon layer 2 and a first metal wiring layer are formed between the input pad 10a and the substrate 1 of the present embodiment. Therefore, the parasitic capacitance between the input pad 10a and the substrate 1 is suppressed, the capacitance value is extremely small, and the input capacitance as viewed from the input pad 10a is small. Since the input capacitance of the input pad becomes a load when the external circuit drives the IC chip, the input protection circuit of the present embodiment suppresses the load capacitance and facilitates high-speed driving.

The resistance element R1 is equivalently formed by the polysilicon layer 2. That is, the resistance element R1 is connected between the input pad 10a and the wiring region 5 formed thereunder.

FIG. 4 is a diagram showing an equivalent circuit in the portion of the input pad 10a and the wiring region 5. FIG.
, The wiring region 5 is simply represented in the form of a signal line. The signal line is connected to the input terminal of the input buffer on the circuit configuration. As shown, the input pad 10a
A parasitic capacitance Cp6 exists between the wiring region 5 and the wiring region 5, and a parasitic capacitance Cp7 exists between the wiring region 5 and the substrate 1. Here, parasitic capacitance Cp6 the parasitic capacitance Cp _11, Cp ₁₂ in the equivalent circuit shown in FIG. 3, ..., an equivalent capacitance of the sum of the capacitance of Cp _{1 m,} the parasitic capacitance Cp7 is in the equivalent circuit shown in FIG. 3 Parasitic capacitances Cp ₂₁ , Cp ₂₂ ,..., Cp
_This is an equivalent capacitance having a total value of _2n capacitances. Since the substrate 1 is normally held at the ground potential GND, the parasitic capacitance Cp7
Is equivalent to the wiring region 5 as shown in the equivalent circuit of FIG.
And the ground potential GND.

A pulse signal having a high voltage is instantaneously generated at the input pad 10a due to static electricity or the like. When this pulse is transmitted to the input side of the semiconductor device through the signal line 6, the semiconductor device may be broken. So-called electrostatic breakdown occurs. In the input protection circuit of the present invention, since the low-pass filter is formed by the equivalent resistance element R1 formed by the polysilicon layer 2 and the parasitic capacitance Cp7, the high-frequency component of the pulse appearing on the input pad 10a is suppressed,
The peak voltage of the pulse is suppressed.

A pulse signal whose peak level is suppressed is output to the wiring region 5 and further applied to the input side of the input buffer via the signal line 6. At this time, the level of the pulse signal applied to the input buffer may exceed the power supply voltage V _CC or be lower than the ground potential GND. This can be addressed to the input side of the input buffer by providing a voltage limiting circuit that limits between the peak level of the pulse signal and the power supply voltage V _CC and the ground potential GND.

FIG. 5 shows a configuration example of an input protection circuit to which a voltage limiting circuit is added. As shown, the input protection circuit of the present example includes an input pad 10a, a resistor 20a, a voltage limiting circuit 30a, and an input buffer 40.

The input pad 10a is a metal wiring region having a predetermined area formed in the second metal wiring layer as shown in the plan view of FIG. 1 and the cross-sectional view of FIG. The input pad 10a is connected to a metal wiring region 5 formed in a first metal wiring layer below the input pad 10a via, for example, a resistance element R1 formed of the polysilicon layer 2. As shown, the input pad 10a and the ground potential G
Although the parasitic capacitance Cp0 exists between the polysilicon layer 2 and the polysilicon layer 2 between the input pad 10a and the substrate 1, the parasitic capacitance Cp0 exists between the polysilicon layer 2 and the substrate 1 as described above.
Each of the metal wiring layers is laminated. For this reason,
Parasitic capacitance Cp0 between input pad 10a and substrate 1 is suppressed. That is, the input capacitance Cp0 of the input pad 10a is small, and the driving load is small when driven by an external circuit.
The resistance portion 20a includes a resistance element R1 formed in the polysilicon layer 2, a parasitic capacitance Cp6 existing between the wiring region 5 and the input pad, and a parasitic capacitance Cp7 existing between the wiring region 5 and the ground potential GND. .

As described above, in the resistance portion 20a,
A low-pass filter is formed by the resistance element R1 and the parasitic capacitance Cp7. With the low-pass filter, for example,
The high frequency component of the pulse generated on the input pad 10a due to static electricity or the like is suppressed, and the peak voltage of the pulse is suppressed.

The voltage limiting circuit 30a includes a pMOS transistor 35 and an nMOS transistor 36. The gate electrode and the source diffusion layer of the pMOS transistor 35 are both connected to the power source voltage V _CC, the gate electrode and the source diffusion layer of the nMOS transistor 36 are both connected to a common potential, for example ground potential GND. pM
The drain diffusion layers of the OS transistor 35 and the nMOS transistor 36 are both connected to the signal line 6.

Between the signal 6 and the power supply voltage V _CC , for example,
The parasitic capacitance Cp8 formed by the junction capacitance of the drain-source diffusion layer of the pMOS transistor 35 is connected, and similarly, nM is connected between the signal line 6 and the ground potential GND.
The parasitic capacitance Cp9 formed by the junction capacitance of the drain-source diffusion layer of the OS transistor 36 is connected.

In the voltage limiting circuit 30a, the pMOS transistor 35 and the nMOS transistor 36 are each diode-connected. That is, the power supply voltage V is equivalently supplied from the signal line 6 by the pMOS transistor 35.
_A diode is formed in the forward direction toward _CC , and nM
By the OS transistor 36, the ground potential GND is equivalently provided.
, And a diode is formed in the forward direction toward the signal line 6.

[0034] These diodes, for example, when the peak level of the applied pulse signal to the signal line 6 is higher than the power supply voltage V _CC, diodes composed of a transistor 35 is turned on, the transistor 35 threshold When the voltage is not considered, the potential of the signal line 6 is clamped to the power supply voltage V _CC level. _Assuming that the threshold voltage of the transistor 35 is V _th1 , the potential of the signal line 6 in this case becomes (V _CC + V _th1 ).

When the peak level of the pulse signal applied to the signal line 6 is lower than the ground potential GND, the diode constituted by the transistor 36 is turned on,
When the threshold voltage of the transistor 36 is not considered,
The potential of the signal line 6 is clamped to the ground potential GND. If the threshold voltage of the transistor 36 is V _th2 , the potential of the signal line 6 in this case becomes (−V _th2 ).

The input buffer 40 comprises a pMOS transistor 41 and an nMOS transistor 42. The gate of the pMOS transistor 41 is connected to the signal line 6 together with the gate of the nMOS transistor 42. The source diffusion layer of the pMOS transistor 41 is connected to the power source voltage V _CC, the source diffusion layer of the nMOS transistor 42 is connected to the ground potential GND. Furthermore, p
The drains of the MOS transistor 41 and the nMOS transistor 42 are commonly connected, and the connection point is connected to an input terminal of an internal circuit (not shown).

As described above, according to the present embodiment, the peak level of the high-voltage pulse signal generated on the input pad 10a due to static electricity or the like is suppressed by the low-pass filter including the resistance element R1 and the parasitic capacitance in the resistance section 20a. Is done. When the peak level of the suppressed pulse signal exceeds the power supply voltage V _CC or when the peak level is lower than the ground potential GND, the peak level of the pulse signal is clamped by the voltage limiting circuit 30a, and the level of the ground signal is substantially equal to the ground potential GND. And the level of the power supply voltage V _{CC, the} level of the signal applied to the input terminal of the input buffer 40 is limited within this range, thereby preventing the input buffer 40 and the internal circuit from being damaged by static electricity. .

Further, in this embodiment, as shown in FIG. 2, the input pad 10a is formed in the second metal wiring layer, and the resistor R1 is provided between the second metal wiring layer and the substrate 1. Since the polysilicon layer 2 and the first metal wiring layer to be formed are respectively formed, the parasitic capacitance between the input pad 10a and the substrate 1 can be greatly reduced as compared with the conventional input pad. It is possible. In the present embodiment, the capacitive element forming the low-pass filter mainly includes a parasitic capacitance Cp7 between the metal wiring region 5 formed in the first metal wiring layer and the substrate 1, and a transistor 35 in the voltage limiting circuit 30a. Parasitic capacitances Cp8 and Cp composed of the junction capacitance of the drain-source diffusion of
p9 is not a necessary component for forming a low-pass filter. Therefore, the voltage limiting circuit 30 of the present embodiment
The sizes of the transistors 35 and 36 constituting the “a” in FIG.
Since the size of the transistors 31 and 32 in the voltage limiting circuit 30 of the conventional input protection circuit shown in FIGS. 1 to 9 can be made smaller, the size of the entire input protection circuit can be reduced.

As a result of the above, in the input protection circuit of the present embodiment, the input capacitance of the input pad 10a is smaller than that of the conventional input protection circuit, that is, the load capacitance of the input pad 10a as viewed from the external circuit is smaller. In comparison with the input protection circuit, the operation speed can be easily improved. Further, since the size of the transistor constituting the voltage limiting circuit can be reduced without lowering the protection function of the input protection circuit, the layout area of the entire circuit can be reduced.

[0040]

As described above, according to the input protection circuit of the present invention, the parasitic capacitance applied to the input pad is suppressed,
Since the input load can be reduced, high-speed driving by an external circuit can be easily realized. Further, there is an advantage that the layout area of the entire input protection circuit can be reduced without lowering the input protection function, so that high integration of the semiconductor device and miniaturization of the IC chip can be realized.

[Brief description of the drawings]

FIG. 1 is a simplified plan view showing an embodiment of an input protection circuit according to the present invention.

FIG. 2 is a simplified cross-sectional view illustrating a configuration of the input protection circuit according to the present embodiment.

FIG. 3 is a simplified sectional view showing a parasitic capacitance of the input protection circuit according to the embodiment.

FIG. 4 is an equivalent circuit of the present embodiment.

FIG. 5 is a circuit diagram showing a configuration example of the input protection circuit of the present invention.

FIG. 6 is a circuit diagram showing a configuration example of a conventional input protection circuit.

FIG. 7 is a circuit diagram showing an equivalent circuit of the conventional input protection circuit shown in FIG.

FIG. 8 is a diagram showing an equivalent circuit of a conventional input protection circuit and a signal waveform of each part.

FIG. 9 is a diagram illustrating an equivalent circuit of a conventional input protection circuit and waveforms of respective partial signals, and illustrating an operation principle.

[Explanation of symbols]

1 ... substrate, 2 ... polysilicon layer, 3,4 ... contact,
5: metal wiring area, 6: signal line, 7a, 7b: minute wiring area, 8: contact, 9: input pad window, 10, 10
a: input pad, 20, 20a: resistor, 30, 30a
... voltage limiting circuit, 40 ... input buffer, 31, 35, 4
1 ... pMOS transistor, 32, 36, 42 ... nMO
S transistor, R1 ... resistance element, Cp0, Cp1, C
p2, Cp3, Cp4, Cp5, Cp6, Cp7, Cp
8, Cp9 ... parasitic capacitance, V _CC ... the power supply voltage, GND ... ground potential.

Claims (11)

[Claims] A first metal wiring layer formed on the surface of the semiconductor substrate at least electrically separated from the semiconductor substrate; and a first metal wiring layer electrically separated from the first metal wiring layer on the surface of the first metal wiring layer. An input pad formed on the second metal wiring layer, and an input pad formed on the first metal wiring layer below the input pad. A metal wiring region formed in accordance with a pad; a resistance element formed between the metal wiring region formed in the first metal wiring layer and the input pad formed in the second metal wiring layer; An input protection circuit having: A first metal wiring layer formed at least on the surface of the semiconductor substrate so as to be electrically separated from the semiconductor substrate; and a first metal wiring layer electrically separated from the first metal wiring layer on the surface of the first metal wiring layer. An input pad formed on the second metal wiring layer, and an input pad formed on the first metal wiring layer below the input pad. A metal wiring region formed in accordance with a pad; a resistance element formed between the metal wiring region formed in the first metal wiring layer and the input pad formed in the second metal wiring layer; And an input buffer having an input terminal connected to the metal wiring region. 3. The input protection circuit according to claim 2, wherein said metal wiring region formed in said first metal wiring layer has substantially the same size as said input pad. 4. The input protection circuit according to claim 2, wherein said metal wiring region formed in said first metal wiring layer is formed larger in size than said input pad. 5. The input protection circuit according to claim 2, wherein said resistance element is formed in a polysilicon layer formed between said first metal wiring layer and said substrate. 6. An anode is connected to the metal wiring region,
3. The input protection circuit according to claim 2, comprising: a first diode having a cathode connected to a power supply voltage; and a second diode having an anode connected to a common potential and a cathode connected to the metal wiring region. 7. The first diode comprises a first conductivity type insulated gate field effect transistor having a gate electrode and a source diffusion layer connected to the power supply voltage, and a drain connected to the metal wiring region. The second diode comprises a second conductivity type insulated gate field effect transistor having a gate electrode and a source diffusion layer connected to the common potential, and a drain connected to the metal wiring region. 6. The input protection circuit according to 6. 8. The first metal wiring layer includes a metal wiring formed between the metal wiring region and an input terminal of the input buffer, an anode connected to the metal wiring, and a cathode connected to a power supply voltage. 3. The input protection circuit according to claim 2, further comprising: a first diode connected to the first wiring, and a second diode having an anode connected to the common potential and a cathode connected to the metal wiring. 9. The first diode comprises a first conductivity type insulated gate field effect transistor having a gate electrode and a source diffusion layer connected to the power supply voltage, and a drain connected to the metal wiring. 9. The second diode according to claim 8, wherein a gate electrode and a source diffusion layer are connected to the common potential, and a drain is a second conductivity type insulated gate field effect transistor connected to the metal wiring. Input protection circuit. 10. The input buffer, wherein a gate electrode is connected to the metal wiring region and a source diffusion layer is connected to a power supply voltage; a first conductivity type insulated gate field effect transistor; A second conductive type insulated gate field effect transistor connected to a region, a source diffusion layer connected to a common potential, and a drain connected to an input terminal of an internal circuit together with a drain of the first conductive type insulated gate field effect transistor. 3. The input protection circuit according to claim 2, further comprising a transistor. 11. In the first metal wiring layer, a metal wiring formed between the metal wiring region and an input terminal of the input buffer, wherein the input buffer has a gate electrode connected to the metal wiring. A first conductivity type insulated gate field effect transistor having a source diffusion layer connected to a power supply voltage; a gate electrode connected to the metal wiring; a source diffusion layer connected to a common potential; 3. The input protection circuit according to claim 2, further comprising a second conductivity type insulated gate field effect transistor connected to an input terminal of the internal circuit together with a drain of the conductivity type insulated gate field effect transistor.