JPH11225064A - Frequency division circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency division circuit having a frequency division ratio of an optional fraction. SOLUTION: A counter section 10 is operated, based on a control signal CS1 when a count CNT3 of a counter section 40 is 0-2, and applies 1/5 frequency division to an input signal IN to output a frequency division signal S1. A counter 41 counts up with the frequency division signal S1 given via an OR 30 and when the count CNT3 reaches 3 or 4, the counter section 10 is stopped, a counter section 20 is operated instead to apply 1/6 frequency division to the input signal IN and to output a frequency division signal S2. The frequency division signals S1, S2 are outputted via an OR 30 as an output signal OUT. A desired frequency division ratio (P+Q)/(M×P+N×Q) is obtained by selecting frequency division ratios 1/M, 1/N of the counter sections 10, 20 and output periods P, Q of control signals CS1, CS2 of the counter section 40, where, N are integers being 2 or over and P, Q are integers being 1 or over.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency dividing circuit capable of dividing a frequency of an original oscillation frequency to generate a clock signal by setting the frequency dividing ratio to an arbitrary fraction.

[0002]

2. Description of the Related Art A frequency dividing circuit is a circuit that generates an output signal having a frequency that is a divisor of the frequency of an input signal. Conventionally, such a frequency dividing circuit uses, for example, a counter composed of flip-flops cascade-connected in multiple stages, counts the pulses of the input signal by the counter, and when the counted number reaches a predetermined divisor. Then, by resetting the counter to 0 and starting counting again, an output signal having a desired frequency is obtained.

[0003]

However, in the conventional frequency dividing circuit, since the count number is an integer, a predetermined divisor is also an integer, and the frequency dividing ratio is limited to an integer. However, in an apparatus that actually uses a frequency dividing circuit, various frequencies are required for the operation of each unit in the apparatus, and the ratio between the reference oscillation frequency and the desired frequency often does not become an integer ratio. . For this reason, it is necessary to provide an oscillator for obtaining a desired frequency separately from the reference oscillator, and there has been a problem that the circuit scale is increased and the cost is increased. Further, in such a case, since the output signals of the two oscillators are independent from each other, there has been a problem that a malfunction occurs due to an out-of-phase state of the two output signals. The present invention solves the problem of the prior art and provides a frequency dividing circuit capable of generating a frequency having an arbitrary fractional frequency dividing ratio from an original oscillation frequency.

[0004]

According to a first aspect of the present invention, there is provided a frequency dividing circuit, comprising: a first control circuit for controlling a first control signal of a complementary first and second control signals; First dividing means for dividing an input signal having a constant frequency into 1 / M (where M is an integer of 2 or more) and outputting a first divided signal when a signal is given; , When the second control signal is supplied, the input signal is divided by 1 / N (where N is an integer of 2 or more) to output a second frequency-divided signal. Means for synthesizing the first and second frequency-divided signals to generate an output signal; and dividing the output signal into (P + Q) base (where P and Q are 1
The first control signal is output when the count value is 0 to (P-1), and when the count value is P to (P + Q-1), the second control signal is output. And counting means for outputting

In the second invention, the integers M and N in the first invention are set so as to have a relationship of N = M + 1. According to the present invention, since the frequency dividing circuit is configured as described above, the following operation is performed. When the first control signal is supplied from the counting means, the input signal is frequency-divided into 1 / M by the first frequency dividing means and supplied to the counting means as a first frequency divided signal. When P first frequency-divided signals are supplied to the counting means, the first frequency-dividing means is stopped and
A second control signal for bringing the frequency dividing means into an operating state is as follows:
It is output from this counting means. As a result, the input signal is frequency-divided into 1 / N by the second frequency dividing means, and supplied to the counting means as a second frequency-divided signal. When Q second frequency-divided signals are supplied to the counting means, the first control signal for stopping the second frequency-dividing means and bringing the first frequency-dividing means into the operating state again is transmitted to the counting means. Output from By such repetition, (P + Q) pulses are output from the synthesizing unit as output signals for each pulse number (M × P + N × Q) of the input signal.

[0006]

FIG. 1 is a block diagram of a frequency dividing circuit showing an embodiment of the present invention. This dividing circuit has a dividing ratio of 5 /
27 is an example of a frequency dividing circuit having an input signal IN having a constant frequency to be divided by 1 / M (for example,
A first frequency dividing means (for example, a counting unit) 10 for dividing the frequency by M = 5 is provided. The counting unit 10 receives the input signal I
It has a two-input AND gate (hereinafter, referred to as "AND") 11 to which N and a control signal CS1 are applied. The output side of the AND 11 is connected to the clock terminal C of a three-digit binary counter 12. I have. The counter 12 detects the falling edge of the signal supplied to the clock terminal C,
The count value CNT1 is incremented by one, and the output terminals Q1,
A binary number is output to Q2 and Q3, and the count value CNT is output when a reset signal is applied to the reset terminal R.
It has a function of resetting 1 to 0. Counter 12
Are connected to the input side of a two-input AND 13, and the output side of the AND 13 is connected to the binary counter 1.
2 reset terminal R.

[0007] This frequency dividing circuit similarly changes the input signal IN to 1
/ N (for example, n = 6) is provided with a second frequency dividing means (for example, a counting unit) 20. Counting section 20
Has a two-input AND 21 to which an input signal IN and a control signal CS 2 are supplied. The output of the AND 21 is connected to a clock terminal C of a three-digit binary counter 22 having the same function as the counter 12. Have been. Output terminals Q1 and Q for outputting the count value CNT2 of the counter 22
2 and Q3, the output terminals Q2 and Q3 are AND2 of two inputs.
The output of the AND 23 is connected to the reset terminal R of the counter 22. First frequency-divided signal S1 output from output terminal Q3 of counter 12
And the second frequency-divided signal S2 output from the output terminal Q3 of the counter 22 are provided to the input side of a synthesizing means (for example, a two-input OR gate, hereinafter referred to as “OR”) 30. . The output signal OUT is output to the output side of the OR 30.
Is output. The output signal OUT is further (P + Q)
(For example, P = 3, Q = 2) is provided to a clock terminal C of a 3-digit binary counter 41 in a counting means (for example, a counting unit) 40 for counting in a binary system. The counter 41 has the same function as the counter 12, and the output terminals Q1, Q2, Q3
Are connected to the input terminals A, B, and C of the decoder 42. The decoder 42 decodes the binary numbers given to the input terminals A, B, and C, and outputs the level "1" to one of the output terminals Y0, Y1,..., Y5 provided corresponding to the binary numbers. It outputs a signal of level "L" to "H" and other terminals. The output terminal Y5 of the decoder 42 is connected to the reset terminal R of the counter 41. The P (that is, three) output terminals Y0 to Y2 of the decoder 42 are 3
The control signal CS1 is connected to the input side of the input OR43, and the control signal CS1 is supplied to the AND11 from the output side of the OR33. Further, Q decoders 42 (that is, Q decoders)
The (two) output terminals Y3 and Y4 are connected to the input side of a two-input OR 44, and the control signal CS2 is supplied to the AND 21 from the output side of the OR 44.

FIG. 2 is a time chart showing the operation of the frequency dividing circuit of FIG. Hereinafter, referring to FIG. 2, FIG.
Will be described. Input signal I at time t0 in FIG.
It is assumed that the counter 41 in the counting unit 40 is reset by the falling of N, and the count value CNT3 becomes 0. At this time, it is assumed that the count values CNT1 and CNT2 of the counters 12 and 22 are also 0. When the count value CNT3 becomes 0, the signal output from the output terminal Y0 of the decoder 42 becomes "H", and the control signals CS1 and CS2 become "H" and "L", respectively. Thus, the operation of the counter 12 of the counting section 10 is started. On the other hand, the operation of the counter 22 of the counting section 20 is stopped.

The count value CNT1 of the counter 12 becomes 1 due to the fall of the input signal IN at time t1. Thereafter, each time the input signal IN falls, the counter 1
The count value CNT1 of 2 is incremented by one. When the count value CNT1 of the counter 12 becomes 4 due to the fall of the input signal IN at time t4,
The frequency-divided signal S1 output from the output terminal Q3 of the counter 12 becomes "H". As a result, the output signal OUT output from the OR 30 also changes to “H”. When the input signal IN falls at time t5, the counter 12
When the count value CNT1 of the counter becomes 5, this counter 12
, Both output from the output terminals Q1 and Q3 attain "H". As a result, the reset signal is supplied from the AND 13 to the reset terminal R of the counter 12, and the counter 12 is reset at the moment when the count value CNT1 becomes 5, and the count value CNT1 returns to 0. At the same time, the frequency-divided signal S1 and the output signal OUT also change to “L”.

When the output signal OUT falls, the count value CNT3 of the counter 41 counts up to one. As a result, the output signal of the output terminal Y1 becomes "H" instead of the output terminal Y0 of the decoder 42, but the control signals CS1 and CS2 do not change. Therefore, the next time t6
The operation at the falling point of the input signal IN at t9 is the same as that at the times t1 to t4. When the count value CNT1 of the counter 12 becomes 4 due to the fall of the input signal IN at time t9, the frequency-divided signal S1 output from the output terminal Q3 of the counter 12 and the output signal OUT output from the OR 30 are both " H ”.

When the input signal IN falls at time t10, the count value CNT1 of the counter 12 is reset to 0, and at the same time, the frequency-divided signal S1 and the output signal OUT also change to "L". By the falling of the output signal OUT, the count value CNT3 of the counter 41 is counted up to 2. As a result, the output signal of the output terminal Y2 becomes "H" instead of the output terminal Y1 of the decoder 42, but the control signals CS1 and CS2 do not change. Therefore,
The operation at the fall of the input signal IN at the following times t11 to t14 is the same as that at the times t6 to t9.
Due to the fall of the input signal IN at time t14,
When the count value CNT1 of the counter 12 becomes 4, the frequency-divided signal S output from the output terminal Q3 of the counter 12
1 and the output signal OUT output from the OR 30 both change to "H".

When the input signal IN falls at time t15, the count value CNT1 of the counter 12 is reset to 0, and at the same time, the frequency-divided signal S1 and the output signal OUT also change to "L". By the falling of the output signal OUT, the count value CNT3 of the counter 41 is counted up to 3. As a result, the output signal of the output terminal Y3 becomes "H" instead of the output terminal Y2 of the decoder 42, and the control signals CS1 and CS2 become "L" and "L", respectively.
Invert to “H”. When the control signal CS1 becomes "L",
The counter 12 of the counting unit 10 counts CNT1 =
The operation stops at 0. On the other hand, since the control signal CS2 becomes “H”, the counter 22 of the counting section 20 starts operating instead of the counter 12. The falling of the input signal IN at time t16 causes the counter 22
Count value CNT2 becomes 1. Thereafter, the input signal IN
Count value CNT2 of the counter 22 at each fall of
Counts up one by one.

When the count value CNT2 of the counter 22 becomes 4 due to the fall of the input signal IN at time t19, the frequency-divided signal S2 output from the output terminal Q3 of the counter 22 becomes "H". Thereby, OR30
Also changes to "H". When the count value CNT2 of the counter 22 becomes 6 due to the fall of the input signal IN at time t21, the signals output from the output terminals Q2 and Q3 of the counter 22 both become "H". As a result, a reset signal is provided from the AND 23 to the reset terminal R of the counter 22,
The counter 22 is reset at the moment when the count value CNT2 becomes 6, and the count value CNT2 returns to 0. At the same time, the frequency-divided signal S2 and the output signal OUT also become “L”.
Changes to

The falling edge of the output signal OUT causes the count value CNT3 of the counter 41 to count up to 4. As a result, the output signal of the output terminal Y4 becomes "H" instead of the output terminal Y3 of the decoder 42, but the control signals CS1 and CS2 do not change. Therefore, at the next time t22
The operation at the falling point of the input signal IN from to t25 is the same as the operation from the time t16 to t25. Time t2
When the count value CNT2 of the counter 22 becomes 4 due to the fall of the input signal IN at 5, the frequency-divided signal S2 output from the output terminal Q3 of the counter 22 becomes "H". As a result, the output signal OUT output from the OR 30 also changes to “H”.

When the input signal IN falls at time t27, the counter 22 is reset, and the count value CNT2 returns to zero. At the same time, the frequency-divided signal S2 and the output signal OUT also change to “L”. By the falling of the output signal OUT, the count value CNT3 of the counter 41 is counted up to 5. As a result, the output signal of the output terminal Y5 becomes "H" in place of the output terminal Y4 of the decoder 42, the counter 41 is reset, the count value CNT3 becomes 0, and returns to the same state as the state at the time t0. The number of pulses of the output signal OUT between the times t0 and t27 is five.

As described above, the frequency dividing circuit according to the present embodiment
The frequency division operation for the input signal IN is performed with time t0 to t27 as one cycle, and during this cycle, the output signal OUT
As a result, five pulses are generated. That is, there is an advantage that frequency division can be performed with an arbitrary fraction (for example, 5/27) as the frequency division ratio.

Further, since the frequency division numbers M and N in the counting units 10 and 20 are set to continuous integers as 5 and 6, there is an advantage that an output signal OUT with small phase jitter can be obtained. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (e). (A) FIG. 1 shows a frequency dividing circuit having a frequency dividing ratio of 5/27 in order to more specifically explain the configuration and operation of the frequency dividing circuit, but the frequency dividing ratio may be an arbitrary fraction. Can be. In that case, the values of the constants M, N, P, and Q of the counters 12, 22, and 42 for a desired frequency division ratio (for example, 5/27) are as follows:
What is necessary is just to calculate as follows. First, the desired division ratio 5
Take the reciprocal of / 27 to get 27/5 = 5.4. next,
From the integers before and after the obtained numerical value 5.4, M = 5 and N = 6 are determined. Furthermore, the values of P and Q are obtained by substituting M = 5 and N = 6 into the following simultaneous equations. M × P + N × Q = 27 P + Q = 5 As a result, P = 3 and Q = 2 are calculated.

(B) The configuration of the counting units 10, 20, and 40 is not limited to the configuration shown in FIG. 1, and any configuration may be used. (C) In the counting units 10 and 20, the signals of the output terminal Q3 of the most significant digit of the counters 12 and 22 are output as frequency-divided signals S1 and S2, for example, by adding a gate circuit such as an OR. The frequency-divided signals S1 and S2 having a duty ratio of approximately 50% may be output. Thereby, the output signal O having a duty ratio of approximately 50% is output.
It is possible to obtain a UT. (D) In the counting section 40, of the output terminals Y0 to Y4 of the decoder 42, three consecutive output terminals Y0 to Y2
Is connected to OR43, and two continuous output terminals Y3, Y
4 is connected to the OR 44, but the output terminals Y0, Y2, and Y4 may be connected to the OR 43, and the output terminals Y1 and Y3 may be connected to the OR 44, for example. This allows
The phase shift of the output signal OUT can be averaged. (E) Dividing numbers M and N in counting sections 10 and 20
Is set to be a continuous integer such as 5 or 6, but may be set to an arbitrary integer in a frequency dividing circuit that does not emphasize phase jitter. Any integer M, N (eg,
4, 8, 16, etc.), the configuration of the counting units 10, 20 can be simplified in some cases.

[0019]

As described above in detail, according to the first aspect, while the first control signal is being given, the input signal is divided by 1 / M to obtain the first divided signal. While the first frequency dividing means outputting as
A second frequency divider for dividing the input signal by 1 / N and outputting it as a second frequency-divided signal; counting P first frequency-divided signals; and counting Q second frequency-divided signals A counting means for switching and outputting the first and second control signals every time. This allows the input signal to be converted to an arbitrary fraction (P +
Q) / (M × P + N × Q). According to the second invention, the frequency dividing number M of the first frequency dividing means
And the dividing number of the second dividing means N are set to be continuous integers. Thereby, an output signal with small phase jitter can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a frequency dividing circuit according to an embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the frequency dividing circuit of FIG. 1;

[Explanation of symbols]

 10, 20, 40 counting section 11, 13, 21, 23 AND 12, 22, 41 counter 30, 43, 44 OR 42 decoder

Claims (2)

[Claims] When a first control signal of the complementary first and second control signals is given, an input signal having a constant frequency is 1 / M (where M is 2 or more). First dividing means for dividing the input signal by an integer and outputting a first divided signal; and when the second control signal is given, the input signal is divided by 1 / N (where N is 2 Divided by the above integer)
A second frequency dividing means for outputting a frequency-divided signal of the following; a synthesizing means for generating an output signal by synthesizing the first and second frequency-divided signals; , P, and Q are integers of 1 or more), and the count value is 0 to (P−
Counting means for outputting the first control signal when 1) and outputting the second control signal when the count value is P to (P + Q-1). circuit. 2. The frequency dividing circuit according to claim 1, wherein the integers M and N have a relation of N = M + 1.