JPS5883435A - Pulse swallow frequency dividing circuit - Google Patents

Abstract

PURPOSE:To mitigate the restriction in the design of a frequency synthesizer, by controlling the frequency dividing ratio of the 1st counter with the information of the 2nd and 3rd counters and obtaining an arbitrary integer number of frequency dividing ratio. CONSTITUTION:A prestage variable frequency divider 9 is the 1st counter which performs frequency division of a pair of frequency dividing ratios P and P-0.5 in response to the logical level ''1'' or ''0'' of a control signal 200 to an input signal 100, a programmable counter 2 is the 2nd counter which performs frequency division in the frequency dividing ratio of a positive integer B in cascade connection with the 1st counter, and a programmable counter 3 is the 3rd counter which is cascade-connected to the 1st counter and can count a positive integer A equal to or smaller than the B. When the counter counts B-set of outputs of the frequency divider 9, an output pulse is generated, the couners 2, 3 are reset, the next count is started, the signal 200 is changed from ''1'' to ''0'' and the frequency divider 9 is controlled for the frequency division by the frequency dividing ratio (P-0.5).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency dividing circuit, particularly a frequency dividing circuit that can directly divide high-frequency signals at any half-integer (a positive integer divided by 2 and 9 numbers is called a half-integer) division ratio. -Relating to frequency dividing circuits.

Conventionally, as a divider that can divide a high frequency signal with an arbitrary integer division ratio, 1. Pulse swallow frequency divider circuits are known. FIG. 1 shows a basic diagram of this frequency divider.

The variable front divider l is a divider that divides the input signal 100 from the input terminal by a division ratio of either P or P+1 corresponding to the logic level 111 or 101 of the control signal 200, respectively. be. This output is applied to a programmer pull counter 2 which performs a frequency division operation using a frequency division ratio B and a programmer pull counter 3 which counts integers. The output of counter 3 is used as a control signal 200,
The output becomes the output of this frequency dividing circuit and is used to reset the counter 2 itself and the counter 3. However, P, A and B are positive integers, and H: 4A
It is.

Initially, assume that the control signal 200 is l□l. counter 3
is a 0 counter that stops when it counts A number of (P+1) branch signals of input signal 100, inverts control signal 200t from "O" to @11, and switches the frequency division ratio of splitter 1 from ()'+1) to P. 2 counts A number of (P+1) division signals, and then counts the P frequency division signals, and when the total number reaches B, outputs an output pulse and returns the circuit to the initial state. As a result, the input signal to =()'+1)A+)'(HA-A), PH+A ・
...(1) It becomes a frequency divider circuit that counts and outputs one output. Here, when A and Bt are variable, in order for the overall division ratio given above to be a continuous integer, A:Q, P-1, H: 4P-1 can be set, and this lower limit Theory 11 for frequency division ratio is Aeal+a=OJ ■I Otori=P-1 to Na+1a = PHa+1m +Aw1m ==P
(P-1) ...”(jl). From the above explanation,
When using a pulse swallow frequency divider circuit, )'(P-1)
It can be seen that the above continuous integer division ratios can be obtained.

The pulse swallow frequency divider circuit described above is often used in a frequency synthesizer as a programmable counter in a PLL circuit. Figure 2 is a block diagram showing the basic configuration of a frequency synthesizer. ) 8 frequency programmable counter 4
', and compare the phase with the output of a reference frequency generator 5 with high frequency stability using a phase comparator 6 to detect an error output signal, which is then fed back to the VCO 8 via a low-pass filter 7. A PLL circuit is formed to control the frequency.

In such a frequency section synthesizer, the output frequency is
) When changing the frequency in steps of ), according to the conventional pulse swallow frequency divider circuit, the division ratio is limited to 1/integer, so the reference frequency fr is f.

= ΔF, and when the step of Δ) is small, it is not possible to select a reference frequency higher than 1 times, and there is a certain restriction in design. If the reference frequency can now be selected to be twice the frequency and set f w = 2j'', these constraints will be greatly eased, and the following effects will be achieved in terms of design. Namely, (
+) Since the division ratio is approximately halved, the loop gain of the PLL circuit can easily be approximately doubled9, and phase noise can be suppressed to a low level. (
(2) Since the reference frequency is doubled, leakage of the reference signal component from the low-pass filter is reduced, and therefore spurious noise due to residual modulation can be reduced. Alternatively, the design of the low-pass filter can be simplified. (-) Frequency step ΔF
Since the loop band can be widened when the frequency is extremely low, the L-response characteristics can be improved in combination with an increase in the loop gain. It is an object of the present invention to provide a branching circuit that can obtain the above-mentioned effects, that is, a pulse thrower frequency divider circuit that can obtain any continuous half-integer frequency division ratio. is a first circuit that performs a division operation by selecting one of a pair of frequency division ratios P (P is a positive integer) and P-0, 5 or P and P+0.5 by a control signal. '', a second counter that is cascade-connected to the first counter and performs frequency dividing operation at a division ratio of B (B is a positive integer), and a second counter that is cascade-connected to the first counter and performs frequency division operation at a division ratio of B; a positive integer At equal to or less than B; and a third counter capable of counting a positive integer At equal to or less than
The division of the first counter is performed by counting the A number of frequency division outputs based on one of the division ratios and counting the remaining HA division outputs based on the other division ratio to perform the frequency division operation. It is constructed by controlling the ratio using the information of the second and third counters.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram of an embodiment of the present invention, in which 9 is a variable pre-frequency divider, 2 and 3 are block 2 maple counters, and 100
is an input signal, and 200 is a control signal. The front variable branching unit 9 converts the human input signal 100 from the input terminal into a control signal 200.
A pair of division ratios P and i'-0, 5 are selected in correspondence with the logic level 01@ or lo@rc, and the programmable counter 2 is the first counter that performs the division operation.
A programmable counter 3 is connected in cascade to the first counter and performs a division operation with a division ratio of a positive integer B, and a programmable counter 3 is cascaded to the first counter and can count a positive integer equal to or less than B. 3 counter. The programmable counter 2 receives the output t-8 of the prevariable frequency divider 9.
When counting, an output pulse is generated, which resets the boogramma pull counters 2 and 3 to start the next count, and changes the control signal 200t"11 to I□I, causing the variable prefrequency divider 9 to divide the stations. Control to perform frequency division operation by ratio (P-0, 5).Programmable counter 3
When A number of pulses are counted, the control signal zoot is changed from "o" to "l" and the prefix variable divider 9 is controlled to perform the frequency division operation with the frequency division ratio P.0 As is clear from the above explanation, , according to the circuit of this embodiment, the programmable counter 2 ti destination f (P-0,5
) is divided into A number of stitches, and then the divided output according to the frequency division ratio of P is counted and the remaining (H-A) are counted to perform the division operation.N7=(1'- 0,5) A+)' (B-A)
=PB-0,5A...Pulse frequency divided by (8)
A swallow frequency divider circuit is obtained.

However, it is B\A. When A and B are changed with this (8)
The condition for the division ratio given by the formula to be any continuous half-integer is A = 0 to 2)'-1. HΣ2()'-1) (however, H
= 2(P-1), A=θ~2(i'-1)), and the lower limit division ratio is Hmia :2()'-1), A
way = 2 ()'-1) to NTm1m = PBmim-0,5Amax = (
P-1)(2P-1)...(4) This results in a continuous nine-half integer splitting ratio of CP-1)(2)'-1) or more.

FIG. 4 is a block diagram showing an embodiment of the variable pre-distributor used in the present invention, in which 10 is an exclusive*summing circuit, 11.12
and 13 is a Ta1l flip 7a block circuit which operates at the rising edge of the input signal, and 14 is a simple sum circuit which divides the input signal 100 at a frequency division ratio of 3.5 when the control signal 200 is 1()1.
This is a prefix variable divider V with P=4 which divides the frequency at a dividing ratio of 4 when the control signal 200 is 11''.

FIG. 5 is a time chart explaining the operation of FIG.
) 11 input TI, FFI 1 output Ql s
The signal waveforms of the output q (branch output) of FF 12, the complementary output Q3 of PF'12, the control signal 200, the input Ts of F'F13, and d of k'F13 are shown. The waveform shown by the solid line from T to Q in the figure is 3.5
Count an even number of 1/1 frequency divided pulses and control signal 2 at the 9th point.
The broken line shows the waveform when 00 is changed from I□l to III, and the broken line shows the waveform when the number is odd. In either case, the output signal Q for the I□l or 嬬@1@ of the % control signal 200
It can be seen that the snow is divided into 3.5 or 1/4 of the input signal. The waveform in the figure is displayed ignoring the time delay between the input and output of
The output Qs actually has a time delay of about Δt'' from the figure, and the output of the exclusive OR circuit lO has a waveform as shown at T in the figure.0 Also, the control signal 200 is a frequency-divided output. Q
, but they do not necessarily need to be switched at the same time. That is, even if the time point at which the switching signal 200 switches is later than the illustrated t@@'Is "Re F by a time less than nine, the same operation is performed without any change in other waveforms. The time chart in FIG. 5 shows a case where the D-T ratio of the input signal 100 is 50%, but if it deviates from 50%, the interval between the outputs of Q will deviate slightly from the state shown. DA ratio is 5
When the dipulse width smaller than 0% becomes shorter by ΔT, in the case of a solid line, starting from time - 3.5To - ΔT, 3.5T
, +ΔT, 4T, , -... 3.5 for broken line
To−ΔT*4Toe3. sT, +ΔT, e++, and f, 3.5T, alternately changes by ±ΔT, so if the overall division ratio Nte has a fraction of 0.5, the interval between the divided outputs will also be N T T, However, this slight phase modulation due to the A frequency can be easily removed with a filter, etc., and does not cause any essential problems as a branching device. Although one embodiment of the present invention has been described, the variable pre-distributor used in the present invention is not limited to the circuit shown in FIG.
It can be configured with other circuits, such as a circuit including a T-type flip-flop that operates at the falling edge of a human input signal, and can be realized not only with an asynchronous ripple counter circuit but also with a synchronous counter circuit. In the explanation of the embodiment shown in FIG.
and (P-o, s) are the control signals 200C)"
9, which corresponds to 1@ and 10'', may conversely correspond to 10I and 111 of the control signals.Furthermore, even if the division ratio is P and ()'+0.5), the same effect can be obtained. The control signal is not limited to a binary signal of logic levels I□l and 11'', but may also be a pulse signal issued at the switching point. In this embodiment, all the control signals 200 are supplied from the color/receiver 3, but the control signal for switching the frequency division ratio at the same time as resetting the counters 2 and 3 is supplied via the counter 3. It is also possible to configure it so that it is supplied from the contact counter 2 without having to do so. Furthermore, out of a total of B pulses counted by the power counter 2, it is configured to first count A (P-0, 5) branch pulses, but the timing of counting A pulses is It is clear that the same effect can be obtained not only at any position but also at any position. Therefore, if this is applied to a PLL circuit such as a frequency synthesizer, the reference frequency can be selected to be twice the frequency step, and various conventional design constraints are relaxed, and a device with good performance can be easily obtained.

[Brief explanation of drawings]

FIG. 1 is a basic block diagram of a conventional pulse swallow frequency divider circuit, FIG. 2 is a block diagram showing the basic configuration of a frequency synthesizer, and FIG. 3 is a block diagram of an embodiment of the present invention.
FIG. 4 is a block diagram of one embodiment of the variable pre-distributor used in the present invention, and FIG. 5 is a time chart illustrating the operation of the circuit shown in FIG. 4. 1...Conventional front variable splitter, 2.3 and 4.
...Progera! Pull counter, 5... Reference frequency generator, 6... Phase comparator, 7...
...Low-pass filter, 8...Voltage controlled oscillator (V
CO), 9 and G... Front variable splitter, 10
・Old... Exclusive 1-fill sum circuit, 11.12 and 13...
...T-type 7-lip 7-oy loop circuit, 14...
1mJ! Sum circuit, 100...Input signal, 200
······Control signal. 1st Kuni Hayabusa 2 Ferocious 3 Ward 4 Ward 5 Figure-2 (

Claims (1)

[Claims] A pair of frequency division ratios P (P is a positive integer) and P- are determined by the control signal.
o, 5 (fL<ri, P and)'+0.5) (7) 0
The first branching ratio is selected and the branching operation is performed.
and the counter of H
(B is a positive integer a); and a second counter that is cascade-connected to the first counter and can count a positive integer equal to or smaller than the division ratio B. a third counter, wherein the second counter is the first counter.
The frequency dividing output according to one of the preselected frequency division ratios of the counter is counted by the A number, and the frequency division output according to the other division ratio is counted by IA90B-A to perform the division operation. A pulse swallow frequency divider circuit characterized in that the frequency division ratio of the first counter is controlled by the information of the second and third counters.