JPH11265580A - Semiconductor storage device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor memory device in which a memory cycle time is shortened by a simple configuration and a memory operation is realized by a clock signal at a high frequency. SOLUTION: A memory array having a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of complementary bit lines, and a memory array selected from a plurality of the complementary bit lines by a selection signal are commonly inputted. In a semiconductor memory device provided with a column switch connected to an output line and a precharge circuit for setting the common complementary input / output line to a predetermined same potential, the readout period of the column switch is increased during reading and the common The precharge period of the complementary input / output line is shortened, the selection period of the column switch is shortened at the time of writing, and the precharge period of the common complementary input / output line is increased correspondingly, thereby shortening the memory cycle period at the time of reading and writing. Make them almost the same.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a technology effective when used in a column selecting circuit in a synchronous DRAM (dynamic random access memory) operating at high speed.

[0002]

2. Description of the Related Art A dynamic RAM having a large storage capacity such as 64 Mbits or 256 Mbits is disclosed in "Nikkei Electronics" No. 641, pp. 99-214, published on July 31, 1995 by Nikkei McGraw-Hill. is there.

[0003]

SUMMARY OF THE INVENTION Dynamic RAM
, There is a high-speed operation mode in which writing and reading are performed by switching a column address while a word line is selected. In the synchronous DRAM, there is a burst mode in which a column address is generated internally in response to a clock signal supplied from an external terminal to continuously switch the column address.
In such a continuous operation mode, the write operation and the read operation are performed by switching the column address. However, when switching the address, the previous cycle information is reset in the common input / output line for high-speed operation. Is provided.

Conventionally, no special consideration is given to a write operation and a precharge operation performed thereafter, and a read operation and a precharge operation performed thereafter, and both are performed at the same time ratio. , So as to satisfy each operation time. If the clock cycle time is relatively long, for example, 10 ns or more, there is sufficient time, so that there is no problem even with the above. However, if the clock frequency is 100 MHz
In order to increase the speed to about 160 MHz beyond the above, the burst mode requires a cycle time of only 6 ns. Considering the increase in the parasitic capacitance of the wiring accompanying the increase in storage capacity and the miniaturization of the element, the above cycle is considered. It is not easy to switch the column address in time. In the present inventor, the time required for each of the above operations and the signal amplitude appearing on the common input / output line greatly differ between the time of writing and the time of reading, and the time required for precharging also corresponds to the signal amplitude. Focusing on the difference, we considered shortening the clock cycle time by optimizing the column selection period and the precharge period for the write operation and the read operation, respectively.

An object of the present invention is to provide a semiconductor memory device having a simple structure and a reduced clock cycle time. Another object of the present invention is to provide a semiconductor memory device that realizes a memory operation using a high-frequency clock signal. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a memory array in which a plurality of memory cells are provided at the intersections of a plurality of word lines and a plurality of complementary bit lines, and a memory array selected from the plurality of complementary bit lines by a selection signal are used as common complementary input / output lines. And a precharge circuit for setting the common complementary input / output line to a predetermined same potential. In a semiconductor memory device, when reading, a column switch selection period is lengthened and the common complementary input / output line is correspondingly extended. The precharge period of the output line is shortened, the selection period of the column switch is shortened at the time of writing, and the precharge period of the common complementary input / output line is lengthened accordingly, so that the memory cycle period at the time of reading and writing is almost the same. To

[0007]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied. In the figure, the main part of each circuit block constituting the dynamic RAM to which the present invention is applied is shown so that it can be understood. Are formed on one semiconductor substrate.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole. A power supply circuit including an input / output interface circuit composed of an address input circuit, a data input / output circuit, a bonding pad array, a step-down circuit, and the like are provided in a central portion 14 in the longitudinal direction of the semiconductor chip. Column decoder regions 13 are arranged in portions of both sides of the central portion 14 in contact with the memory array.

As described above, in each of the four memory arrays divided into two on the left and right and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, the main row decoder is disposed at the upper and lower central parts in the longitudinal direction. An area 11 is provided. Main word driver regions 12 are formed above and below the main row decoder, and drive the main word lines of the vertically divided memory array.

The above-mentioned memory cell array (sub-array) 15
Are formed so as to be surrounded by the sense amplifier region 16 and the sub-word driver region 17 with the memory cell array 15 interposed therebetween, as shown in the enlarged view. An intersection between the sense amplifier area and the sub-word driver area is an intersection area (cross area) 18. The sense amplifiers provided in the sense amplifier region 16 are configured by a shared sense method, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right around the sense amplifier. Selectively connected to the complementary bit lines of the memory cell array.

As described above, the memory arrays divided into four on the left and right sides in the longitudinal direction of the semiconductor chip are arranged in groups of two. In the two memory arrays thus arranged in pairs, the main row decoder region 11 and the main word driver 12 are arranged in the center. The main word driver 12 generates a selection signal of a main word line extended so as to penetrate the one memory array. The main word driver 12 is also provided with a driver for selecting a sub-word, and extends in parallel with the main word line to form a sub-word selection line signal, as described later.

Although not shown, one memory cell array (sub-array) 15 shown as an enlarged view has 256 sub-word lines and 256 pairs of complementary bit lines (or data lines) orthogonal thereto. In the one memory array, 16 memory cell arrays (sub-arrays) 15 are provided in the bit line direction. Therefore, about 4K sub-word lines are provided as a whole, and 8 sub-word lines are provided in the word line direction. A total of about 2K lines are provided. Since eight such memory arrays are provided as a whole, the memory array has a total storage capacity of 8 × 2K × 4K = 64 Mbits.

The one memory array is divided into eight in the main word line direction. A sub-word driver (sub-word line driving circuit) 17 is provided for each of the divided memory cell arrays 15. The sub-word driver 17 is divided into の 長 of the length of the main word line, and forms a sub-word line selection signal extending in parallel with the length. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Are arranged four sub-word lines. In order to select one sub-word line from among the sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction, a sub-word selection driver is used. Be placed. This sub-word selection driver is extended in the arrangement direction of the sub-word drivers.
A selection signal for selecting one of the sub-word selection lines is formed.

Focusing on the one memory array, 1
One sub word line is selected from all eight memory cell arrays allocated to the main word lines. As described above, 2K (20
Since the memory cell of 48) is provided, 2048/8 = 256 memory cells are connected to one sub-word line.

As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. To
It is also divided into 16 in the complementary bit line direction. That is,
The complementary bit line is divided into 16 by the sense amplifier 16 indicated by a thick black line. Although not particularly limited, the sense amplifiers 16 are configured by a shared sense system, and are provided at both ends of the memory array.
Except for the above, complementary bit lines are provided on the left and right with respect to the sense amplifier 16, and are selectively connected to one of the left and right complementary bit lines.

FIG. 2 is a schematic layout diagram for explaining a dynamic RAM to which the present invention is applied. FIG. 1 shows a schematic layout of the entire memory chip and a layout of one memory array divided into eight. This figure illustrates the embodiment of FIG. 1 from another point of view. That is, similarly to FIG. 1, the memory chip is divided into four parts in the left-right direction and two parts up and down in the longitudinal direction (word line direction). A memory array (Array) is divided into eight parts, and a plurality of bonding pads and address buffers, a control circuit, a predecoder, a timing control circuit, and other indirect peripheral circuits (Bonding Pad & peripheral Circuit) are provided in the central part in the longitudinal direction. Is provided.

Each of the eight memory arrays has a storage capacity of about 8 Mbits.
As one of them is shown enlarged, a sub-array divided into eight in the word line direction and divided into sixteen in the bit line direction is provided. On both sides of the sub-array in the bit line direction, sense amplifiers (Sence Amplifiers) are arranged in the bit line direction. A sub-word driver (Sub-Word driver) is provided on both sides of the sub-array in the word line direction.
Driver) is placed.

The one array is provided with a total of 4096 word lines and 2048 pairs of complementary bit lines.
As a result, the storage capacity is about 8 Mbits in total. As described above, 4096 word lines are divided into 16 sub-arrays and arranged, so that one sub-array is provided with 256 word lines (sub-word lines). In addition, since 2048 pairs of complementary bit lines are divided into eight sub-arrays as described above, one sub-array is provided with 256 pairs of complementary bit lines.

At the center of the two arrays, a main row decoder, an array control circuit and a main word driver are provided. The array control circuit includes a driver for driving a first sub-word selection line. A main word line extending so as to penetrate the eight divided sub-arrays is arranged in the array. The main word driver drives the main word line. Like the main word line, the first sub-word select line is also connected to
It is extended so as to penetrate the divided sub-array. Above the array, a Y decoder (YDecoder) and a Y select line driver (YSdriver) are provided.

FIG. 3 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuits in a dynamic RAM according to the present invention. In FIG. 4, four sub-arrays SBARY arranged at hatched positions in the memory array shown in FIG. 2 are shown as representatives. In FIG. 3, a region where the sub-array SBARY is formed is shaded to distinguish a sub-word driver region, a sense amplifier region, and a cross area provided therearound.

The subarray SBARY is divided into the following four types. That is, when the extending direction of the word line is the horizontal direction, the first sub-array SBA
RY has 256 sub-word lines SWL and 256 complementary bit line pairs. Therefore, the above 2
The 256 sub-word drivers SWD corresponding to the 56 sub-word lines SWL are connected to the left and right of the sub-array by one.
It is divided into 28 pieces and arranged. The 256 sense amplifiers SA provided corresponding to the 256 pairs of complementary bit lines BL are arranged alternately in addition to the above-described shared sense amplifier system, and are divided into 128 pieces above and below the sub-array. Placed.

Second sub-array SBAR arranged at the upper right
Although Y is not particularly limited, the regular sub word line SWL
Is provided with eight spare (redundant) word lines in addition to 256, and the complementary bit line pairs are composed of 256 pairs. Therefore, the 264 sub-word drivers SWD corresponding to the above-mentioned 256 + 8 sub-word lines SWL are divided and arranged on the left and right of the sub-array in units of 132. As described above, 128 sense amplifiers are vertically arranged. That is, 128 pairs of complementary bit lines of the 256 pairs formed in the upper and lower sub-arrays SBARY arranged above and below the right side are commonly connected to the sense amplifier SA interposed therebetween via the shared switch MOSFET. .

A third sub-array SBAR arranged at the lower left
Y is composed of 256 sub-word lines SWL in the same manner as the right adjacent sub-array SBARY. 1 as above
28 sub-word drivers are divided and arranged. 256 of the subarray SBARY arranged on the lower left and right sides
The 128 sub-word lines SWL are commonly connected to the 128 sub-word drivers SWD formed in the region sandwiched between them. The subarray SBARY arranged at the lower left as described above is provided with four pairs of spare (redundant) bit lines 4RED in addition to 256 pairs of normal complementary bit lines BL. Therefore, the 260 sense amplifiers SA corresponding to the 260 pairs of complementary bit lines BL are divided and arranged in 130 units above and below the subarray.

Fourth subarray SBAR arranged at the upper left
Y has 256 regular sub-word lines SWL and eight spare sub-word lines as in the right adjacent sub-array SBARY. In addition to the 256 normal complementary bit line pairs as in the lower adjacent sub-array, the spare Are provided, and the sub-word drivers are divided into 132 units each on the left and right sides, and the sense amplifier SA is
Are divided and arranged.

The main word line MWL is extended in the horizontal direction as described above, one of which is exemplarily shown as a representative. The column selection line YS is extended in the vertical direction so that one of them is exemplified as a representative. A sub-word line SWL is arranged in parallel with the main word line MWL, and a complementary bit line BL (not shown) is arranged in parallel with the column selection line YS. In this embodiment, although not particularly limited, in the memory array of 8 Mbits as shown in FIG. 2, eight sub arrays are formed in the bit line direction with the above four sub arrays as one set of basic units. Four sets of subarrays are configured in the direction. Since one set of sub-arrays is composed of four,
In an M-bit memory array, 8 × 4 × 4 = 128 sub-arrays are provided. Since eight 8M-bit memory arrays are provided in the entire chip, 128 × 8 = 1024 subarrays are formed in the entire memory chip.

For the above four sub-arrays, 8
The sub-word select lines FX0B to FX7B are extended so as to penetrate four sets (eight) of sub-arrays, similarly to the main word line MWL. Then, the sub word select line FX
Four lines consisting of 0B to FX3B and four lines consisting of FX4B to FX7B are separately extended on the upper and lower sub-arrays. The reason why one set of sub-word selection lines FX0B to FX7B are allocated to the two sub-arrays and they are extended on the sub-arrays is to reduce the memory chip size.

That is, when the above-mentioned eight sub-word select lines FX0B to FX7B are allocated to each sub-array and are formed in the wiring channels on the sense amplifier area, the short-side direction as in the memory array of FIG. 32
As many as 256 sense channels are required for each sense amplifier. On the other hand, in the above-described embodiment, the wiring itself is connected to the upper and lower sub-arrays by the eight sub-word select lines FX0B to FX0B.
By allocating 7B in common and arranging them so that they are mixed on the sub-array in parallel with the main word line, it can be formed without providing a special wiring-dedicated area.

In the first place, one main word line is provided for eight sub-word lines on the sub-array, and a sub-word selection line is used to select one of the eight sub-word lines. Is necessary. Sub-word line S formed according to the pitch of the memory cells
Main word line MWL by one of eight WLs
Is formed, the main word line MWL
Have a gentle wiring pitch. Therefore, it is relatively easy to form the above-mentioned sub-word selection line between the main word lines by using the same wiring layer as the main word line MWL, with only a slight sacrifice in the looseness of the wiring pitch. .

The sub-word driver SWD of this embodiment
Is obtained by using a selection signal supplied through the sub-word selection line FX0B and the like and a selection signal obtained by inverting the selection signal.
A configuration for selecting one sub-word line SWL is adopted. The sub-word driver SWD is configured to simultaneously select the sub-word lines SWL of the sub-arrays arranged on the left and right of the sub-word driver SWD. Therefore, as described above, for the two sub-arrays sharing the FX0B or the like, the four sub-word selection lines are allocated and supplied to 128 × 2 = 256 sub-word drivers. That is, focusing on the sub-word selection line FX0B, it is necessary to supply a selection signal to as many as 256 ÷ 4 = 64 sub-word drivers SWD for two sub-arrays.

If the one extending in parallel with the main word line MWL is a first sub-word selection line FX0B,
The six sub-word selection line driving circuits FXD which are provided in the upper left cross area and receive the selection signal from the first sub-word selection line FX0B are arranged in the above-mentioned vertical direction.
A second sub-word selection line FX0 that supplies a selection signal to four sub-word drivers is provided. The first sub-word selection line FX0B extends in parallel with the main word line MWL and the sub-word line SWL, while the second sub-word selection line has a column selection line YS and a complementary bit line BL which are orthogonal thereto. The sub word driver area is extended in parallel. Similarly to the eight first sub-word selection lines FX0B to FX7B, the second sub-word selection lines FX0 to FX7 also have even numbers FX0, 2, 4, 6
And odd word FX1, 3, 5, 7 and subword drivers SW provided on the left and right of subarray SBARY.
D.

The sub word select line driving circuit FXD is
In the same drawing, as shown by a triangle, two pieces are distributed above and below one cross area. That is, as described above, in the upper left cross area, the sub-word selection line driving circuit arranged on the lower side operates the first sub-word selection line F
Two sub-word selection line driving circuits FXD corresponding to X0B and provided in the cross area in the left middle part are disposed above the lower left cross area in correspondence to the first sub-word selection lines FX2B and FX4B. The sub-word selection line driving circuit corresponds to the first sub-word selection line FX6B.

In the upper central cross area, a lower sub word select line driving circuit corresponding to the first sub word select line FX1B is provided, and two sub word select line drivers provided in the central middle cross area are driven. Circuit FXD
Correspond to the first sub-word selection lines FX3B and FX5B, and the sub-word selection line driving circuit disposed above the cross area at the lower center corresponds to the first sub-word selection line FX7B. In the upper right cross area, the lower sub word select line drive circuit corresponds to the first sub word select line FX0B, and two sub word select line drive circuits provided in the right middle cross area. FXD is the first sub-word select line FX2B
And the sub-word selection line driving circuit disposed above the cross area at the lower right of FIG. 4 corresponds to the first sub-word selection line FX6B. Thus, in the sub-word driver provided at the end of the memory array,
Since there is no sub-array on the right side, only the left sub-word line SWL is driven.

As in this embodiment, the sub-word selection line FX is provided in the gap of the pitch of the main word line MWL on the sub-array.
In the configuration in which B is arranged, a special wiring channel can be made unnecessary, so that arranging eight sub-word selection lines in one sub-array does not increase the size of the memory chip. However, the formation of the sub-word select line driving circuit FXD as described above increases the area of the cross region, which hinders high integration. That is, in the cross area, a switch circuit IOSW provided corresponding to the main input / output line MIO and the local input / output line LIO, a power MOSFET driving a sense amplifier, a shared switch MOS
Driving circuit for driving FET, precharge MOS
This is because there is no area allowance because peripheral circuits such as a drive circuit for driving the FET are formed. For this reason, in the embodiment of FIG. 3, the upper and lower sub-arrays share the sub-word select line driving circuit FXD to suppress an increase in area.

Among the cross areas, those arranged in the extension direction A of the second sub-word selection lines FX0 to FX6 corresponding to the even numbers have internal voltages which are made constant with respect to the sense amplifiers as described later. An N-channel power MOSFET Q16 for supplying VDL, an N-channel power MOSFET Q15 for supplying an overdrive power supply voltage VDD, and an N-channel power MOSFET Q14 for supplying a circuit ground potential VSS to the sense amplifier. Is provided.

In the above-mentioned cross areas, those arranged in the extending direction B of the odd-numbered second sub-word select lines FX1 to FX7 include an inverter circuit for turning off the MOSFETs for precharging and equalizing bit lines. Although not particularly limited, an N-channel type power MOSFET for supplying the circuit ground potential VSS to the sense amplifier is provided. This N-channel type power MOSFET supplies a ground potential to the common source line (CSN) of the N-channel type MOSFET amplifying MOSFETs constituting the sense amplifier from both sides of the sense amplifier row. That is, for the 128 or 130 sense amplifiers provided in the sense amplifier area, the N-channel type power MOSFET provided in the cross area on the A side and the N-channel power MOSFET provided in the cross area on the B side are provided. The ground potential is supplied by both of the channel type power MOSFETs.

As described above, the sub word line drive circuit SWD
Selects the sub-word lines of the sub-arrays on both sides with respect to the center. On the other hand, two left and right sense amplifiers are activated corresponding to the sub-word lines of the two selected sub-arrays. That is, when the sub-word line is selected, the address selection MOSFET is turned on,
This is because the charge of the storage capacitor is combined with the charge of the bit line, so that it is necessary to perform a rewrite operation of returning the charge to the original charge state by activating the sense amplifier. Therefore, except for the one corresponding to the subarray at the end, the power MOSFET is used to activate the sense amplifiers on both sides of the power MOSFET. On the other hand, the sub-word line driving circuit SWD provided on the right or left side of the sub-array provided at the end of the sub-array group
Since only the sub-word line of the sub-array is selected, the power MOSFET activates only one sense amplifier group corresponding to the sub-array.

The sense amplifier is of a shared sense type, and among the subarrays arranged on both sides of the shared amplifier, the shared switch MOSFET corresponding to the complementary bit line on the side where the subword line is not selected is turned off. As a result, the read signal of the complementary bit line corresponding to the selected sub-word line is amplified, and a rewrite operation of returning the storage capacitor of the memory cell to the original charge state is performed.

FIG. 4 is a circuit diagram of a simplified embodiment from the address input to the data output centering on the sense amplifier section of the dynamic RAM according to the present invention. In the figure, a sense amplifier 16 sandwiched between two sub-arrays 15 from above and below and a circuit provided in the intersection area 18 are exemplarily shown, and others are shown as block diagrams. The circuit blocks indicated by the dotted lines are indicated by the above-mentioned reference numerals.

The dynamic memory cell is typically exemplified by one provided between the sub-word line SWL provided in the one sub-array 15 and one of the complementary bit lines BL and BLB. Is shown in The dynamic memory cell has an address selection MOS
It comprises an FET Qm and a storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the sub word line S
The drain of the MOSFET Qm is connected to the bit line BL, and the source is connected to the storage capacitor Cs. The other electrode of the storage capacitor Cs is shared and supplied with the plate voltage VPLT. MOS above
A negative back bias voltage VBB is applied to the substrate (channel) of the FET Qm. The selection level of the sub-word line SWL is a high voltage VPP higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm.

When the sense amplifier is operated at the internal step-down voltage VDL, the high level amplified by the sense amplifier and given to the bit line is equal to the internal voltage VD
The level is set to L level. Therefore, the high voltage VPP corresponding to the word line selection level is set to VDL + Vth + α. A pair of complementary bit lines BL and BLB of the sub-array provided on the left side of the sense amplifier are arranged in parallel as shown in the figure, and are appropriately crossed as necessary to balance the bit line capacitance. . The complementary bit lines BL and BLB are connected to the shared switch MOSFET Q1.
And Q2 are connected to the input / output node of the unit circuit of the sense amplifier.

The unit circuit of the sense amplifier is composed of N-channel type amplifying MOSFETs Q5, Q6 and P-channel type amplifying MOSFETs Q7, Q8, whose gates and drains are cross-connected to form a latch. The sources of the N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CS.
Connected to P. Power switch MOSFETs are connected to the common source lines CSN and CSP, respectively. Although not particularly limited, an N-channel type amplification MOS
Common source line C to which the sources of FETs Q5 and Q6 are connected
An operating voltage corresponding to the ground potential is applied to SN by an N-channel type power switch MOSFET Q14 provided in the cross area 18.

Although not particularly limited, the common source line CSP to which the sources of the P-channel type amplification MOSFETs Q7 and Q8 are connected is connected to the N-channel type power MO for overdrive provided in the cross area 18.
An SFET Q15 and an N-channel power MOSFET Q16 for supplying the internal voltage VDL are provided.
The power supply voltage VDD supplied from an external terminal is used for the overdrive voltage, although there is no particular limitation. Alternatively, the voltage may be slightly reduced in order to reduce the power supply voltage VDD dependency of the sense amplifier operation speed. For example, an N-channel MOSFET in which a boosted voltage VPP is applied to a gate and a power supply voltage VDD is applied to a drain
The above step-down voltage can be obtained from the source.

The N-channel type power MOSFET
The sense amplifier overdrive activation signal SAP1 supplied to the gate of Q15 is
Activation signal SAP supplied to the gate of SFET Q16
2, and the signals SAP1 and SAP2 are set to a high level in time series. Although not particularly limited, the signals SAP1 and SAP2 are high-level signals corresponding to the boosted voltage VPP. That is, since the boost voltage VPP is about 3.8 V, the N-channel MOSFET
Q15 and Q16 can be sufficiently turned on. After the MOSFET Q15 is off, the MOSFET
Q16 is turned on and the internal voltage VDL is applied from the source side.
Can be output.

An equalizing MOSF for short-circuiting the complementary bit line is provided at the input / output node of the unit circuit of the sense amplifier.
ETQ11 and switch MOSFETs Q9 and Q10 for supplying half precharge voltage VBLR to complementary bit lines
A precharge (equalize) circuit is provided. The gates of these MOSFETs Q9 to Q11 are commonly supplied with a precharge signal PCB. Although not shown, a driver circuit for forming the precharge signal PCB is provided with an inverter circuit in the above-mentioned cross area to make the falling speed faster. That is, at the start of the memory access, prior to the word line selection timing, the MOSFETs Q9 to Q1 which constitute the precharge circuit through the inverter circuits distributed in each cross area.
1 is switched at high speed.

In the cross area 18, in addition to the circuit shown in FIG. 4, if necessary, a half precharge circuit for the common source lines CSP and CSN of the sense amplifier and a half precharge circuit for the local input / output line LIO are provided. , Shared distributed signal lines SHR and SHL are also provided.

The unit circuit of the sense amplifier is connected to the similar complementary bit lines BL and BLB of the lower sub-array 15 via shared switch MOSFETs Q3 and Q4. The switch MOSFETs Q12 and Q13 constitute a column switch circuit, and are turned on when the selection signal YS is set to a selection level (high level).
Input / output nodes and local input / output lines LIO1 and LIO1B, LIO2, LIO2B of the unit circuit of the sense amplifier
And so on. For example, when the sub-word line SWL of the upper sub-array is selected, the upper shared switch MOSFETs Q1 and Q2 of the sense amplifier remain on and the lower shared switch MOSFET Q3
And Q4 are turned off.

As a result, the input / output node of the sense amplifier is connected to the upper complementary bit lines BL and BLB to amplify the small signal of the memory cell connected to the selected sub-word line SWL. Circuit (Q
12 and Q13) through the local input / output lines LIO1, L
Communicate to IO1B. The local input / output lines LIO1, L
IO1B extends along the sense amplifier row, that is, in the horizontal direction in FIG. The local input / output line LI
O1 and LIO1B are the N provided in the cross area 18.
IO consisting of channel type MOSFETs Q19 and Q20
The input terminals of the main amplifier 61 are connected to main input / output lines MIO and MIOB via a switch circuit. Note that the IO switch circuit is provided with a selection signal IOSW
As a result, a CMOS switch is obtained in which a P-channel MOSFET is connected in parallel to each of the N-channel MOSFETs Q19 and Q20 as described later. Although not shown, the output terminals of the write amplifier are also connected to the main IO lines MIO and MIOB.

Although not particularly limited, the column switch circuit connects two pairs of complementary bit lines BL, BLB to two pairs of local input / output lines LIO1, LI in response to one selection signal YS.
O1B is connected to LIO2 and LIO2B. Therefore,
In the sub-array selected by the operation of selecting one main word line, a total of four pairs of complementary bit lines are selected by the two pairs of column switch circuits provided corresponding to the pair of sense amplifiers provided on both sides thereof. , Four bits can be simultaneously read / written by selecting one YS line. In a burst mode to be described later, the column selection signal YS is switched, and the connection between the local input / output lines LIO1 and LIO1B and the complementary bit lines BL and BLB of the sub-ray is sequentially switched.

The address signal Ai is supplied to the address buffer 5
1 is supplied. The address buffer operates in a time-division manner to receive the X address signal and the Y address signal.
The X address signal is supplied to the predecoder 52, and a selection signal for the main word line MWL is formed via the main row decoder 11 and the main word driver 12. Since the address buffer 51 receives the address signal Ai supplied from the external terminal, it is operated by the power supply voltage VDD supplied from the external terminal, and the predecoder is operated by the step-down voltage VPERI.
The main word driver 12 is operated by the boost voltage VPP. Column decoder (driver) 53
Receives the Y address signal supplied by the time division operation of the address buffer 51 and forms the column selection signal YS.

The main amplifier 61 has a step-down voltage VPE
The signal is output from the external terminal Dout (or DQ) through the output buffer 62 operated by the RI and operated by the power supply voltage VDD supplied from the external terminal. A write signal input from an external terminal Din (or DQ) is taken in through an input buffer 63, and is written to the main input / output lines MIO and MIOB through a write amplifier included in the main amplifier 61 in FIG. Supply. The input section of the output buffer is provided with a level shift circuit and a logic section for outputting the output signal in synchronization with a timing signal corresponding to the clock signal.

Although not particularly limited, the power supply voltage VDD supplied from the external terminal is set to 3.3 V, the step-down voltage VPERI supplied to the internal circuit is set to 2.5 V, and the operating voltage VDL of the sense amplifier is set. Is set to 2.0V. Then, the word line selection signal (boosted voltage)
It is set to 3.8V. Bit line precharge voltage VBL
R is set to 1.0 V corresponding to VDL / 2, and the plate voltage VPLT is also set to 1.0 V. And the substrate voltage V
BB is set to -1.0V.

FIG. 5 is a circuit diagram showing one embodiment of an IO switch circuit of a dynamic RAM to which the present invention is applied. FIG. 2 shows two pairs of local input / output lines LI.
O1 to LIO1B, LIO2, LIO2B and a pair of main input / output lines MIO1, MIO1B are shown. IO switches for another pair of local input / output lines and main input / output lines are provided in cross areas at different positions.

IO switch circuit (MIO-LIOsw)
Are the pair of local input / output lines LIO1, LIO1B
And the corresponding main input / output lines MIO1, MIO
1B. IO switch circuit (MIO-LI
Osw) is the N-channel type MOSF shown in FIG.
A CMOS switch circuit including two N-channel MOSFETs similar to the ETQ19 and the N-channel MOSFET Q20 and two P-channel MOSFETs connected in parallel to each other. The gate of the N-channel MOSFET is supplied with BLEQ as a selection signal, and the gate of the P-channel MOSFET is supplied with BLEQB as a selection signal. A similar IO switch circuit is provided in a cross area at another position, and connects the other local input / output lines LIO2 and LIO2B to the corresponding main input / output lines MIO2 and MIO2B (not shown).

The local input / output lines LIO1 and LIO1
B, a short circuit MO similar to the precharge (equalize) circuit provided for the complementary bit lines BL and BLB is provided.
A local input / output line precharge (equalize) circuit LIOeq including an SFET and a switch MOSFET for supplying a precharge voltage VBLR is provided. This local input / output line precharge circuit LIOeq and the bit line precharge circuit B provided on the complementary bit line
Leq includes a precharge (equalize) signal BLEQ.
A precharge (equalize) signal BLEQB formed by the inverter circuit N3 receiving the signal is supplied.

The main input / output lines MIO and MIOB are connected to a P-channel type MO for short-circuit and for supplying an internal voltage VDL.
A main input / output line precharge (equalize) circuit MIOeq configured by an SFET is provided. The gates of these P-channel MOSFETs are supplied with a precharge (equalize) signal EQMIOB. In the burst mode as described above, the IO switch circuit (MIO
-LIOsw) remains ON, and the column switch is switched by selection YS. That is, the precharge (equalize) operation for the second and subsequent local input / output lines LIO and LIOB is controlled by the same precharge signal as that of the bit line precharge circuit BLeq since the sub-word line of the sub-array remains in the selected state. Local I / O line precharge (equalize) circuit LIOe
q is not operated, and the main input / output line precharge (equalize) circuit MIOeq supplies V during YS selection.
The DL level precharge operation is performed.

Therefore, the precharge operation for the local input / output lines LIO1 and LIO1B through the IO switch circuit (MIO-LIOsw) composed of the MOSFETs described above requires a large number of column switch MOSFETs connected to the local input / output lines. Therefore, a relatively large parasitic capacitance is added and a relatively long time must be spent synergistically.

FIG. 6 is a circuit diagram showing one embodiment of the write amplifier and the main amplifier connected to the main input / output line. The write amplifier (write amplifier) WA
The write signal is applied to the main input / output line MIO by the internal voltage VDL.
P-channel type MOSF that supplies high level like
ETQ31, N-channel MOSFET Q30 for supplying a circuit ground potential, P-channel MOSFET Q33 for supplying a write signal to main input / output line MIOB at a high level such as internal voltage VDL, and N for supplying a circuit ground potential And a channel type MOSFET Q32. Write signals MIDDT to MIPBB are supplied to the gates of these MOSFETs Q31 to Q34.

The main input / output lines MIO and MIOB are P-channel MOSFET selection switches MOSFET Q
It is connected to the input terminal of a main amplifier as a readout amplifier via 34 and Q33. A pair of input terminals of this main amplifier are connected to three P-channel type M
A VPERI level precharge circuit composed of an OSFET is provided. The main amplifier is composed of P-channel MOSFETs Q36 and Q
37 and an N-channel type MOSFET which is turned on by a main amplifier control signal MAE using a CMOS latch circuit comprising N-channel type MOSFETs Q38 and Q39.
An operating current flows through the SFET Q40.

The output signal of the main amplifier MA is composed of a P-channel MOSFET Q41 and an N-channel MOSFET Q41.
Input to the CMOS inverter circuit composed of Q42.
This CMOS inverter circuit includes an N-channel MOSFET Q43 operated by the control signal MAE.
Is operated. The output of the CMOS inverter circuit is connected to the CMOS inverter circuits N1 and N1.
2 is provided and transmitted to an output buffer (not shown).

FIG. 7 is a logic circuit diagram of one embodiment of the timing generation circuit provided in the dynamic RAM according to the present invention. Internal clock signal ICLKB formed by a clock signal supplied from an external terminal
Is supplied to a delay circuit D1 having a delay time corresponding to a pulse width required for a read operation, and the delay signal and the clock signal ICLKB
To the OR gate circuit G1 to supply a pulse signal P having a relatively long pulse width corresponding to the delay time of the delay circuit D1.
Form one. On the other hand, the clock signal ICLKB is supplied to a delay circuit D2 having a delay time corresponding to a pulse width required for a write operation,
The delay signal and the clock signal ICLKB are supplied to an OR gate circuit G2 to form a pulse signal P2 having a relatively short pulse width corresponding to the delay time of the delay circuit D2.

The pulse P1 is output through an AND gate circuit G3 controlled by a read control signal BRD so as to be generated at the time of a read operation. The pulse P2 is output through an AND gate circuit G4 controlled by a write control signal BWT in order to generate the pulse at the time of a write operation. The above gate circuit G3
And the output signal of G4 is supplied to the Y selection circuit as a pulse signal YSE through an OR gate circuit G5. The output signal of the gate circuit G3 is also used to form the main amplifier control signal for performing a read operation.
The output signal of the gate circuit G4 is also used to control a write circuit. And YIOR, YIOW
Are also used to form a control signal EQMIOB supplied to a main input / output line precharge circuit MIOeq provided on the main input / output lines MIO, MIOB.

The Y-system address signals A0 to A7 are fetched via a Y-system address buffer operated by a clock signal ICLKAY, and are read by a predecoder.
AY00-07, AY3 by combination of bits
AY60 by the combination of 0-37 and the remaining 2 bits
A predecode signal like -63 is formed. Of these predecode signals, although not particularly limited, the predecode signal corresponding to AY00-AY07 and the pulse signal YSE are combined by an AND gate circuit G6 to form a column timing signal φY00-07. The timing signal φY00-07 and the remaining predecode signal are supplied to a NAND gate circuit G7 to form one selection signal, and a column selection signal YS is formed through an inverter circuit N4 as a driver. In order to realize the burst operation of the synchronous DRAM, an address counter is placed at the next stage of the Y-system address buffer.
At the next rising edge of ICLKAY, external address signal A
The address signal incremented by the counter operation is generated in the memory chip without taking in 0 to A7.

In this configuration, at the time of the read operation,
The selection signal YS is set to the selection level for a relatively long time corresponding to the pulse width corresponding to the delay time D1. That is, the complementary bit lines BL, BL
B and the local input / output lines LIO, LIOB are connected. As a result, the signal level read from the complementary bit lines BL and BLB to the local input / output lines LIO and LIOB can be increased to about 100 mV to 150 mV required for stable operation of the main amplifier. The equalization can be completed in a relatively short time because of the low amplitude as described above.

In the write operation, the selection signal Y
S is set to a selection level for a relatively short time corresponding to the pulse width corresponding to the delay time D2. That is, the complementary bit lines BL and BLB are connected to the local input / output lines LIO and LIOB for a relatively short time. In a write operation,
As described above, the write amplifiers provided on the main input / output lines MIO and MIOB transmit a signal having a larger amplitude as compared with the read operation such as the voltages VDL and VSS. If the bit line pair is inverted by the high level of the selection signal YS, the write operation to the memory cell is continuously performed by the amplifying operation of the sense amplifier SA even after the column switch is turned off by the low level of the selection signal YS. The selection time of the high level of the selection signal YS may be short. In a predetermined clock cycle time, the precharge time can be extended correspondingly, and the level of the large amplitude main input / output line MIO and local input / output line LIO is reliably precharged (equalized) to the VDL level. Can be done.

FIG. 8 is a schematic layout diagram of an embodiment of a synchronous DARM (dynamic RAM) to which the present invention is applied. The configurations of the memory array and the sub-array are basically the same as the embodiment of FIG. However, in order to further reduce the area, a main row decoder 11 and a main word driver 12 are collectively provided in the central portion in the longitudinal direction of the memory chip, and the entire chip is divided into four parts by the peripheral circuit region 14 as described above. In this case, banks 0 to 3 are assigned to the respective banks.

In one bank, 16 subarrays are provided in the word line direction. Two pairs of main input / output lines are extended to a sub-word driver region sandwiched between two sub-arrays. Therefore, one bank is provided with 2 × 8 = 16 pairs of main input / output lines. Each main input / output line is provided with the main amplifier MA and the write amplifier WA. Therefore, 16 main amplifiers and 16 write amplifiers are provided for one bank,
Memory access is performed in units of 16 bits. And a synchronous DRAM designated by a command.
Are as follows.

(1) Mode register set command (M
o) A command for setting a mode register included in the input circuit, CSB, RASB, CASB, W
The command is designated by EB = low level, and the data to be set (register set data) are A0 to Ai.
Given through. Here, CSB is a chip select signal, RASB is a row address strobe signal, CASB is a column address strobe signal, WEB is a write enable signal, and B at the end of each signal name is low level active. Indicates that it is a level.

Although not particularly limited, the register set data is set to a burst length, a CAS latency, a write mode, or the like. Although not particularly limited, the settable burst length is 1, 2, 4, 8, and full page, the settable CAS latency is 1, 2, 3, and the settable write modes are burst write and Single light.

The above-described CAS latency indicates how many cycles of the internal clock signal should be spent from the fall of CASB to the output operation of the output buffer in a read operation specified by a column address read command described later. is there. Internal operation time for data reading is required until the read data is determined,
This is to set it according to the operating frequency of the internal clock signal. For example, when using a high-frequency internal clock signal, the CAS latency is set to a relatively large value, and when using a low-frequency internal clock signal, the CAS latency is set to a relatively small value.

(2) Row address strobe / bank active command (Ac) This is a command for row address strobe and A12, A1
3 is a command for enabling the selection of the memory bank by CSB, RASB = low level, CASB, WEB
= High level. At this time, the address excluding the upper 2 bits is taken as a row address signal, and the address signals A12 and A13 of the upper 2 bits are taken as a memory bank selection signal. The fetch operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

(3) Column address read command (Re) This command is a command necessary for starting a burst read operation and a command for giving an instruction of a column address strobe. CSB, CASB =
Instructed by low level, RASB, WEB = high level, the column address supplied at this time is taken in as a column address signal. The fetched column address signal is supplied to the column address counter as a burst start address. In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the internal clock signal. Are sequentially selected in accordance with the address signal output from the column address counter and are successively read out. The number of data to be continuously read is the number specified by the burst length. Also,
Data reading from the output buffer is started after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

(4) Column Address Write Command (Wr) When a burst write is set in the mode register as a mode of the write operation, it is a command necessary to start the burst write operation, and the mode of the write operation When single write is set in the mode register, the command is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. The command is CSB, CAS
Instructed by B, WEB = low level and RASB = high level, the address supplied at this time is taken in as a column address signal. The fetched column address signal is supplied to the column address counter as a burst start address in burst write. The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of write data is started from the column address / write command cycle.

(5) Precharge command (Pr) This is a command to start a precharge operation for the memory bank selected by the upper two-bit address signal. CSB, RASB, WEB = low level, C
Instructed by ASB = high level.

(6) Auto-refresh command This command is required to start auto-refresh, and includes CSB, RASB, and CAS.
Instructed by B = low level, WEB, CKE (clock enable) = high level.

(7) Burst stop in full page command This command is required to stop the burst operation for a full page for all memory banks, and is ignored in burst operations other than the full page. This command is CSB, WEB = low level, RASB, CAS
B = indicated by high level.

(8) No operation command (No
p) This is a command for instructing that no substantial operation is performed. CSB = low level, RASB, CASB, WE
Indicated by the high level of B.

FIG. 9 is a waveform chart for explaining the operation of the synchronous DRAM to which the present invention is applied. FIG. 2 shows a case where the burst length BL = 2 and the CAS latency CL = 2 as an example. The above BL =
2, CL = 2 is set in the mode register as described above. As described above, BL = 2 means that reading / writing is performed from two column switches in two continuous cycles, and CL = 2 means that output data is output from the output terminal DQ two cycles after the read command. Output.

In response to a bank active command, a row-related address signal is fetched from an address input terminal (not shown), and is decoded to obtain a sub-word line SW.
L is brought to a selection level such as VPP. This allows
A minute read signal appears on the complementary bit lines BL and BLB. Since the sense amplifier is activated by the operation timing signal, the small read signal of the complementary bit lines BL and BLB is amplified to a high level such as VDL and a low level such as VSS, and the memory in which the sub-word line is selected. Rewriting (refresh) to the cell is performed.

A write command is input two cycles after the active command, a column address signal (not shown) is fetched, and a column selection signal YS1 rises. As a result, the column switch is turned on during this time, and VDL and VSS are switched from the main input / output lines MIO and MIOB.
Is transmitted to the bit line pair, the bit line pair can be inverted and written in a short time, the column selection signal YS1 is set to the non-selection level, and the main input / output line is precharged. Circuit MIOe
q starts operation and sets the main input / output lines MIO and MIOB and the local input / output lines LIO and LIOB (not shown) to VD.
In the next clock cycle, the Y address is incremented by the address counter, YS2 is selected, and the same write operation and precharge operation as described above are performed in the next clock cycle.

For example, a read command is input two more cycles after the write command, a column address signal (not shown) is fetched in the same manner as described above, and a column selection signal YS3 is raised to select the selected complementary bit lines BL and B.
The LB read signal is supplied to the local input / output lines LIO, LIO
B and the main input / output lines MIO, MIOB to obtain a voltage difference of 100 to 150 mV,
The output signal MO is amplified by the main amplifier activated by the AE. In the above read operation,
The selection period of YS3 is lengthened, and
Since a voltage difference of mV is obtained, a stable read operation can be performed. MIO pair as above, LI
It takes only a short time to precharge the VDL with a relatively small voltage difference between the O pair. In the next clock cycle, the Y address is incremented, YS4 is selected, and the same read operation and precharge operation as described above are performed.
The output signal MO of the main amplifier is controlled by the timing signal MOE and DOC and level converted immediately before the output buffer to form an output signal DQ.

In the present invention, since the pulse width of the column selection signal YS is set short at the time of writing, the precharge time after writing can be lengthened by that amount, and the large amplitude input / output lines MIO and LIO are set to the selection signal of the next cycle. VDL can be precharged before YS is brought high. At the time of reading, the pulse width of the column selection signal YS is set to be long, so that the input / output line MI
A read signal having a potential difference sufficient for O can be obtained, which contributes to stable and high-speed operation of the main amplifier. The precharge of a small potential difference between the MIO line pair and the LIO line pair at the time of reading can be completed in an extremely short time. With such a configuration, for example, for a synchronous DRAM having an upper limit frequency of about 120 MHz,
By applying the present invention of switching the column selection pulse width at the time of writing and at the time of reading as described above, it is possible to increase the speed up to about 160 MHz even with the same device function.

The operation and effect obtained from the above embodiment are as follows. That is, (1) a memory array in which a plurality of memory cells are provided at intersections of a plurality of word lines and a plurality of complementary bit lines, and a memory array selected from the plurality of complementary bit lines by a selection signal in common complement A semiconductor memory device comprising: a column switch connected to an input / output line; and a precharge circuit for setting the common complementary input / output line to a predetermined same potential.
When reading, the column switch selection period is lengthened and the pre-charge period of the common complementary input / output line is shortened accordingly. During writing, the column switch selection period is shortened and the pre-charge period of the common complementary input / output line is shortened accordingly. And the memory cycle period at the time of reading and writing can be made substantially the same short clock cycle time.

(2) A selection signal transmitted to the column switch is converted into a clock signal supplied from an external terminal,
The logic circuit is formed by a logic of a pulse signal having two pulse widths corresponding to the read period and the write period corresponding to the read control signal and the write control signal, respectively, and a selection signal formed by a Y-system address decoder. By generating the precharge signal of the precharge circuit based on the pulse signal, an effect is obtained that the memory cycle period corresponding to the clock signal supplied from the external terminal can be reduced to almost the same short clock cycle. Rara.

(3) By using a dynamic memory cell including an address selection MOSFET and a storage capacitor as the memory cell, a memory corresponding to a high-frequency clock signal supplied from an external terminal while increasing the storage capacity is achieved. The effect that recycling can be achieved is obtained.

(4) The word lines are divided into a main word line and a length divided in the direction in which the main word line extends, and a plurality of the word lines are arranged in a bit line direction crossing the main word line. A hierarchical word line system comprising sub-word lines to which address selection terminals of a plurality of dynamic memory cells are connected, wherein the complementary bit lines are arranged so as to be orthogonal to the plurality of sub-word lines, and A sub-array is formed together with the sub-word line as a plurality of pairs of complementary bit lines, one of which is connected to the input / output terminal of the cell, and the local complementary input / output line is provided corresponding to the small number of sub-arrays. And main input / output lines provided corresponding to a number of sub-arrays arranged in the bit line direction. A precharge circuit is provided for each of the input / output line and the main input / output line, and the input terminal of the read amplifier and the output terminal of the write amplifier are connected to the main input / output line, respectively, thereby achieving a large storage capacity. In addition, an effect is obtained that a memory cycle corresponding to a high-frequency clock signal supplied from an external terminal can be realized.

(5) Sub-word line driving circuits are divided and arranged at both ends of the plurality of sub-word line arrays, and sense amplifiers are divided and divided at both ends of the plurality of complementary bit line arrays. The one sub-array is formed so as to be surrounded by the plurality of sub-word line driving circuit rows and the plurality of sense amplifier rows, and the local input / output lines are extended along the sense amplifiers. While increasing the storage capacity, the local input / output lines are divided and arranged for each of a small number of sub-array groups to reduce the parasitic capacitance and to reduce the memory cycle corresponding to a high-frequency clock signal supplied from an external terminal. The effect that it can be realized is obtained.

(6) A shared sense system is provided corresponding to a bit line pair of an adjacent sub-array centered on a sense amplifier, and the column switch is provided between an input / output node of the sense amplifier and the local input / output line. With this arrangement, an effect is obtained that data can be efficiently read and written between a large number of memory cells and a small number of local input / output lines.

(7) By applying the present invention to a synchronous DRAM, an effect that the operating frequency can be significantly increased by adding a simple circuit while using the same circuit can be obtained.

Although the invention made by the present inventors has been specifically described based on the embodiments, the invention of the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the dynamic RAM shown in FIG. 1 or FIG. 8, the configuration of the memory array, sub-array, and sub-word driver can employ various embodiments, or may be a word shunt system without using a sub-word driver. The dynamic RAM may have a high-speed page mode or a column static mode in addition to the burst mode described above. The semiconductor memory device as described above may be built in a digital integrated circuit such as a one-chip microcomputer. The present invention can be widely used for semiconductor memory devices.

[0090]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a memory array in which a plurality of memory cells are provided at the intersections of a plurality of word lines and a plurality of complementary bit lines, and a memory array selected from the plurality of complementary bit lines by a selection signal are used as common complementary input / output lines. And a precharge circuit for setting the common complementary input / output line to a predetermined same potential. In a semiconductor memory device, when reading, a column switch selection period is lengthened and the common complementary input / output line is correspondingly extended. By shortening the precharge period of the output line and shortening the selection period of the column switch at the time of writing and extending the precharge period of the common complementary input / output line by that much, the memory cycle period at the time of reading and writing is substantially reduced. The same short clock cycle time can be achieved.

[Brief description of the drawings]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a schematic layout diagram for explaining a dynamic RAM to which the present invention is applied;

FIG. 3 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuits in a dynamic RAM according to the present invention.

FIG. 4 is a circuit diagram showing a simplified embodiment from address input to data output centering on the sense amplifier section of the dynamic RAM according to the present invention.

FIG. 5 is a circuit diagram showing an embodiment of an IO switch circuit of a dynamic RAM to which the present invention is applied.

6 is a circuit diagram showing one embodiment of a write amplifier and a main amplifier connected to main input / output lines in the dynamic RAM of FIG. 5;

FIG. 7 is a logic circuit diagram showing one embodiment of a timing generation circuit provided in the dynamic RAM according to the present invention.

FIG. 8 is a schematic layout diagram showing an embodiment of a synchronous dynamic RAM to which the present invention is applied.

9 is a waveform chart for explaining an example of the operation of the synchronous dynamic RAM of FIG. 8;

[Explanation of symbols]

10: memory chip, 11: main row decoder area,
12: Main word driver area, 13: Column decoder area, 14: Peripheral circuit, bonding pad area, 1
5 Meseli cell array (subarray), 16 Sense amplifier area, 17 Subword driver area, 18 Cross area (cross area), 51 Address buffer, 52
... Predecoder, 53 ... Decoder, 61 ... Main amplifier, 62 ... Output buffer, 63 ... Input buffer, BLe
q: bit line precharge circuit, LIOeq: local input / output line precharge circuit, MIOeq: main input / output line precharge circuit, MIO-LIOsw: IO switch circuit, MA: main amplifier, WA: write amplifier, D
1, D2 delay circuit, G1 to G6 gate circuit, N1
N4: an inverter circuit; Q1 to Q35: MOSFETs.

Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/10 681E (72) Inventor Yoji Dei 5-2-1, Josuihoncho, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd. (72 ) Inventor Goro Tachibanakawa 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Michihiro Mishima 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Co., Ltd. Hitachi Semiconductor Division

Claims (7)

[Claims] 1. A memory array comprising a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of complementary bit lines, and a memory array selected from a plurality of complementary bit lines by a selection signal. A column switch connected to the input / output line; a precharge circuit for setting the common complementary input / output line to a predetermined same potential; a read amplifier for amplifying a read signal of the common complementary input / output line; And a write amplifier for transmitting a write signal to the line. In the read operation, the selection period of the column switch is lengthened and the precharge period of the common complementary input / output line is shortened accordingly. In the write operation, the selection period of the column switch is shortened. The precharge period of the common complementary input / output line is extended correspondingly, and the memory size at the time of reading and writing is increased. The semiconductor memory device characterized by comprising almost the same Le period. 2. The selection signal transmitted to the column switch includes a clock signal supplied from an external terminal, and two types of signals corresponding to the read period and the write period corresponding to a read control signal and a write control signal, respectively. An output signal of a pulse generation circuit for generating a pulse signal having a pulse width;
The precharge signal of the precharge circuit is generated based on the output signal of the pulse generation circuit. The precharge signal is formed by logic with a selection signal formed by a Y-system address decoder. 2. The semiconductor memory device according to claim 1, wherein: 3. The memory cell according to claim 1, wherein a gate is connected to a corresponding word line, and one source and drain are connected to one of the corresponding complementary bit lines.
3. A semiconductor device according to claim 2, wherein said memory cell is a dynamic memory cell comprising an ET and a storage node having a storage node connected to the other source and drain of said address selection MOSFET and a predetermined voltage applied to the other. Storage device. 4. The word line has a main word line and a length divided in an extension direction of the main word line, and a plurality of the word lines are arranged in a bit line direction intersecting the main word line. And a sub-word line connected to address selection terminals of a plurality of dynamic memory cells, wherein the complementary bit lines are arranged so as to be orthogonal to the plurality of sub-word lines, A terminal is composed of a plurality of complementary bit line pairs connected to one of them, and a sub-array is constituted by the plurality of sub-word lines and the plurality of complementary bit line pairs and a plurality of dynamic memory cells provided at intersections thereof. The common complementary input / output lines are provided corresponding to the subarrays, and are arranged in the bit line direction with the local input / output lines. A main input / output line provided corresponding to a plurality of sub-arrays, a precharge circuit is provided for each of the local input / output line and the main input / output line, and an input terminal of a read amplifier is provided for the main input / output line. 4. The semiconductor memory device according to claim 3, wherein an output terminal of the write amplifier is connected to the write amplifier. 5. The sub-array, wherein sub-word line drive circuits are divided and arranged on both ends of the plurality of sub-word line arrays, and sense amplifiers are distributed on both ends of the plurality of complementary bit line arrays. The one sub-array is formed so as to be surrounded by the plurality of sub-word line drive circuit rows and the plurality of sense amplifier rows, and the local input / output lines are arranged along the sense amplifiers. 5. The semiconductor memory device according to claim 4, wherein said semiconductor memory device is extended. 6. The sense amplifier is of a shared sense type and is provided corresponding to a bit line of an adjacent sub-array centered on the shared sense system. The column switch includes an input / output node of the sense amplifier and the sense amplifier. 6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is provided between the local input and output lines. 7. The synchronous memory device according to claim 1, wherein
4. A RAM constituting a RAM.
Semiconductor storage device.