JPH1126590A - Integrated circuit and its pattern design method and design apparatus - Google Patents

Abstract

(57) Abstract: To prevent latch-up of an integrated circuit due to a parasitic bipolar transistor without increasing a chip area. A power supply wiring (12) for supplying power to a basic cell (11) to an integrated circuit formed on a semiconductor substrate by a basic cell (11) and a wiring connected to the basic cell (11).
And a substrate contact diffusion region 17 formed inside a region of the power supply wiring 12 on the semiconductor substrate or well 10 of the integrated circuit, and a uniform size formed inside the substrate contact diffusion region 17. And a plurality of through holes 18A for substrate contact having a thickness.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit formed on a semiconductor substrate and a method and an apparatus for designing a pattern thereof.

[0002]

2. Description of the Related Art In recent years, with the progress of miniaturization of patterns in the process of manufacturing CMOS integrated circuits, latch-up has become a serious problem. Latch-up is C
Since a parasitic transistor of a bipolar type is formed inside a MOS integrated circuit and has a thyristor structure, a phenomenon in which the thyristor is turned on by a trigger such as a surge and an excessive current continues to flow. As a countermeasure against latch-up, a potential difference between a source of a MOS transistor and a source to be connected to a power supply potential and a semiconductor substrate or between the source and a well formed in the semiconductor substrate is prevented. Method.

A conventional latch-up measure in a cell-based design will be described with reference to FIG. FIG. 4 is a pattern diagram showing a conventional integrated circuit. In FIG.
The basic cell 11 is a cell formed in the semiconductor substrate or the well 10. The power supply wiring 12 is connected to each basic cell 1
1 is a wiring for supplying a power supply voltage to 1. The first wiring 13 is a wiring for connecting the basic cells. The second wiring 14 is a wiring made of polysilicon used as necessary. The diffusion region 15 in the basic cell
This is a diffusion region formed in the basic cell 11. The through hole 16 in the basic cell is formed in the diffusion region 15 in the basic cell for connecting the pattern to be connected to the source and power supply potential of the MOS transistor of the basic cell 11 to the semiconductor substrate or the well 10. This is the interlayer connection means. Diffusion region 15 and through hole 1 in basic cell
6, the source in the basic cell 11 and the semiconductor substrate or the well 10 are connected, so that the semiconductor substrate or the well 10 is fixed to the power supply potential (hereinafter, the semiconductor substrate or the well 10 is fixed to the power supply potential). Is called a substrate contact). This can prevent a potential difference between the source of the MOS transistor and the semiconductor substrate or well 10 from occurring.

[0004]

However, according to the above-mentioned conventional structure, the number and size of through-holes decrease with the progress of miniaturization of the pattern. Since the resistance is higher than the wiring 12, a potential difference is easily generated between the source of the MOS transistor and the semiconductor substrate or the well 10, and
Latch-up is likely to occur and the latch-up withstand voltage decreases. On the other hand, if a substrate contact is added in the basic cell as a countermeasure, the chip area increases.

An object of the present invention is to provide an integrated circuit capable of preventing latch-up without increasing the chip area in view of the above-mentioned conventional problems.

[0006]

In order to solve the above object, the present invention provides an integrated circuit formed on a semiconductor substrate by a basic cell and wiring connected to the basic cell, and a power supply to the basic cell. In a region of a power supply line for supplying, a semiconductor substrate or a well formed on the semiconductor substrate and the power supply line are connected to each other with a substrate contact diffusion region and a substrate contact through hole. Things.

With the above configuration, the power supply wiring is securely connected to the semiconductor substrate or the well, and the semiconductor substrate or the well is reliably fixed at the power supply potential.

[0008]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) Hereinafter, an integrated circuit and a pattern design apparatus according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a pattern diagram of an integrated circuit according to the present embodiment. The same elements as those of the conventional integrated circuit are denoted by the same reference numerals, and description thereof will be omitted. The substrate contact diffusion region 17 is a diffusion region formed in a diffusion region formed of a region where only the power supply wiring 12 is disposed on the semiconductor substrate or the well 10. The substrate contact through holes 18A are through holes formed in the substrate contact diffusion region 17 and each having a uniform size. The semiconductor substrate or well 10 and the power supply wiring 12 are securely connected by the substrate contact diffusion region 17 and the plurality of substrate contact through holes 18A, and the semiconductor substrate or well 10 is reliably fixed at the power supply potential.

FIG. 2 is a block diagram showing the configuration of the pattern design apparatus according to the first embodiment of the present invention. In FIG. 2, the contact array generating means 20 generates a contact array composed of through holes having a uniform size based on the received design rules, and receives the received first pattern composed of a pattern having no substrate contact in the power supply wiring. Is a pattern arranging means for arranging the contact array in the pattern P1 and supplying a second pattern P2 composed of a pattern in which the contact array is arranged. The standard calculating means 21 is a standard determining means for calculating and supplying a standard for the substrate contact diffusion region and the through hole based on the received design rule. Logical operation and resizing means 2
Reference numeral 2 denotes a pattern generation unit for generating and supplying a third pattern P3 including a pattern having a substrate contact in the power supply wiring based on the received standard and the second pattern P2. The logical operation and resizing means 22 performs a logical operation on the pattern based on the standard and the second pattern P2, and changes the size of the obtained diffusible area, that is, resizes the diffused area to the substrate contact diffusion area. The respective patterns of the hole possible area are generated, and a third pattern P3 is generated by performing a logical operation based on the through hole possible area and the second pattern P2. The contact array generation means 20, the standard calculation means 21, and the logical operation and resizing means 22 together constitute a pattern design device 23.

The operation of the pattern design apparatus of FIG. 2 will be described with reference to FIG. The contact array generation means 20 includes:
The chip size of the integrated circuit is measured, the arrangement of the contact array that can be arranged within the chip size is calculated according to the design rule, and the arrangement is arranged on the first pattern P1 to generate the second pattern P2. I do. The standard calculation means 21 determines a standard resize value for each interval between the outer edge of the power supply wiring 12 to the substrate contact diffusion region 17 and the substrate contact through hole 18A based on the design rule. Further, the standard calculating means 21 calculates a value obtained by multiplying a specified value of the minimum pattern width defined by the design rule by a predetermined coefficient, and determines a checking standard.

The logical operation and resizing means 22 operates as follows. First, a pattern excluding the second wiring 14, which is an area where a substrate contact cannot be formed, from the power supply wiring pattern of the second pattern P2, that is, a diffusion-possible area is generated by calculation. For example, an operation of calculating the logical product of the data representing the semiconductor substrate or well 10 and the power supply wiring 12 and obtaining the logical product of the data obtained by the logical product and the inverted data of the data representing the second wiring 14. Thus, data representing the spreadable area is generated. Next, based on the resize value and the generated data, the data of the substrate contact diffusion region 17 and the through-hole possible region are arranged so as to be arranged inward by the respective resize values from the outer edge of the diffuseable region. Generate each. Each resize value is determined in advance so that the through-hole possible region is inside the substrate contact diffusion region 17. Next, the logical product of the generated through-hole possible area and the data representing the contact array of the second pattern P2 is calculated, and the data of the through-hole 18A for the substrate contact is generated. Also, a minute pattern that does not satisfy the check standard is corrected by removing, reducing, or enlarging the pattern. Also, the level of the power supply potential (VDD, VS
It is necessary to discriminate and output the N-type diffusion region and the P-type diffusion region according to S) and the conductivity type of the well (P-type, N-type). Therefore, based on the data representing the power supply wiring pattern that differentiates the level and the data representing the well pattern that distinguishes the conductivity type, the conductivity type of the diffusion region is distinguished and generated. By the above operation, the logical operation and resizing means 22 generates and supplies the third pattern P3 including the pattern in which the substrate contact exists in the power supply wiring.

As described above, according to the present embodiment, the substrate contact diffusion region 17 formed in the power supply wiring 12 and the plurality of substrate contact through holes 18A are formed.
The semiconductor substrate or well 10 and the power supply wiring 12
And the semiconductor substrate or well 10 is reliably fixed at the power supply potential. In addition, since the current capacity of the power supply wiring 12 increases as the number of substrate contacts increases, noise radiation decreases and malfunction due to noise entering from the outside decreases. Further, since the through holes 18A for the substrate contact are each formed of a through hole having a uniform size, a through hole with good controllability and little variation in a manufacturing process can be formed.

In the present embodiment, the contact array is formed by through holes having a uniform size. In addition, the contact array is formed by setting the through holes at equal pitches (equal center-to-center distances). You may.

(Second Embodiment) Hereinafter, an integrated circuit and a pattern design apparatus according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a pattern diagram of the integrated circuit according to the present embodiment. The same elements as those of the integrated circuit according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. The substrate contact through hole 18B is a single through hole formed in the substrate contact diffusion region 17. The semiconductor substrate or well 10 and the power supply wiring 12 are securely connected by the substrate contact diffusion region 17 and the substrate contact through hole 18B, and the semiconductor substrate or well 10 is reliably fixed at the power supply potential.

The pattern designing apparatus according to the present embodiment is different from the pattern designing apparatus shown in FIG. 2 in that the contact array generating means 20 is omitted and the logical operation and resizing means 2 is used.
In 2, this can be realized by making the through hole possible area into one through hole 18 B for substrate contact as it is.

As described above, according to this embodiment, the semiconductor substrate or the well is formed by the substrate contact diffusion region 17 formed in the power supply wiring 12 and the single substrate contact through hole 18B having a large area. The semiconductor substrate or well 10 is reliably fixed at the power supply potential. In addition, since the current capacity of the power supply wiring 12 increases due to an increase in the area of the substrate contact, noise radiation is reduced, and malfunction due to noise entering from the outside is reduced.

[0017]

According to the present invention, a semiconductor substrate or a well can be reliably supplied with power by a substrate contact diffusion region and a plurality of or a single through-hole for a large substrate contact formed in a power supply wiring region. Fix to potential. As a result, it is possible to prevent latch-up due to the parasitic bipolar transistor without increasing the chip area.

[Brief description of the drawings]

FIG. 1 is a pattern diagram of an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a pattern design apparatus according to the first embodiment of the present invention.

FIG. 3 is a pattern diagram of an integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a pattern diagram of a conventional integrated circuit.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate or well 11 Basic cell 12 Power supply wiring 13 First wiring 14 Second wiring 15 Diffusion region in basic cell 16 Through hole in basic cell 17 Diffusion region for substrate contact 18A, 18B Substrate Through hole for contact

Claims (6)

[Claims] 1. An integrated circuit formed on a semiconductor substrate by a basic cell and a wiring connected to the basic cell, the power supply wiring for supplying power to the basic cell, the semiconductor substrate and the power supply A wiring, or a well formed on the semiconductor substrate and the power supply wiring, for connecting a diffusion region and a plurality of through holes having a uniform size in the diffusion region. Integrated circuit. 2. A method for designing a pattern of an integrated circuit formed on a semiconductor substrate, comprising: a contact array generating step of generating in advance data representing a contact array comprising through holes having a uniform size; A logical product of the data representing the semiconductor substrate and the power supply wiring based on the data representing the well to be formed thereon and the power supply wiring to be formed on the semiconductor substrate or the well, or the well and the power supply wiring, respectively. And a substrate contact diffusion region and a substrate contact for connecting the semiconductor substrate or well and the power supply wiring inside the diffusible region represented by the logical product. Data each representing a through hole for use is generated at a predetermined interval from the outer edge of the diffusable area, and A logical operation and a resizing step of generating a logical product of the data representing the tact array and the through hole for the substrate contact, and a standard calculating step of calculating the standard of the interval in advance based on a design rule. Pattern design method. 3. A pattern design apparatus for designing a pattern of an integrated circuit formed on a semiconductor substrate, comprising: a contact for previously generating data representing a contact array comprising through holes having a uniform size; An array generating means, based on data representing a well to be formed on the semiconductor substrate and power supply wiring to be formed on the semiconductor substrate or the well, respectively, A logical product or a logical product of data representing each of the well and the power supply wiring, for connecting the semiconductor substrate or the well and the power supply wiring to the inside of the diffusible region represented by the logical product. Data representing each of the substrate contact diffusion region and the substrate contact through-hole is stored at predetermined intervals from the outer edge of the diffusible region. And a logical operation and resizing means for generating a logical product of the data representing the contact array and the through hole for the substrate contact, respectively, and the standard of the interval in advance based on the received design rule. A pattern design apparatus comprising: a standard calculation unit for calculating. 4. An integrated circuit formed on a semiconductor substrate by a basic cell and a wiring connected to the basic cell, the power supply wiring for supplying power to the basic cell, the semiconductor substrate and the power supply An integrated circuit comprising: a diffusion region for connecting a wiring or a well formed on the semiconductor substrate to the power supply wiring; and a single through hole in the diffusion region. 5. A method for designing a pattern of an integrated circuit formed on a semiconductor substrate, wherein a well to be formed on the semiconductor substrate and a power supply wiring to be formed on the semiconductor substrate or the well are respectively represented. A logical product of data representing the semiconductor substrate and the power supply wiring or a logical product of data representing the well and the power supply wiring is generated based on the data, and the logical product of the spreadable region represented by the logical product is generated. Inside, data respectively representing a substrate contact diffusion region and a substrate contact through-hole for connecting the semiconductor substrate or well to the power supply wiring are generated at predetermined intervals from the outer edge of the diffusible region. A logical operation and a resizing step of calculating the standard of the interval based on a design rule in advance. Down design method. 6. A pattern designing apparatus for designing a pattern of an integrated circuit formed on a semiconductor substrate, comprising: a well to be formed on the semiconductor substrate; and a well to be formed on the semiconductor substrate or the well. A logical product of data representing the semiconductor substrate and the power supply wiring or a logical product of data representing the well and the power supply wiring is generated based on the data representing the power supply wiring and the logical product. Inside the formed diffusible region, data respectively representing a substrate contact diffusion region and a substrate contact through hole for connecting the semiconductor substrate or well and the power supply wiring are respectively specified from an outer edge of the diffusable region. Logical operation and resizing means for generating at intervals of, and calculating the standard of the interval in advance based on the received design rules. Pattern design apparatus being characterized in that a standard calculation means.