JPH11266593A - Motor synchronous control circuit - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide a synchronous control circuit for a motor that is effective when the motor speed is changed. A phase difference detector (9) to which a reference frequency signal and an output frequency signal of a motor are input, a pulse generator (10) triggered by an output of the phase difference detector to generate a pulse signal, A high level detector (13) for detecting a high level output of the comparator, a low level detector (14) for detecting a low level output of the phase comparator, and a high level detector supplied with the output of the pulse generator A first switch circuit (11) that is controlled by the output of the first circuit and outputs a first synchronization pattern, and receives the output of the pulse generator and outputs the second synchronization pattern that is controlled by the output of the low-level detector. A second switch circuit (12) for supplying a control DC voltage based on the synchronization pattern output to the motor driver (6).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a motor synchronous control circuit.

[0002]

2. Description of the Related Art A conventional disk reproducing apparatus, for example, a CD
As shown in FIG. 5, a synchronization control circuit of a spindle motor for a CD / DVD disc in a (compact disc) / DVD (digital versatile disc) player includes an oscillating unit 1, a variable frequency divider 2, and a phase comparator (PD).
3, a lag / lead filter (LF) 4, an adder 5, a motor driver 6, and a three-phase motor 7 to form a phase-locked loop. The oscillating unit 1 oscillates a square wave crystal oscillation signal, and outputs a square wave of 10 Hz to 150 Hz to the PD 3 via the variable frequency divider 2 by externally adjusting the frequency division ratio. L
F4 allows the low-frequency component in the output of PD3 to pass, and adder 5 combines (adds) the output of LF4 and the output (variable DC voltage) of initial setting section 8 to generate motor driver 6 (the aforementioned CD).
/ DVD disk spindle motor driver). The three-phase motor 7 is driven by the output of the motor driver 6, combines and outputs a three-phase drive output waveform generated from the Hall element, and inputs the combined waveform to the PD 3.
The input / output relationship of the phase comparator 3 is shown in FIG. In FIG. 6, (A), (B), and (C) show the case where the output signal b of the three-phase motor 7 is in the leading, in-phase and lagging states with respect to the output a of the variable frequency divider 2, respectively. Variable frequency divider 2 in
FIG. 3 is an input / output timing chart showing an output a, an output signal b of the three-phase motor 7 and an output c of the PD 3.

[0003]

By the way, for example, a CD
In order to change the number of revolutions of the disk motor (that is, the three-phase motor 7) to switch from the reproduction to the DVD reproduction (or vice versa), for example, the setting of the initial setting unit 8 is changed to an appropriate DC voltage to control the motor driver 6. When the DC voltage is changed, as shown in FIG. 7, a change in the motor rotation speed (that is, the output of the Hall element) may not be able to catch up with a change in the control DC voltage.
7, (A) and (B) show the output of the variable frequency divider 2 with respect to the output a of the variable frequency divider 2 when the output signal b of the three-phase motor 7 is in the leading and lagging states, respectively. FIG. 3 is an input / output timing diagram showing an output a, an output signal b of a three-phase motor 7 and an output c of a PD 3.

[0004] In general, the relationship between the motor speed and the control DC voltage is expressed by the following equation. f (t) = F (v (t)) where f is the number of rotations of the motor, v is the control DC voltage, and t is the time. It should be noted that the above equation is a time function. The problem with FIG. 7 is that the time involved in the required change in the motor speed with the change in the control DC voltage is longer than the period T of the PD3 output. Using the above equation, the relationship between the motor rotation speed and time is shown in a graph as shown in FIG. The cause of the problem that occurred was t after the control DC voltage change.
At a point of time T (the above-described PD3 output cycle T), the motor revolution does not reach the required motor revolution f1 yet, so that the motor revolution cannot be changed within the cycle T of the PD3 output. It is recognized that. Table 1 shows the results of three experiments on the input / output relationship between the control DC voltage (volts (V)) and the motor rotation speed (hertz (Hz)... Represented by the output signal frequency generated from the Hall element).

[0005]

[Table 1]

[0006] As can be seen from Table 1, the result is that the motor rotation speed is almost doubled with respect to a slight change of the control DC voltage of 10 mV. Therefore, when the motor driver 6 and the three-phase motor 7 are regarded as a VCO (voltage controlled oscillator), the gain of the VCO is considered to be a considerably large value.

An object of the present invention is to provide a synchronous control circuit for a motor which solves the above-mentioned conventional problems.

[0008]

A motor synchronous control circuit according to the present invention is controlled by a control DC voltage based on a result of phase comparison between a reference frequency signal and a motor output frequency signal. A motor synchronous control circuit having a motor driver for driving the motor,
A phase difference detector to which the reference frequency signal and the output frequency signal of the motor are input, a pulse generator triggered by an output of the phase difference detector to generate a pulse signal, and a high-level output of the phase comparator. A high-level detector for detecting, a low-level detector for detecting a low-level output of the phase comparator, and a first synchronization pattern supplied with an output of a pulse generator and controlled by an output of the high-level detector. And a second switch circuit to which the output of the pulse generator is input and which is controlled by the output of the low-level detector and outputs a second synchronization pattern, And supplying a control DC voltage based on the synchronization pattern output of the second switch circuit to the motor driver.

According to a second aspect of the present invention, there is provided a motor synchronous control circuit which is controlled by a control DC voltage based on a phase comparison result between a reference frequency signal and an output frequency signal of the motor to drive the motor. A synchronous control circuit of a motor having a motor driver that performs a rise detection that detects a rise of the output of the phase comparator, and a fall detector that detects a fall of the output of the phase comparator. A pulse generator for generating a pulse signal triggered by outputs of the rising detector and the falling detector, a high level detector for detecting a high level output of the phase comparator, and a low level of the phase comparator. A low-level detector for detecting a level output; and an output of a pulse generator is supplied and controlled by the output of the high-level detector to output a first synchronization pattern. A first switch circuit, and a second switch circuit to which an output of a pulse generator is supplied and which is controlled by an output of the low level detector and outputs a second synchronization pattern, wherein the first and second switch circuits are provided. A control DC voltage based on a synchronous pattern output of a switch circuit is supplied to the motor driver.

According to a third aspect of the present invention, there is provided a motor synchronous control circuit for driving a motor controlled by a control DC voltage based on a phase comparison result between a reference frequency signal and a motor output frequency signal. A synchronous control circuit of a motor having a motor driver that performs a rise detection that detects a rise of the output of the phase comparator, and a fall detector that detects a fall of the output of the phase comparator. A first pulse generator triggered by an output of the rising detector to generate a pulse signal; a second pulse generator triggered by an output of the falling detector to generate a pulse signal; A high-level detector that detects a high-level output of the phase comparator, a low-level detector that detects a low-level output of the phase comparator, and an output of the first pulse generator. A first switch circuit which is supplied and controlled by an output of the high level detector to output a first synchronization pattern; and an output of the second pulse generator is supplied and provided by an output of the low level detector. Controlled second
And a second switch circuit for outputting a synchronous pattern of the control signal, and supplying a control DC voltage based on the synchronous pattern output of the first and second switch circuits to the motor driver.

[0011]

FIG. 1 is a block diagram showing an embodiment of a motor synchronization control circuit according to the present invention. In FIG. 1, in addition to the conventional configuration shown in FIG. 5, a phase difference detector (in this example, an exclusive OR (EXOR) gate is used) 9, a pulse generator (for example, a multivibrator) 10, a switch circuit 11 And 12, a high level detector 13, and a low level detector 14.

The operation principle of the above configuration will be described with reference to the timing chart of FIG. In FIG. 2, (A),
(B) and (C) show the output a of the variable frequency divider 2 respectively.
The output a of the variable frequency divider 2, the output signal b of the three-phase motor 7, the output c of the PD3, the output c of the PD3, and the EXOR gate 9 when the output signal b of the three-phase motor 7 is in the leading, in-phase, and lagging states. FIG. 4 is an input / output timing chart showing an output d of the pulse generator 10, an output e of the pulse generator 10, and outputs (ie, synchronization patterns) f and g of the switch circuits 11 and 12.

The high level of the output c of the PD 3 is the power supply voltage, the low level is GND (ground), and the other levels are high impedance between the power supply voltage and GND. If the characteristics of the PD3 output are used, high-level detection or low-level detection can be performed by using, for example, analog comparators as the high-level and low-level detectors 13 and 14.

The EXOR gate 9 outputs the output a of the variable frequency divider 2
And the output b of the three-phase motor 7 is input. If there is a phase difference between the two inputs, the output signal d is supplied to the pulse generator 10. The pulse generator 10 generates a pulse signal e having a predetermined width every time triggered by the output d of the EXOR gate 9.

The switch circuits 11 and 12 and the high-level and low-level detectors 13 and 14 are connected to the output c of the PD3.
To take out the respective synchronization pattern outputs f and g corresponding to The output of the high level detector 13 or the output of the low level detector 14 is controlled by controlling the respective switch circuits 11 and 12 so that the PD 3
Synchronization pattern outputs f and g corresponding to the output c of
Can be taken out.

To explain this in detail, first, FIG.
When the output signal b of the three-phase motor 7 is in the leading phase with respect to the output a of the variable frequency divider 2 as shown in FIG. The EXOR gate 9 detects the phase difference between the output a of the variable frequency divider 2 and the output signal b of the three-phase motor 7, and outputs an output d. The pulse generator 10 generates a pulse signal e each time triggered by the output d of the EXOR gate 9. The high level detection circuit 13
It is detected that the output c of PD3 is at a high level, and only while the output c of PD3 is at a high level,
The switch circuit 11 is controlled to be turned on to pass the pulse signal from the pulse generator 10 supplied to the switch circuit 11, and the switch circuit 11 outputs a synchronization pattern output f. On the other hand, the low level detector 14
Does not include a low level, no detection signal is output, the switch circuit 12 remains off, and the pulse signal from the pulse generator 10 is cut off.

Next, as shown in FIG. 2B, when the output signal b of the three-phase motor 7 is in the same phase as the output a of the variable frequency divider 2, the output c of the PD 3 becomes high level. An intermediate low level output is generated and the EXOR gate 9
Are the output a of the variable frequency divider 2 and the output signal b of the three-phase motor 7
No output is generated because there is no phase difference between them. Therefore,
The pulse generator 10 does not generate a pulse signal, and the outputs of the switch circuits 11 and 12 disappear.

Next, when the output signal b of the three-phase motor 7 is in a delayed state with respect to the output a of the variable frequency divider 2 as shown in FIG. An output c is generated. The EXOR gate 9 detects the phase difference between the output a of the variable frequency divider 2 and the output signal b of the three-phase motor 7, and outputs an output d. The pulse generator 10 generates a pulse signal e each time triggered by the output d of the EXOR gate 9. The low-level detection circuit 14 detects that the output c of the PD 3 is at a low level, and controls the switch circuit 12 to be turned on only while the output c of the PD 3 is at a low level. The pulse signal from the pulse generator 10 supplied to the circuit 12 is passed, and the switch circuit 12 outputs a synchronization pattern output g. On the other hand, the high level detector 13 does not output a detection signal because the output c of the PD 3 does not include a high level, and the switch circuit 1
1 remains off, and the pulse signal from the pulse generator 10 is cut off.

The synchronizing pattern outputs f and g are extracted as described above, and the features are as follows. That is, regarding the synchronous pattern outputs f and g, the maximum pulse width of these outputs is the pulse width generated from the pulse generator 10 (the pulse output width of the multivibrator in this example).
Determined by Also, synchronous pattern outputs f and g
With respect to the pulse width of these outputs,
And the pulse width of the PD3 output. The output levels of the synchronous pattern outputs f and g are turned on / off by the pulse generated from the pulse generator 10 and the pulse of the PD3 output. With respect to the above features, in particular, the present invention relates to CD / D
It is recognized as an indispensable element when implemented in the motor control system for VD disks.

As described above, the synchronous pattern output f and the synchronous pattern output g are taken out in accordance with the PD3 output c, and the control DC voltage created based on these synchronous pattern outputs is directly (the synchronous pattern output f
Is a positive value and the control DC voltage based on the synchronization pattern output g is a negative value.)
This is given to the motor driver 6.

Thus, for example, in order to change the number of revolutions of the disk motor (ie, the three-phase motor 7) for switching from CD reproduction to DVD reproduction (or vice versa), for example, the setting of the initial setting unit 8 is set to an appropriate DC voltage. When the control DC voltage of the motor driver 6 is changed by the change, the synchronization pattern output f shown in FIG.
Alternatively, since the synchronous pattern output g is supplied to the motor driver 6, the rotation speed of the three-phase motor 7 is driven so as to quickly reach the target rotation speed. A series of operations are performed within the capture range, and after the rotation speed of the three-phase motor 7 reaches the target rotation speed (ie, is synchronized), FIG.
As shown in (B), the synchronous pattern outputs f and g are not generated, so that the phase locked loop is not affected.

[0022]

FIG. 3 is a block diagram showing another embodiment of the motor synchronization control circuit according to the present invention. In FIG.
Instead of the EXOR gate 9 in the configuration shown in FIG.
5 and a falling detector 16 are used, their inputs are connected to the output of PD 3 and their outputs are connected to the pulse generator 10. That is, in the configuration of FIG. 1, the portion for extracting the synchronization pattern output depends on both the input and output of the PD 3, but in the configuration of FIG. 3, it only depends on the output of the PD 3. 3, based on only the output c of PD3, the rising detector 15 outputs the output c of PD3 (FIG. 2).
(A)) detects a rise and generates a detection output, and a fall detector 16 detects a fall of the output c (FIG. 2 (C)) of the PD 3 and generates a detection output to generate a pulse output. Supply 10 The pulse generator 10 generates a pulse output e each time triggered by the detection output of the rising detector 15 and the falling detector 16. (The other operations are the same as those in FIG. 1, and a detailed description thereof will be omitted.)

FIG. 4 is a block diagram showing still another embodiment of the motor synchronization control circuit according to the present invention. FIG. 4 shows a configuration in which two pulse generators 17 and 18 are used instead of the pulse generator 10 in the configuration shown in FIG. The pulse generator 17 controls the pulse output generated by the output of the rising detector 15 (FIG. 2).
The pulse output e) of (A) is supplied to the switch circuit 11,
The pulse generator 18 supplies a pulse output (pulse output e in FIG. 2C) generated by being controlled by the output of the falling detector 16 to the switch circuit 12. (The other operations are the same as those in FIG. 3, and a detailed description thereof will be omitted.)

Although the embodiment of the present invention has been described above, the present invention is useful for a synchronous control system of a motor for a CD / DVD disk, but is not limited to this and can be applied to a synchronous control of another motor. It is.

[0025]

According to the present invention, it is possible to obtain a synchronous control circuit which is effective when the number of rotations of the motor is changed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a motor synchronization control circuit according to the present invention.

2 (A), (B) and (C) respectively show FIG.
FIG. 10 is an input / output timing diagram of each unit when the output signal of the three-phase motor 7 is in a leading, in-phase, and lagging state with respect to the output of the variable frequency divider in the block diagram of FIG.

FIG. 3 is a block diagram showing another embodiment of the motor synchronization control circuit according to the present invention.

FIG. 4 is a block diagram showing another embodiment of the motor synchronization control circuit according to the present invention.

FIG. 5 is a block diagram showing an example of a conventional motor synchronization control circuit.

6 (A), (B) and (C) respectively show FIG.
FIG. 7 is an input / output timing diagram of each unit when the output signal of the three-phase motor is in a leading, in-phase, and lagging state with respect to the output of the variable frequency divider in the block diagram of FIG.

FIGS. 7A and 7B are diagrams of respective parts when the output signal of the three-phase motor 7 is in the leading and lagging states with respect to the output of the variable frequency divider 2 in the block diagram of FIG. It is an input / output timing diagram.

FIG. 8 is a graph illustrating a transient phenomenon of the three-phase motor in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Oscillator 2 Variable frequency divider 3 Phase comparator (PD) 4 Lag lead filter (LF) 5 Adder 6 Motor driver 7 Three-phase motor 8 Initial setting part 9 Phase difference detector 10 Pulse generator 11 Switch circuit 12 Switch circuit 13 High level detector 14 Low level detector 15 Rise detector 16 Fall detector 17 Pulse generator 18 Pulse generator

Claims (3)

[Claims] 1. A synchronous control circuit for a motor, comprising: a motor driver for driving a motor controlled by a control DC voltage based on a phase comparison result between a reference frequency signal and an output frequency signal of the motor; And a phase difference detector to which an output frequency signal of the motor is input, a pulse generator triggered by an output of the phase difference detector to generate a pulse signal, and a high level for detecting a high level output of the phase comparator A detector, a low-level detector for detecting a low-level output of the phase comparator, and a second for receiving a pulse generator output and controlling the output of the high-level detector to output a first synchronization pattern. 1 switch circuit and a second switch that receives the output of the pulse generator and outputs a second synchronization pattern controlled by the output of the low level detector. And a first circuit and a second circuit.
A control DC voltage based on a synchronous pattern output of the switch circuit of (c) is supplied to the motor driver. 2. A synchronous control circuit for a motor, comprising: a motor driver for driving a motor controlled by a control DC voltage based on a result of a phase comparison between a reference frequency signal and an output frequency signal of the motor, wherein the phase comparator A rise detector for detecting the rise of the output of the phase comparator; a fall detector for detecting the fall of the output of the phase comparator; and a pulse signal triggered by the outputs of the rise detector and the fall detector. , A high-level detector that detects a high-level output of the phase comparator, a low-level detector that detects a low-level output of the phase comparator, and an output of the pulse generator. A first switch circuit controlled by an output of the high-level detector to output a first synchronization pattern; an output of a pulse generator supplied to the first switch circuit; A second switch circuit that is controlled by an output of the first detector and outputs a second synchronization pattern.
A synchronous control circuit for a motor, wherein a control DC voltage based on a synchronous pattern output of the first and second switch circuits is supplied to the motor driver. 3. A synchronous control circuit for a motor, comprising: a motor driver for driving a motor controlled by a control DC voltage based on a phase comparison result between a reference frequency signal and an output frequency signal of the motor, wherein the phase comparator A rise detector for detecting a rise of the output of the phase comparator, a fall detector for detecting a fall of the output of the phase comparator, and a first detector for generating a pulse signal triggered by the output of the rise detector A pulse generator that is triggered by an output of the falling detector to generate a pulse signal; a high-level detector that detects a high-level output of the phase comparator; A low-level detector for detecting a low-level output of the first pulse generator; and a first synchronous pattern supplied with the output of the first pulse generator and controlled by the output of the high-level detector. And a second switch circuit to which an output of the second pulse generator is supplied and which is controlled by an output of the low level detector and outputs a second synchronization pattern. A synchronous DC control circuit for supplying a control DC voltage to the motor driver based on a synchronous pattern output of the first and second switch circuits.