JPH11276700A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of effectively defending an attack from an illegal substrate to play. SOLUTION: Concerning this game machine, the output of an oscillation circuit 68 for generating a clock signal at a frequency different from that of a reset pulse from a cyclic reset circuit 66 is inputted to the interruption terminal of a CPU 56 for executing a play control program. In interrupting processing, the CPU 56 outputs data to the outside of a play control substrate on which the CPU 56 is loaded. Therefore, the internal operating frequency of the CPU 56 and a data output frequency are made asynchronous and even when the data output is observed, it is impossible to know the internal operating frequency of the CPU 56.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine, and more particularly to a game machine in which a game medium is shot by a player's operation and the game medium wins a prize area provided in the game area. A predetermined value is given to the player, and a special game is performed by the entry of the game medium into the specific winning section, and the predetermined game value is given to the player based on the result of the special game being in a predetermined mode. The present invention relates to a gaming machine that can be provided.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

The variable display section has a plurality of display areas, and is usually configured to display a plurality of variable display results at different times. In the variable display unit, for example,
A plurality of identification information such as symbols are variably displayed. The fact that the display result of the variable display unit is a combination of predetermined specific display modes is usually referred to as “big hit”. In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate. When a "big hit" occurs, for example, a large amount of prize balls and the like are paid out to the player.

In game control of such a gaming machine, a random number is generated when a predetermined condition (for example, a start winning which is a condition for starting a variable display) is satisfied, and when a random number value matches a predetermined value determined in advance. "Big hit". Further, a circuit portion for performing game control for noise suppression or the like is reset and activated at predetermined time intervals. Since the generation of the random number value is performed in the circuit portion that performs the game control, it must be synchronized with the time interval of activation of the circuit portion that performs the game control.

[0005] Then, if the time interval of activation is detected by some means, the timing of random number generation is recognized. Further, the timing at which a random number value of "big hit" occurs is recognized. Then, by aiming for the start winning at the timing when the random number value of “big hit” is generated, it is possible to frequently generate “big hit”.

[0006] In order to detect the activation timing of a circuit portion for performing game control, an illegal board may be attached to a game machine. Such illegal board introduces a signal output from the circuit part that controls the game to the outside, detects the start timing of the circuit part that performs the game control based on the signal, and generates a random number value that becomes a "big hit" The timing to perform is detected. Then, the illegal board can send a start winning signal to a circuit portion that performs game control at that timing, thereby making it possible to illegally generate a "big hit".

[0007]

Since various components such as a variable display device, a decorative lamp, and a sound generating device are present in a gaming machine, a signal line from a circuit portion for performing game control to those components is eliminated. Can not. Accordingly, there is still room for the illegal board to be attached and illegal gaming to be performed. Therefore, how to prevent illegal gaming using illegal substrates has become an important issue in gaming machines.

[0008] Therefore, an object of the present invention is to provide a gaming machine capable of effectively preventing an attack on a game by an unauthorized board.

[0009]

A gaming machine according to the present invention comprises:
Perform special games by entering game media into the special prize section,
A game machine capable of giving a predetermined game value to a player based on a result of a special game having a predetermined mode, wherein game control means including a game control program for controlling progress of a game is mounted. And a desynchronizer for making the internal operating frequency of the game control means different from the output frequency of data output from the game control board. In the gaming machine, the game control means includes a CPU,
The non-synchronization unit may include an oscillation circuit that generates a signal having a frequency different from the internal operation frequency of the game control unit, and a CPU interrupt process that operates based on a signal from the oscillation circuit. . Further, in the gaming machine, the desynchronizing means outputs an oscillation circuit for generating a signal having a frequency different from the internal operating frequency of the game control means, and output data from the game control means in synchronization with a signal from the oscillation circuit. An output circuit may be included.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as viewed from the front. Here, a pachinko gaming machine is shown as an example of a gaming machine. However, the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine or the like. Is performed, and based on the fact that the result of the special game has become a predetermined mode, the present invention can be applied to all gaming machines in which a predetermined game value can be given to a player.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display device 8 including an image display section 9 for displaying game contents and a variable display 10 using 7-segment LEDs is provided. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. A gate sensor 1 that detects a hit ball that has passed through the passage gate 11 is provided in a passage between the passage gate 11 and the ball exit 13.
There are two. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6 and detected by the starting port sensor 17.

Below the starting winning port 14, a variable winning ball device 15 for opening and closing is provided. The variable winning ball device 15 is opened by the solenoid 16. An opening / closing plate 20 that is opened by the solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball device 15. A winning ball that has entered one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count sensor 22. The winning ball from the opening / closing plate 20 is detected by the count sensor 23. At the lower portion of the variable display device 8, a starting winning storage display 18 having four display sections for displaying the number of winning balls entering the starting winning port 14 is provided. In this example, each time there is a starting prize, the starting prize storage display 1
Numeral 8 increases the number of lit display units one by one. Then, every time the variable display of the image display unit 9 is started, the number of the lit display units is reduced by one.

The game board 6 is provided with a plurality of winning ports 19 and 24. Decorative lamps 25 are provided around the left and right sides of the game area 7 so as to blink during the game.
There is an out port 26 for absorbing a hit ball that does not win. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. On the outer periphery of the game area 7, a game effect lamp / LED 28 is provided. In this example, a prize ball lamp 51 that is turned on when a prize ball is paid out is provided in the vicinity of one of the speakers 27, and a ball out lamp 52 that is turned on when a replenishment ball is out in the vicinity of the other speaker 27. Is provided. Furthermore, in FIG. 1, it is installed adjacent to the pachinko gaming table 1,
Also shown is a card unit 50 that enables lending of balls by inserting a prepaid card.

A hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball passes through the passage gate 11 and is detected by the gate sensor 12, the number displayed on the variable display 10 changes to a continuously changing state. When the hit ball enters the starting winning opening 14 and is detected by the starting opening sensor 17, a predetermined variable display image is displayed in the image display section 9 if the variable display can be started. If the variable display cannot be started, the start winning memory is increased by one. The start winning memory will be described later in detail. The variable display in the image display unit 9 ends when a certain time has elapsed or when a predetermined condition is satisfied. If the condition is satisfied, the game shifts to the big hit game state. That is, the opening and closing plate 20
Is released until a predetermined time (for example, 29.5 seconds) elapses or until a predetermined number (for example, 10) of hit balls is won. When a hit ball wins in the specific winning area while the opening and closing plate 20 is being opened and is detected by the V count sensor 22, a continuation right is generated and the opening and closing plate 20 is opened again. The generation of the continuation right is permitted a predetermined number of times (for example, 16 rounds).

When the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits and becomes a symbol is increased.

Embodiment 1 FIG. 2 is a block diagram showing an example of a circuit configuration of the game control board (main board) 31. FIG. 2 shows the prize ball substrate 37 and the illuminated substrate 3
5 and the display control board 80 are also shown. The main board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 in accordance with a game control program, and a switch circuit for supplying signals from the gate sensor 12, the starting port sensor 17, the V count sensor 22, and the count sensor 23 to the basic circuit 53. And a solenoid 1 for opening and closing the variable winning ball device 15
6 and a solenoid circuit 59 for driving a solenoid 21 for opening and closing the opening / closing plate 20 in accordance with a command from the basic circuit 53
To turn on and off the start storage display 18 and to drive the variable display 10 using 7-segment LEDs,
Further, a lamp / LED circuit 60 for blinking the decorative lamp 25 and a prize sphere board which transmits a command from the basic circuit 53 to the prize sphere board 37 and inputs a winning data signal from the prize sphere board 37 to the basic circuit 53. An output circuit 61, an illuminated board command output circuit 62 for transmitting a command from the basic circuit 53 to the illuminated board 35, and a command or strobe from the basic circuit 53 to a display control board 80 for controlling the image display unit 9 by CRT. Display circuit 63 for providing signals
Big hit information indicating occurrence of a big hit according to data provided from the basic circuit 53, valid starting information indicating the number of start winning balls used to start image display on the image display unit 9,
An information output circuit 64 that outputs probability change information or the like indicating that a probability change has occurred to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation in accordance with the control program, and an I / O port unit 57. The ROM 54 and the RAM 55 may be built in the CPU 56 in some cases.

Further, the main board 31 is provided with an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on, and a reset pulse is provided to the basic circuit 53 periodically (for example, every 2 ms) to control the game. A periodic reset circuit 66 for executing the program again from the beginning;
An address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57 is provided.

FIG. 3 is a block diagram showing a main part of a peripheral circuit of the CPU 56. As shown in the figure, the output of the initial reset circuit 65 for giving a reset pulse to the CPU 56 when the power is turned on and the output of the periodic reset circuit 66 for giving a reset pulse to the CPU 56 every 2 ms are N
The signal is supplied to a reset terminal of the CPU 56 via an AND gate 69. Therefore, in this embodiment, the CPU 56
Is restarted every 2 ms. Further, a clock signal from the oscillation circuit 68 is input to an interrupt terminal of the CPU 56.

Here, the oscillation circuit 68 outputs a clock signal having a frequency based on the oscillation of the crystal oscillator. Note that a capacitor, a resistor, and a gate circuit for stabilizing oscillation are connected outside the crystal resonator. In addition, the oscillation cycle of the oscillation circuit 68 is set to a different value from the reset cycle of 2 ms. In this embodiment, the oscillation cycle is 1.89 m.
s. However, this value is merely an example, and the oscillation cycle may be another value as long as it does not coincide with 2 ms.

FIG. 4 is a block diagram showing a circuit configuration in the display control board 80 together with a CRT 82 for realizing the image display section 9. The display control board 80 is provided with a display control circuit 81 for controlling image display on the CRT 82. Further, a reset circuit 83 for resetting the display control circuit 81 is provided on the display control board 80.
An oscillation circuit 84 for supplying a clock signal to the display control circuit 81, a character ROM 86 for storing data representing a frequently used image, a VRAM 87 for storing image data generated by the display control circuit 81,
And a frame memory circuit 88 in which image data for one screen is set. The image data in the frame memory circuit 88 is converted into a video signal composed of an RGB color signal and a SYNC signal in synchronism with a predetermined synchronization signal.
And an image is displayed on the CRT 82. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, graphics, or symbols displayed on the CRT 82.

When the strobe signal is input from the display device circuit 63 of the main board 31, the display control circuit 81 inputs the display control command data from the display device circuit 63 and recognizes the state indicated by the command data. The display control circuit 81 generates image data to be displayed on the CRT 82 according to the state of the command data. Then, the image data is stored in the VRAM 87.

FIG. 5 is a block diagram showing an example of the configuration of the display control circuit 81. The CRT control circuit 81 includes a display control CPU 91, a VDP 93, and a control data ROM 92 in which control data is stored. The display control CPU 91 controls the character ROM 8 according to the display control command data from the display device circuit 63.
6 is read out as necessary data. And the display control C
The PU 91 outputs the read data to the VDP 93. The VDP 93 outputs the CRT 82 according to the input data.
, And stores the image data in the VRAM 87. Then, the image data in the VRAM 87 is transferred to the frame memory circuit 88.
Although not shown in FIG. 5, a CRT is provided between the display control board 80 and the CRT 82 based on a video signal.
A CRT substrate having a CRT driving circuit for driving the CRT 82 is provided.

FIG. 6 is a timing chart showing transmission timing of display control command data given from the main board 31 to the game control board 80. As will be described later in detail, in this embodiment, each piece of display control data constituting the display control command data is sent out by an interrupt process started every 1.89 ms. However, if two interrupts occur within 2 ms from when the CPU 56 is activated to when it is restarted, the data transmission process is executed only once. Then, a strobe signal is output in synchronization with each display control data. Since the display control CPU 91 receives an IRQ2 interrupt at the rising edge of the strobe signal as shown in FIG. 5, the display control CPU 91 can fetch each display control data by an interrupt processing program.

Next, the operation will be described. FIG. 7 is a flowchart showing the main operation of the basic circuit 53 on the main board 31. As described above, this processing is performed by the reset pulse generated by the periodic reset circuit 66.
It is activated every 2 ms. When the basic circuit 53 is activated,
First, the basic circuit 53 performs a stack setting process for setting a designated address of a stack pointer (step S1). Next, initialization processing is performed (step S
2). In the initialization processing, the basic circuit 53 determines whether or not the RAM 55 contains an error. If the error is included, the basic circuit 53 performs processing such as initializing the RAM 55.
Then, a 2 ms flag indicating activation is set (step S2a).

Further, processing for setting display control data sent to the display control board 80 in a predetermined area of the RAM 55 is performed (step S3). In addition, while performing processing for transmitting a predetermined command for sound generation and LED lighting control to the illuminated board 35 via the illuminated board command output circuit 62, various lamps and lights are transmitted via the lamp / LED circuit 60.
Perform processing for turning on / off the LED (step S
4). Further, a process for transmitting data such as big hit information, start information, and probability variation information to the hall management computer via the information output circuit 64 is performed (output data setting process: step S5). Specifically, the CPU 56
In step S5, output data is set in a predetermined RAM area. The contents of the RAM area are output via the I / O port 57 by an interrupt process described later.

Next, various abnormality diagnosis processes are performed by a self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S6).

Next, a process of updating each counter indicating each determination random number (such as a random number for determining whether or not to make a jackpot) is performed (step S7). Next, the basic circuit 53
Performs a special symbol process (step S8). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S9). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Further, the basic circuit 53 inputs the state of each sensor via the switch circuit 58 (Step S10). The basic circuit 53 is
Further, a process of updating the display random numbers (random numbers for determining a lost symbol or a reach type) is performed (step S11).

The basic circuit 53 performs signal processing with the award ball substrate 37 (step S12). That is, it is determined whether or not a winning data signal is output from the prize ball substrate 37, and when a predetermined condition is satisfied, the prize ball substrate 3
7 to output a prize ball number signal. The payout control microcomputer mounted on the prize ball board 37 drives the ball payout device 97 according to the prize ball number signal. Thereafter, the basic circuit 53 repeats the display random number updating process in step S13 until the next reset pulse is given from the periodic reset circuit 66.

In the special symbol process processing, it is determined whether the display mode of the symbol change based on the winning start is a jackpot, a reach mode, or a loss mode, and a combination of the respective stop symbols is determined. Then, information indicating the determined symbol and a command for instructing all symbol changes are transmitted from the basic circuit 53 of the main substrate 31 to the display control substrate 80 as display control command data. The basic circuit 53 may transmit only the information indicating the combination of the stopped symbols to the display control board 80, or may transmit the display control command data indicating the instantaneous symbol variation to the display control board 80. Good.

FIG. 8 is a flowchart showing the interrupt processing. This processing is executed every 1.89 ms as described above. When an interrupt occurs, the CPU 56
It is checked whether the ms flag is set (step S2b). If it is set, the 2 ms flag is reset (step S2c), and step S4
The processing of S5a is executed. Does nothing if not set. As described above, since the process is executed only when the 2 ms flag is set, a plurality of interrupt processes are not executed during one main operation of the basic circuit 53. When the interrupt processing is executed a plurality of times, data set in one main operation may be output to the peripheral board (a board other than the main board 31) a plurality of times, causing inconsistency.

In the interruption process, the CPU 56 transmits display control command data to the display control board 80 (step S4). The display control command data is stored in a predetermined RAM area by the process of step S3.

Further, the CPU 56 controls the illuminated board 35 via the illuminated board command output circuit 62 to generate a sound or an LED.
A predetermined command for lighting control is transmitted, and data such as big hit information, start information, and probability variation information are transmitted to the hall management computer via the information output circuit 64 (step S5a). The lamp / LED circuit 60
The various lamps / LEDs are turned on / off via. In addition,
Lamp / LED circuit 60, illumination board command output circuit 6
2 and the data output to the information output circuit 64 have been set in a predetermined RAM area in the processing of step S5, and in the processing of step S5a, the R
The data is taken out from the AM area and the I / O port 57
Output via. The lamp / LED circuit 60, the illuminated board command output circuit 62 and the information output circuit 64
Is composed of, for example, a pull-up resistor provided between the I / O port 57 and the data output connector.

FIG. 9 is a flowchart showing an operation example of the display control data output process (step S4) executed in the interrupt process. In the display control data output process, the CP
U56 first checks whether or not the data sending flag is set (step S411). If not set, it is confirmed whether or not the transmission request flag of the display control command data is set (step S41).
2). If the transmission request flag has been set, the transmission request flag is reset (step S413). Further, the data sending flag is set and the pointer is cleared (step S414). The pointer indicates which byte in the display control command data storage area is to be transmitted. Here, it is assumed that the display control command data is composed of 8-byte display control data.

If the data sending flag is set, the data indicated by the pointer in the display control command data storage area is output to the display control board 80 via the output port and the display device circuit 63 ( Step S415). The display device circuit 63 includes:
For example, it is a circuit portion that pulls up output data to a power supply to secure an output current amount. Further, the CPU 56 turns on the strobe signal (step S416).
After a wait period of 500 μs (step S417), the strobe signal is turned off (step S418).

Next, the CPU 56 sets the value of the pointer to +
1 (step S419). Then, when the value of the pointer becomes 8, it means that transmission of all 8-byte display control command data has been completed, and the data transmission flag is reset (steps S420 and S42).
1). With the above processing, the display control command data is transmitted one byte at a time by the interrupt processing.

As described above, the display control command data transmitted from the main board 31 to the display control board 80 is sent out by the interruption processing. In this embodiment, the interrupt processing is executed at 1.89 ms intervals. The CPU 56 is activated at 2 ms intervals and performs the main operation.
6 is 500 Hz. on the other hand,
The data output frequency is (1 / 1.89 ms) Hz, which is asynchronous with the internal operating frequency. Then, even if the display control command data output from the main board 31 is observed, the internal operating frequency of the CPU 56 cannot be predicted. Therefore, it is not possible to recognize the generation timing of the random number for generating the big hit based on the display control command data.

In this embodiment, if two interrupts occur during one 2 ms operation of the CPU 56 as in the example shown in FIG. 6, no data is transmitted in the second interrupt. . Then, the display control data may be transferred in (1.89 × 2) ms, but there is no practical problem because it is related to display.

Each data output from the main board 31 via the lamp / LED circuit 60, the illuminated board command output circuit 62 and the information output circuit 64 is also output by an interrupt process executed every 1.89 ms. I was Therefore, their data output frequencies are also asynchronous with the internal operating frequency of the CPU 56. Therefore, even if the output data output from the main board 31 is observed, the CPU 5
6 cannot be known.

Further, in this embodiment, the main substrate 3
The prize ball number signal transmitted from 1 to the prize ball substrate 37 is 2 ms.
The main operation is performed every time. However, if the difference between the interruption intervals of 2 ms is acceptable as the prize ball payout delay time, the prize ball number signal may also be output in the interrupt processing. Good. In this embodiment, the drive signals for the solenoids 16 and 21 output via the solenoid circuit 59 are output, for example, in a special symbol processing process. The drive signal for the solenoids 16 and 21 may also be output in the interrupt process if the delay time for opening the special winning opening can be tolerated.

Embodiment 2 In the example shown in FIG. 3, the oscillation circuit 68 oscillated the interrupt signal based on the oscillation of the crystal oscillator. That is, oscillation is performed in a state where the frequency is relatively stable. However, it is preferable that the intervals between the generations of the interrupt signal vary within a range where the operation of the gaming machine does not become unstable. Then, when the output signal from the main board 31 is observed outside the main board 31, the data output timing further varies, and the difficulty of predicting the internal operating frequency of the CPU 56 further increases.

FIG. 10 shows an example in which an oscillating circuit 68a for generating an interrupt signal by a CR oscillating circuit using a resistor or a capacitor which is more susceptible to the influence of temperature or the like than a crystal oscillator is formed. According to such an oscillation circuit 68a, as compared with the case where a crystal oscillator is used, when the internal temperature or the like of the gaming machine fluctuates, the oscillation frequency fluctuates accordingly. Therefore,
The data output timing from the main board 31 fluctuates, and it becomes more difficult to recognize the generation timing of a random number that generates a big hit. Note that the operation of the gaming machine is the same as in the first embodiment.

Embodiment 3 FIG. In the first and second embodiments, the internal operating frequency of the CPU 56 and the data output frequency are shifted by the interrupt processing. However, the internal operating frequency and the data output frequency may be shifted without the interrupt processing. it can. FIG. 11 is a block diagram showing an example of a circuit configuration capable of shifting the internal operating frequency and the data output frequency without depending on the interrupt processing.

The lamp / LED circuit 60 shown in FIG.
A signal output from the CPU 56 to the outside of the main board 31 via the illumination board command output circuit 62, the display device circuit 63, and the information output circuit 64 is output via the I / O port 57. Therefore, as shown in FIG.
A D latch circuit 5 is connected to the output of the output port of the / O port 57.
71 to 578 are connected. Then, each D latch circuit 57
The oscillation output of the oscillation circuit 68 is connected to the clock inputs 1 to 578. Here, the oscillation cycle of the oscillation circuit 68 is, for example, 385 μs, but this value is also merely an example. Note that FIG. 11 shows only the D latch circuits 571 to 578. However, since the number of output ports is more than eight in a game machine, more D latch circuits are actually provided. In FIG. 11, only the data bus is shown, and the address bus is omitted.

FIG. 12 is a flowchart showing the main operation of the basic circuit 53 on the main board 31 in this embodiment. In the first and second embodiments, the display control data output processing and the data output processing are performed by interrupt processing. However, as shown in FIG. Executed in
Therefore, as shown in FIGS.
6, display control data and a strobe signal are output from the I / O port 57 based on the internal operation frequency of 2 ms.

However, the output data from I / O port 57 is 385 μm by D latch circuits 571 to 578.
It is latched and output at the falling edge of the s clock signal (see FIGS. 13C, 13D and 13E). Then, the output frequency of the display control data from the main board 31 is substantially (1/385 μs) Hz, and does not match the internal operating frequency of the CPU 56. Therefore, the main board 3
Even if the display control command data output from 1 is observed, the internal operating frequency of the CPU 56 cannot be predicted, and the generation timing of the random number for generating the big hit cannot be recognized based on the display control command data.

Since the strobe signal is also latched by the 385 μs clock signal, the width of the strobe signal output from the D latch circuit may be 385 μs or (385 × 2) depending on the timing relationship between the clock signal and the strobe signal. ) Μs (FIG. 13)
(E)). However, the display control CPU 91 of the display control board 80 can sufficiently recognize the strobe signal of 385 μs or the strobe signal of (385 × 2) μs.
The display control CPU 91 can fetch the display control data without any practical problem (see FIG. 13F).

Each data output from the main board 31 via the lamp / LED circuit 60, the illuminated board command output circuit 62 and the information output circuit 64 is also output via the D latch circuit. Can be. In that case, those data output frequencies are also asynchronous with the internal operating frequency in the CPU 56. Therefore, even if the output data output from the main board 31 is observed, the internal operating frequency of the CPU 56 cannot be known.

Further, the prize ball substrate 37 from the main substrate 31
2ms and 385
If the deviation from the clock signal at the interval of μs can be tolerated as the winning ball payout delay time, a D latch circuit may be provided on the output side of the I / O port 57 for outputting the winning ball number signal. The maximum shift amount is 385 μs when the period of the clock signal is 385 μs.
As for the drive signals for 6,21, 2ms and 385
If the amount of deviation from the clock signal at the interval of μs can be tolerated as a delay time with respect to the opening of the winning opening and the opening of the winning opening, the I / O port 5 that outputs the solenoids 16 and 21
7, a D latch circuit may be provided on the output side.

In this embodiment, since the internal operating frequency and the data output frequency are shifted without depending on the interrupt processing, the interrupt processing has already been used as another processing.
This is useful when interrupt processing cannot be used for some reason. In this embodiment, the D latch circuits 571 to 578 are used as output circuits for outputting output data from the CPU 56 in synchronization with a signal from the oscillation circuit 68a, but the output circuit is limited to the D latch circuit. I can't.

As shown in the first to third embodiments, according to the present invention, the internal operating frequency of the CPU 56,
Since the output frequency of the data output from the main board 31 to the outside is asynchronous, even if the data output from the main board 31 is observed by an unauthorized board, the CPU
The internal operating frequency of 56 cannot be predicted. Therefore, even when an illegal board is attached, the timing of generating a random number that generates a big hit cannot be recognized, and an attack on the gaming machine by the illegal board can be reliably prevented.

The configuration of the peripheral board shown in FIG. 2 is an example, and various peripheral board configurations can be adopted in a gaming machine. Regardless of the configuration method, the present invention can be applied to data output from the main board 31 to each peripheral board.

The gaming machine of each of the above-described embodiments, that is, the pachinko gaming machine shown in the front view of FIG. 1, has a special symbol that is variably displayed on the image display section 9 based on a winning start. Although it was a first-class pachinko gaming machine in which a predetermined game value could be given to a player when a predetermined combination of symbols was reached, a predetermined area was determined when an electric accessory that was opened based on a start winning prize entered a predetermined area. Winning a second-class pachinko gaming machine that allows a player to give a game value to a player, and a predetermined electric role that is opened when a stop symbol of a symbol variably displayed based on a winning start becomes a predetermined symbol combination. The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a certain right.

In each of the above embodiments, the image display unit 9 using a CRT for variably displaying a plurality of types of symbols is provided.
Although the description has been given of the case of using a variable display device, a case where a variable display device using an LCD may be used. Furthermore, the present invention can be applied to a video-type pachinko gaming machine in which the entire board surface is composed of video.

[0056]

As described above, according to the present invention, a gaming machine is provided with a desynchronizer for making the internal operating frequency of the game controller different from the output frequency of data output from the game controller. Therefore, even if the illegal board observes the data output from the game control board, it cannot predict the internal operating frequency of the game control means. Therefore, even if an illegal board is attached, it is not possible to illegally send a start winning signal to the game control means aiming at the timing of generating a random number that generates a big hit, and it is possible to reliably prevent illegal acts by the illegal board. In the case where the desynchronizing means is constituted by an oscillating circuit for generating a signal having a frequency different from the internal operating frequency of the game control means, and a CPU interrupt processing which operates based on a signal from the oscillating circuit, The internal operating frequency of the game control means and the output frequency of the data output from the game control board can be made different without adding components to the control board. In addition, the desynchronizing means has an oscillation circuit for generating a signal having a frequency different from the internal operating frequency of the game control means, and an output circuit for outputting output data from the game control means in synchronization with a signal from the oscillation circuit. If it is composed of
Even when the interruption of U is not used, the internal operating frequency of the game control means and the output frequency of the data output from the game control board can be made different.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a block diagram showing an example of a circuit configuration of a game control board and a peripheral board.

FIG. 3 is a block diagram showing a main part of a peripheral circuit of the CPU.

FIG. 4 is a block diagram showing a circuit configuration in a display control board.

FIG. 5 is a block diagram illustrating an example of a configuration of a display control circuit.

FIG. 6 is a timing chart showing transmission timing of display control command data.

FIG. 7 is a flowchart showing the operation of the basic circuit on the main board.

FIG. 8 is a flowchart illustrating an interrupt process.

FIG. 9 is a flowchart illustrating an operation example of display control data output processing.

FIG. 10 is a block diagram illustrating a main part of a peripheral circuit of a CPU according to a second embodiment.

FIG. 11 is a block diagram illustrating a main part of a peripheral circuit of a CPU according to a third embodiment.

FIG. 12 is a flowchart showing the operation of the basic circuit according to the third embodiment.

FIG. 13 is a timing chart showing transmission timing of display control command data according to the third embodiment.

[Explanation of symbols]

 8 Variable display device 9 Image display unit 31 Game control board 35 Illuminated board 37 Winning ball board 70 Lamp board 53 Basic circuit 54 ROM 56 CPU 65 Initial reset circuit 66 Periodic reset circuit 68, 68a Oscillation circuit 80 Display control board 91 Display control CPU

Claims (3)

[Claims] 1. A gaming machine in which a special game is performed by entering a game medium into a specific winning section, and a predetermined game value can be given to a player based on a result of the special game becoming a predetermined mode. A game control board equipped with a game control means including a game control program for controlling the progress of the game, wherein the internal operation frequency of the game control means and the output frequency of data output from the game control board A gaming machine characterized by having a differentiating means. 2. The game control means includes a CPU, the desynchronization means includes an oscillation circuit for generating a signal having a frequency different from an internal operating frequency of the game control means, and the non-synchronization means operating based on a signal from the oscillation circuit. The gaming machine according to claim 1, further comprising an interrupt process of a CPU. 3. An asynchronous circuit for generating a signal having a frequency different from an internal operating frequency of the game control means, and outputting output data from the game control means in synchronization with a signal from the oscillation circuit. And an output circuit.
The gaming machine described.