JPH11284199A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device utilizing a semiconductor thin film having a high crystallinity by the manufacturing method with high mass- producibility. SOLUTION: When an amorphous silicon film 106 is subject to crystalization, a first heating treatment is given thereto by using a germanium as a catalytic element to promote crystalization. Then a second heating treatment is given to the obtained polysilicon film 108 at a higher temperature than that of the first heating treatment, thereby obtaining a polysilicon film 109 in which defects in crystal grains are eliminated significantly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit composed of a thin film transistor (hereinafter abbreviated as TFT) formed using a semiconductor thin film. In particular, the present invention relates to a semiconductor device using an inverted staggered TFT.

[0002] In this specification, a semiconductor device refers to a device which can function by utilizing semiconductor characteristics.
It is not limited to a single element such as T, but also includes a semiconductor circuit, an electro-optical device, and an electronic device mounted with them as a component.

[0003]

2. Description of the Related Art In recent years, attention has been focused on a semiconductor device in which a TFT is formed on a substrate using a semiconductor thin film having crystallinity, and a circuit is formed by the TFT. As a semiconductor thin film, polycrystalline silicon (also referred to as polysilicon) is the most common, but research using a compound semiconductor represented by Si _x Ge _1-x (0 <X <1) has also been made.

Although a TFT using a polysilicon film has already been put to practical use, there is still room for development to improve film quality and mass productivity, and further technical development is required. Under such circumstances, the present applicant discloses a technique described in Japanese Patent Application Laid-Open No. Hei 7-130652 as a means for simultaneously improving the quality of polysilicon film and the improvement of mass productivity.

[0005] The technique described in the publication is to add a catalytic element for promoting crystallization of silicon to an amorphous semiconductor film (typically amorphous silicon), and to crystallize by utilizing the action of the catalyst element. It is a technique to make it. As a result, the temperature and time required for crystallization were reduced, and the throughput was dramatically improved. Furthermore, it was confirmed that the obtained polysilicon had extremely high crystallinity, and the electrical characteristics of the TFT were significantly improved.

However, since nickel (Ni), which is the most effective as the above-mentioned catalyst element, is a metal element, it is feared that if it remains in polysilicon, it will adversely affect TFT characteristics. Therefore, the present applicant has considered that it is necessary to remove excess nickel when crystallization is completed, and has developed a technique for performing gettering of a catalytic element (Japanese Patent Application Laid-Open No. H9-1997).
-112260).

The techniques described in these publications mainly use a metal element such as nickel as a catalyst element for promoting crystallization, and after the polysilicon is obtained, the catalyst element itself is unnecessary. Was there.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a technique for forming a semiconductor thin film having high crystallinity by a manufacturing method with high mass productivity. And T using such a semiconductor thin film
It is an object to reduce a manufacturing yield and a manufacturing cost of a semiconductor device by forming a circuit with an FT.

[0009]

The present invention provides a process that does not require gettering by using germanium (Ge), which is a semiconductor, as a catalyst element for promoting crystallization of silicon. Germanium has a property very close to that of silicon, and therefore exists in silicon with very good consistency. That is, there is an advantage that there is no adverse effect on the TFT characteristics even if it is not particularly removed after being used as a catalyst element.

[0010] Basically, this is a technique in which germanium is added to an amorphous silicon film, and amorphous silicon is crystallized by utilizing the catalytic action of germanium. As a result, the crystallization temperature can be lowered, the processing time can be reduced, and the process can be shortened at the same time.

[0011] Further, since germanium exists in silicon with very high consistency, it has extremely high crystallinity as compared with the case where another catalytic element is used. Since germanium continuously changes the band gap of silicon according to its content, an active layer having a band gap narrower than that of polysilicon can be formed. Such an active layer is called T
Utilization for FT can realize higher mobility (field effect mobility) than TFT using an active layer of polysilicon.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention having the above-mentioned structure will be described in more detail with reference to the following embodiments.

[0013]

[Embodiment 1] A manufacturing process of a TFT using the present invention will be described with reference to FIGS. Here, NTFT is used on the same substrate as the basic configuration of the circuit.
(N-channel TFT) and PTFT (P-channel TF)
A case where a CMOS circuit in which T) and T) are combined in a complementary manner will be exemplified.

In this embodiment, the present invention is used to make T
This is only one example of the case of manufacturing an FT. Therefore, the conditions and numerical values need not be limited to the configuration of the present embodiment.

First, a base film 102 made of a silicon oxide film is provided on a quartz substrate 101, and a gate electrode 10 is formed thereon.
3 and 104 are formed. Although not shown, a gate wiring connected to the gate electrode is also formed at the same time.

The reason why a quartz substrate is used in the present embodiment is that a high heat treatment exceeding 700 ° C. is performed in the subsequent thermal oxidation step, so that a substrate having high heat resistance is required. Therefore, a silicon substrate, a ceramic substrate, crystallized glass, or the like can be used instead of quartz. In the case of quartz, a base film may not be provided.

In this embodiment, the gate electrodes 103, 1
As the conductive film 04, a three-layer structure of tantalum nitride / tantalum / tantalum nitride is adopted. The film thickness is 200
Control with a thickness of ~ 400 nm. In the case of this embodiment, since high-temperature treatment is performed in a later step as described above, it is necessary to use a conductive film having high heat resistance. Alternatively, chromium, titanium, tungsten, or the like may be used.

Then, a gate insulating film 105 made of a silicon oxynitride film represented by SiO _x N _y is formed thereon.
Formed to a thickness of nm. Of course, silicon oxide, silicon nitride, or a stacked structure thereof may be employed.

Next, an amorphous silicon film 106, which is an amorphous semiconductor film, is formed to a thickness of 30 nm. In addition to the amorphous silicon film, a compound semiconductor such as a silicon-germanium compound represented by Si _x Ge _1-x (0 <X <1) can also be used.

Next, a germanium film 107 is formed on the amorphous silicon film 106 by a sputtering method. Using a germanium target for film formation, ultimate pressure 4 × 10
^-4 Pa or less, sputtering gas is argon (Ar), film forming temperature is room temperature, film forming pressure is 0.4 Pa, DC current during film forming is 0.4 A
And

The germanium film 107 can be formed by a low pressure thermal CVD method or a plasma CVD method. Since germane (GeH ₄ ) is a gas which is very easily decomposed, it can be easily decomposed at a low temperature of about 450 ° C. to form a germanium film.

Thus, the state shown in FIG. 1A is obtained. Next, a heat treatment is performed at 600 ° C. for 8 hours to crystallize the amorphous silicon film 106 and change it into a polysilicon film 108 which is a crystalline semiconductor film. If the temperature exceeds 600 ° C., the generation of natural nuclei in amorphous silicon increases, and the crystallinity is mixed with crystals having germanium as nuclei, which is not preferable. (FIG. 1 (B))

This crystallization step may use any of furnace annealing, lamp annealing, and laser annealing. In this embodiment, furnace annealing is used with emphasis on the uniformity of the formed film.

The atmosphere for the heat treatment is preferably an inert atmosphere or a hydrogen atmosphere. In the presence of oxygen, the germanium film is easily oxidized and changes into an inactive germanium oxide film. Attention must be paid to such a case, since the catalytic action may be impaired and poor crystallization may occur.

After the polysilicon film 108 is thus obtained, the germanium film remaining on the polysilicon film 108 is removed with a sulfuric acid / peroxide solution (H ₂ SO ₄ : H ₂ O ₂ = 1: 1).
Thereafter, heat treatment is performed at 900 ° C. for 30 minutes in an oxygen atmosphere. (Fig. 1 (C))

In the present invention, heat treatment at this high temperature (at least higher than the heat treatment temperature in the crystallization step) is very important. By performing this step, trap levels existing in crystal grain boundaries can be reduced, and defects (such as stacking faults) in crystal grains can be significantly reduced.

The present applicant has considered the following model for the above effects. There is a nearly 10-fold difference in the coefficient of thermal expansion between the polysilicon film and the underlying quartz (silicon oxide). Therefore, when the amorphous silicon film is transformed into a polysilicon film, a very large stress is generated when the polysilicon film is cooled.

This will be described with reference to FIG.
FIG. 8A shows a thermal history applied to the polysilicon film after the crystallization step. First, the polysilicon film crystallized at the temperature (t ₁ ) is cooled to room temperature after a cooling period (a).

FIG. 8B shows the polysilicon film during the cooling period (a), 800 is a quartz substrate, and 801 is a polysilicon film. At this time, the adhesion at the interface 802 between the polysilicon film 801 and the quartz substrate 800 is not so high, and it is considered that a large number of intragranular defects are generated due to this.

That is, the polysilicon film 801 pulled by the difference in thermal expansion coefficient is very easy to move on the quartz substrate 800, and a defect 803 such as a stacking fault or a dislocation is easily generated by a force such as a tensile stress. Conceivable.

FIG. 1 shows the polysilicon film thus obtained.
This corresponds to the polysilicon film 108 in FIG. Thereafter, as shown in FIG. 8A, a heat treatment step is performed at a temperature (t ₂ ), and defects in the crystal grains (intra-granular defects) are almost eliminated. This is considered to be due to the fact that interstitial silicon atoms existing between the lattices are moved by the heat treatment to compensate for the defects.

Since such lattice intrusion type silicon atoms are generated in a large amount in the thermal oxidation step, the heat treatment at a temperature higher than the above-mentioned crystallization temperature removes defects more effectively when performed in an oxidizing atmosphere. It is possible.

After the intragranular defects are removed by the heat treatment in this manner, the film is cooled to room temperature again after the cooling period (b). The difference from the cooling period (a) after the crystallization step is that the quartz substrate 800 and the annealed polysilicon film 80 are different.
The point is that the interface 805 with No. 4 is in a state of extremely high adhesion. (FIG. 8 (C))

When the adhesion is high as described above, the polysilicon film 804 is completely fixed to the quartz substrate 800.
Even if stress is applied to the polysilicon film during the cooling step of the polysilicon film, no defect is generated. That is, it is possible to prevent a defect from occurring again.

As described above, by performing the heat treatment at a temperature exceeding the heat treatment in the crystallization step after the crystallization is completed, the interface between the polysilicon film and the base is fixed, and simultaneously with the removal of the intragranular defects. The re-occurrence can be prevented. The present applicant calls this heat treatment step a step of fixing the silicon interface.

In FIG. 8A, a process of lowering the temperature to room temperature after the crystallization step is taken as an example. However, after the crystallization is completed, the fixing step can be performed by raising the temperature as it is. A polysilicon film having similar crystallinity can be obtained through such a process.

The polysilicon film 109 thus obtained
Has a feature that the number of defects in crystal grains is remarkably smaller than that of the polysilicon film 108 which is simply crystallized. The difference in the number of defects was determined by electron spin resonance analysis (Elec
It appears as a difference in spin density due to tron spin resonance (ESR).

At present, the spin density of the polysilicon film 109 is at least 5 × 10 ¹⁷ spins / cm ³ or less (preferably ³ × 10 ¹⁷ spins / cm ³ or less).
× 10 ¹⁷ spins / cm ³ or less). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

Further, by utilizing germanium as a catalytic element, abnormal oxidation of the polysilicon film is prevented in the step shown in FIG. According to the present applicant, when nickel is used as a crystallization catalyst, nickel silicide may be oxidized intensively and grow abnormally. This can be prevented by performing thermal oxidation while preventing the silicon from directly contacting the oxidizing atmosphere, but has caused an increase in the number of steps.

However, in the present invention, since germanium having a high consistency with silicon is used as a catalyst without using nickel, such local abnormal oxidation does not occur, and the polysilicon film which has been crystallized is not used. Heat treatment can be applied directly to the heat treatment.

In this embodiment, the heat treatment is performed at 900 ° C. for 30 minutes.
900900 ° C.), and the heat treatment is performed at such a high temperature. In this step, it is considered that the thermal oxidation mechanism greatly contributes to the reduction of intragranular defects.

Therefore, considering the throughput, the lower limit temperature of the heat treatment is preferably 800 ° C., and the upper limit is preferably 1050 ° C. in consideration of the heat resistance of the substrate (quartz in this embodiment). However, since the melting point of germanium is 930 to 940 ° C., the upper limit is preferably set to 900 ° C.

The heat treatment atmosphere is preferably an oxidizing atmosphere, but may be an inert atmosphere.
In the case of using an oxidizing atmosphere, any of a dry oxygen (O ₂ ) atmosphere, a wet oxygen (O ₂ + H ₂ ) atmosphere, and an atmosphere containing a halogen element (O ₂ + HCl) may be used.

In particular, when heat treatment is performed in an atmosphere containing halogen, excess germanium existing between the lattices of polysilicon becomes volatile due to the gettering effect of the halogen element.
It is removed in the form of GeCl _4. Therefore, this is an effective means for obtaining a polysilicon film with less lattice distortion.

Further, when a heat treatment at 800 to 1,050 ° C. is performed in an oxidizing atmosphere, a thermal oxide film (not shown in the drawing) is formed, so that the polysilicon film itself becomes thin. When practicing the present invention, the thickness of the amorphous silicon film at the time of film formation is determined in consideration of the film reduction due to the thermal oxidation process, and the film thickness when finally used as the active layer of the TFT is 5 to
It is good to design to be 50 nm (preferably 15 to 45 nm). When the film thickness is less than 5 nm, it is difficult to form a normal source / drain contact, and when it exceeds 50 nm, the effect of thinning is reduced.

The polysilicon film of this embodiment obtained by the manufacturing method having the above-described structure has extremely high crystallinity, and is an optimum semiconductor thin film as an active layer of a thin film transistor.
Also, its crystal structure is very characteristic.

When the polysilicon film obtained through the above steps is observed by a TEM (transmission electron microscope), a characteristic pattern extending radially from a certain point is observed.
This seems to be a pattern peculiar to the polysilicon film crystallized using germanium.

The polysilicon film 109 has a thickness of approximately $ 11.
It has been confirmed by XRD (X-ray diffraction) analysis that 1 ° orientation occurs. Further, as a result of examining the polysilicon film 109 by using an electron diffraction method, an electron diffraction pattern almost equal to that of single crystal silicon having {111} orientation was obtained. This means that the polysilicon film 109 has a crystal structure substantially regarded as a single crystal.

The crystal structure of the polysilicon film of the present invention as described above remains unchanged until the TFT is completed. That is, the TFT formed in the manufacturing process of this embodiment
In the active layer, the main orientation plane is approximately {111} plane,
It can be said that there are almost no defects in the crystal grains, and that the crystal grains have a crystal structure substantially regarded as a single crystal.

Further, germanium exists in the polysilicon film of this embodiment. SIMS (Mass Secondary Ion Analysis) confirmed that germanium was distributed at a concentration of 1 × 10 ¹⁴ to 1 × 10 ²² atoms / cm ³ . The distribution of germanium tends to increase as it approaches the main surface of the polysilicon film (the surface of the polysilicon opposite to the base).

It should be noted that germanium is present only up to about 1 × 10 ²⁰ to 1 × 10 ²² atoms / cm ^{3 in the} vicinity of the main surface (region within a depth of about 10 nm from the main surface). At such a concentration, alloying of silicon and germanium occurs, which may result in a silicon germanium layer represented by Si _x Ge _1-x (0 <X <1). That is, in the case of this embodiment,
Such a silicon germanium layer may be formed only near the main surface of the polysilicon film.

However, at most a region deeper than about 10 nm from the main surface contains only germanium at a concentration of 1 × 10 ¹⁴ to 1 × 10 ²⁰ atoms / cm ³ , and no silicon germanium layer is formed. In other words, the TFT has a laminated structure of a polysilicon layer and a silicon germanium layer, and is clearly different from a TFT which only uses a silicon germanium film as an active layer.

In such a laminated structure, the channel region formed near the main surface is formed in the silicon germanium layer. Therefore, since the channel region in which carriers move is a silicon germanium layer, carrier mobility is improved. In addition, it has been pointed out that the silicon germanium layer causes a problem such as an increase in leakage current. However, in this laminated structure, a region deeper than the silicon germanium layer is a polysilicon layer, which is effective in suppressing off current and leakage current. .

Of course, the concentration of germanium existing near the main surface of the polysilicon film is 1 × 10 ¹⁴ to 1 × 10 ²⁰ atoms / cm.
If it is ³ , the entire active layer becomes a polysilicon film. This is because alloying does not occur at such a germanium concentration, and it is not considered that a silicon germanium layer is formed.

When the polysilicon film 109 which can be regarded as a substantially single crystal is obtained, a silicon oxide film having a thickness of 120 nm is formed and patterned to form the spacer insulating layer 110,
111 is formed. After the formation of the spacer insulating layers 110 and 111, an n-type impurity element (phosphorus in this embodiment) is added to form an n-type impurity region 112. (Fig. 1 (D))

In this embodiment, phosphine (PH ₃ ) is used as a doping gas by a plasma doping method. The accelerating voltage is 10 keV and 5 × 10 ¹⁴ atoms / cm ²
May be added at a dose of. Note that the doping conditions need not be limited to this embodiment, but may be changed as needed.

When the state shown in FIG. 1D is obtained,
A resist mask 113 is selectively provided, and a second step of adding an n-type impurity is performed. The resist mask 113 is NT
The region to be FT is formed above the region where a channel formation region is to be formed later, and the region to be a PTFT is formed so that n-type impurities are not added. (Fig. 2 (A))

Here, the acceleration voltage is set to 90 keV, which is higher than the above, and the dose is 3 × 10 ¹³ atoms / cm ² .
Since the spacer insulating layers 110 and 111 do not function as a mask at this acceleration voltage, impurity ions are also added to the silicon film below the end of the spacer insulating layer (a region not hidden by the resist mask 113).

By this step, the source region 11 of the NTFT is formed.
4. A drain region 115, a pair of LDD regions (low-concentration impurity regions) 116, and a channel formation region 117 are defined. Since the second doping step is also a step of forming an LDD region as it is, it is necessary for an operator to appropriately determine an optimum doping amount for the LDD region.

Next, after the resist mask 113 is removed, the region to be NTFT is completely hidden by the resist mask 118, and an impurity element imparting P-type (boron in this embodiment) is added. Here, diborane (B ₂ H ₆ ) is used as a doping gas, the acceleration voltage is 10 keV, and the dose is 1.3 × 10 ¹⁵ atoms / cm ² . (FIG. 2 (B))

In this step, since the spacer insulating layer 111 completely functions as a mask, no impurities are added under the spacer insulating layer 111, and the spacer insulating layer 111 is directly used as the source region 119, the drain region 120, and the channel forming region 1.
21 is defined. Note that the PTFT in the process of FIG.
Phosphorus is also added to the region to become p-type.

Thus, the source region, the drain region and the L
After the step of adding impurity ions for forming the DD region is completed, the resist mask 118 is removed, and the polysilicon film is patterned to form island-like silicon layers (active layers) 122, 1
23 are formed.

After that, an impurity activation step is performed. In this embodiment, the activation is performed by irradiating an excimer laser beam. However, furnace annealing or lamp annealing may be used. Of course, they can be used in combination. (Figure 2
(C))

The spacer insulating layers 110 and 111 may be removed before the step of activating the impurities.
The removal greatly improves the efficiency of activation by laser beam irradiation. However, when the spacer insulating layer is removed, the channel formation region is exposed.

Next, an interlayer insulating film 1 made of a silicon oxide film
24, a contact hole is formed, and source wirings 125 and 126 and a drain wiring 127 made of a conductive film are formed. At this time, a contact hole (not shown) for electrically connecting the gate wiring connected to the gate electrode to the source wiring (or drain wiring) must be formed at the same time.

Finally, the whole is subjected to a heat treatment at 350 ° C. for about 2 hours in a hydrogen atmosphere to terminate dangling bonds in the film (particularly in the channel forming region). Through the above steps, a CMOS circuit having a structure as shown in FIG. 2D is completed.

As a feature of the TFT manufactured in the steps of this embodiment, germanium is present at a higher concentration in the polysilicon film serving as the active layer as it approaches the main surface. This is because crystallization was performed in contact with germanium on the main surface. Typically, germanium is often present only near the main surface. The germanium concentration in that case is
It is about 1 × 10 ¹⁴ to 1 × 10 ²² atoms / cm ³ .

Since the channel formation region does not pass through a step that disturbs the crystallinity in a later step after the formation of the active layer, the main orientation plane is substantially {111} plane, and substantially single crystal It has a crystal structure feature that can be considered, and also has a feature that the spin density in the film is 5 × 10 ¹⁷ spins / cm ³ or less.

In the present invention, a circuit is constituted by the inverted staggered TFT manufactured in the above-described steps. Note that the manufacturing process of this embodiment is merely an example for carrying out the present invention, and should not be limited to this.

Although not performed in this embodiment, NTF
The practitioner may appropriately perform channel doping on the T and PTFT and control the threshold voltage.

The inverted staggered TFT manufactured according to the process of this embodiment has NTFT mobility (field effect mobility) of 200 to 350 cm ² / Vs and PTF
A 150~250cm ² / Vs at T, S value (sub-threshold coefficient) is NTFT, PTFT both 70~200mV / decade
It is.

The important structure of the present invention lies in that the amorphous silicon film is crystallized using germanium as a catalyst, and this structure is not limited to the structure of the TFT. Therefore, the present invention is applied to a planar type TFT.
It can also be applied to a top gate type TFT such as a staggered type TFT or the like.

[Embodiment 2] In this embodiment, an example of an inverted staggered TFT manufactured by a process different from that of Embodiment 1 will be described with reference to FIGS.

First, in accordance with the steps of Embodiment 1, FIG.
The steps up to the step are ended. Next, active layers 201 and 202 are formed by patterning the polysilicon film. After forming the active layers 201 and 202, spacer insulating layers 203 and 204 made of a silicon oxide film are formed. (FIG. 3
(A))

Next, plasma CVD or reduced pressure thermal CVD
An amorphous silicon film 205 is formed to a thickness of 100 nm by using the method, and a microcrystalline silicon film 206 is further formed thereon.
It is formed to a thickness of 50 nm. (FIG. 3 (B))

The conditions for forming the amorphous silicon film 205 are as follows: 100 sccm SiH ₄ and 300 sccm H
_The film forming pressure is 0.75 torr, and the applied power is 20 W using a gas obtained by mixing ₂ and ₂ . Further, film forming conditions of the microcrystalline silicon film 206, and SiH ₄ of 5sccm as a deposition gas 500sccm
Using a gas mixed with H ₂ at a film forming pressure of 0.75 torr,
The applied power is 300W.

Next, an impurity element for imparting n-type (phosphorus in this embodiment) is added to the amorphous silicon film 205 and the microcrystalline silicon film 206, and the n-type amorphous silicon film 207 and the n-type Crystalline silicon film 20
Get 8. (FIG. 3 (C))

At this time, the phosphorus addition condition is that the acceleration voltage is 10
keV, and the dose is 5 × 10 ¹⁴ atoms / cm ² . Note that the n-type semiconductor layer having a stacked structure of the amorphous silicon film 207 and the microcrystalline silicon film 208 functions as an electrode for extracting carriers from the active layer, and thus has only to have conductivity appropriate for the function. . Therefore, it is not necessary to limit to the numerical values adopted in the manufacturing process of this embodiment.

The reason why the microcrystalline silicon film is provided as the uppermost layer is to make it easy to make ohmic contact with a wiring layer formed of a conductive film to be formed later. Although it is difficult to obtain good ohmic contact between the amorphous silicon film and the conductive film, a satisfactory level of ohmic contact can be obtained with microcrystalline silicon and the conductive film.

Next, a region to be an NTFT is hidden by a resist mask 209, and an impurity element imparting p-type (boron in this embodiment) is added. In this step, the n-type semiconductor layer formed earlier is inverted in a region to be a PTFT, and a p-type semiconductor layer including a p-type amorphous silicon film 210 and a p-type microcrystalline silicon film 211 is formed. (FIG. 3 (D))

At this time, the condition of boron addition is that the accelerating voltage is 1
0 keV and the dose is 1.3 × 10 ¹⁵ atoms / cm ² . In this case as well, as long as it has sufficient conductivity to take out carriers from the active layer, as described above.

After the step of adding the impurity element is completed, the resist mask 209 is removed, and a furnace anneal process is performed at 350 ° C. for 1 hour in a hydrogen atmosphere to perform a hydrogenation step. In this embodiment, this hydrogenation step also serves as the step of activating the impurity added earlier.

In this embodiment, the n-type semiconductor layer and the p-type semiconductor layer are formed by adding impurities. However, when the semiconductor layer is formed, n-type or P-type is used as a film forming gas. It is also possible to add an impurity to be imparted.

Next, a resist mask (not shown) having an opening is provided on a part of the gate wiring connected to the gate electrode (a part electrically connected to a wiring to be formed later), and dry etching is performed. The microcrystalline silicon film, the amorphous silicon film, and the gate insulating film are sequentially etched to form a contact hole (not shown). Dry etching may be performed within a known technical range.

Then, a resist mask (not shown) is removed, and a conductive film made of a material containing aluminum as a main component is formed on the n-type semiconductor layer and the p-type semiconductor layer. And a drain wiring 214 is formed. At this time, the gate wiring and the source wiring (drain wiring) are formed through the contact hole.
Are electrically connected.

Further, the n-type semiconductor layer and the p-type semiconductor layer are etched using these wirings as a mask. This etching may be performed under the same conditions as those for forming the contact holes. However, it is necessary to set conditions so that the semiconductor layer can be etched without etching the wiring.

The semiconductor layer is etched by the spacer insulating layer 2
Stop at 03 and 204, the source wiring and the drain wiring are completely separated electrically. When the process is completed so far, hydrogenation is performed in a hydrogen atmosphere, and a CM having a structure shown in FIG.
The OS circuit is completed.

In the structure of this embodiment, an inversely staggered TFT can be manufactured with one less mask (six) than in the first embodiment. As a result, the yield can be improved and the manufacturing cost can be reduced. Of course, the electrical characteristics of the TFT of this embodiment are comparable to those of the TFT manufactured in the steps of Embodiment 1.

[Embodiment 3] In this embodiment, a case in which a layer containing germanium is formed on an amorphous silicon film by a solution coating method (spin coating method) will be described.

In this embodiment, a solution containing germanium is applied on the amorphous silicon film. Such solutions include germanium oxide (GeO _x , typically GeO ₂ ),
Germanium chloride (GeCl ₄ ), germanium bromide (GeB
r ₄ ), germanium sulfide (GeS ₂ ), and aqueous solutions of germanium acetate (Ge (CH ₃ CO ₂ )).

In some cases, an alcoholic solvent such as ethanol or isopropyl alcohol may be used as the solvent.

These solutions are prepared at a concentration of 100 to 1000 ppm, applied and spin-dried to form a germanium-containing layer on the amorphous silicon film. In addition,
Since the amorphous silicon film shows hydrophobicity, it is preferable to form a thin silicon oxide film before spin coating to enhance wettability.

When the spin coating is completed, a heat treatment for crystallization is performed in that state to obtain a polysilicon film. Since the surface of the polysilicon film contains germanium at a high concentration, it is preferable to wash the surface with an etchant such as hydrofluoric acid.

By applying the structure of this embodiment to Embodiments 1 and 2, TFTs as shown in FIGS. 2D and 3E can be easily manufactured.

[Embodiment 4] When germanium is added to an amorphous silicon film, an ion plantation method, a plasma doping method or a laser doping method can be used.

Germane (GeH ₄ ) may be used as the excitation gas, and 1 × 10 ¹⁴ to 5
× 10 ¹⁹ atoms / cm ³ (typically 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atom
It is preferable to adjust so that germanium is added at a concentration of s / cm ³ ).

Germanium added to the amorphous silicon film is 1 × 10 ¹⁴ atoms / cm ³ or more (preferably 1 × 10 ¹⁴ atoms / cm ^3).
If it is less than ¹⁶ atoms / cm ³ ), the effect of promoting crystallization cannot be effectively used as a catalyst. On the other hand, if the addition amount is too large, the physical properties of the germanium film become close to each other, and the TFT characteristics deteriorate. For this reason, it is desirable that the concentration be suppressed to 5 × 10 ¹⁹ atoms / cm ³ or less, and preferably 1 × 10 ¹⁸ atoms / cm ³ or less.

The amorphous silicon film in which germanium is added to the film is easily crystallized by a heat treatment at 450 to 650 ° C. The polysilicon film obtained in this embodiment contains many bonds in which silicon atoms and germanium atoms are substituted, and is called silicon germanium (Si _X Ge).
_1-X ).

It is known that the mobility of carriers (electrons or holes) is improved because such a silicon germanium film has a narrower band gap than a silicon film. However, it should be noted that the TFT characteristics may greatly change depending on the germanium content.

By applying the structure of this embodiment to Embodiments 1 and 2, TFTs as shown in FIGS. 2D and 3E can be easily manufactured.

[Embodiment 5] In this embodiment, when an amorphous silicon film is formed on a substrate, means for adding germanium to the film at the stage of film formation is adopted.

The film is formed by low pressure thermal CVD or plasma CVD.
The film formation gas is a gas obtained by mixing a predetermined amount of germane (GeH ₄ ) with silane (SiH ₄ ) or disilane (Si ₂ H ₆ ). Alternatively, a gas in which germanium fluoride (GeF ₄ ) is mixed with disilane can be used.

In such a means, the amount of germanium added can be adjusted by the flow rate of germane gas, and can be uniformly distributed in the amorphous silicon film. Further, a special process is not required for adding germanium, which is effective for simplifying the process.

In the present embodiment, 1 × 10 ¹⁴ to 5 × 10 ¹⁹ atoms / cm ³ (preferably 1 × 10 ¹⁶
The flow rate of germane gas is adjusted so that germanium is added at a concentration of about 1 × 10 ¹⁸ atoms / cm ³ ). The upper and lower limits of the germanium concentration have been described in the fourth embodiment and will not be described.

The amorphous silicon film in which germanium is added to the film is easily crystallized by a heat treatment at 500 to 600 ° C. Also, the polysilicon film obtained by crystallization in the same manner as in Example 4 is considered to be a silicon germanium film.

By applying the structure of this embodiment to Embodiments 1 and 2, TFTs as shown in FIGS. 2D and 3E can be easily manufactured.

[Embodiment 6] In this embodiment, a case where phosphorus is used as a means for gettering germanium will be described. The manufacturing process of this embodiment will be described with reference to FIGS. First, the steps up to the step shown in FIG. 1C are completed according to the steps of the first embodiment. Next, the polysilicon film 1
A thin film 401 containing phosphorus is formed on the substrate 09. (FIG. 4
(A))

As a thin film containing phosphorus, typically, PS
An insulating film called G (phosphorus silicate glass) in which phosphorus is added to silicon oxide is given. In this embodiment, an n-type amorphous silicon film in which phosphorus is added to the amorphous silicon film can be used.

After forming the thin film 401 containing phosphorus, 500
A heat treatment is performed at a temperature of 600 ° C. (typically 550 ° C.) for 2 to 8 hours (typically 4 hours). (FIG. 4 (B))

In this step, germanium contained in the polysilicon film 109 (especially germanium which enters between silicon lattices to form a lattice mismatch) is reduced by the gettering effect of phosphorus as shown by arrows. It is taken into the thin film 401 containing phosphorus.

At this time, the moving distance of germanium is very small since it is almost the same as the thickness of the polysilicon film 109. Therefore, gettering can be performed effectively despite relatively short processing at a relatively low temperature.

Next, the thin film 401 containing phosphorus is removed, and
A polysilicon film 402 from which germanium existing between lattices is removed is obtained. After that, the TFT may be manufactured in the same steps as those in the first embodiment and the second embodiment.

As the gettering technique using phosphorus, the technique described in Japanese Patent Application No. 9-094607 by the present applicant may be used.

Further, the gettering step using phosphorus shown in this embodiment is performed immediately after the crystallization of the amorphous silicon film, and the step of fixing the silicon interface as described in the first embodiment is performed after the gettering step. May be.

[Embodiment 7] When performing a crystallization step using germanium as a catalyst element, it is necessary to pay attention to the amount of oxygen present in the treatment atmosphere during crystallization. As explained in the first embodiment, germanium is easily oxidized to be inactive germanium oxide, so that it is necessary to eliminate oxygen as much as possible.

For this reason, it is desirable to continuously perform the steps of cleaning the surface of the amorphous silicon film, forming a germanium film, and crystallizing by heat treatment without opening to the atmosphere.

In this embodiment, such a process is performed using a multi-chamber (cluster tool) type processing apparatus. FIG. 9 shows a processing apparatus used in this embodiment. Note that FIG. 9A is a top view, and FIG.
The cross-sectional configuration diagram at X ′ is shown.

Reference numeral 11 denotes a common room for the entire apparatus,
3 is a load lock chamber, 14 and 15 are sputtering chambers, 16 is an etching chamber, 17 is a heating chamber, and each of the chambers 12 to
17 is connected to the common chamber 11 via a gate valve,
The airtightness can be maintained for each of the chambers 11 to 17.

An exhaust system (not shown) for reducing the pressure in each of the chambers 11 to 17 and a gas supply system (not shown) for supplying a gas for controlling the atmosphere or a sputtering gas are provided. Have been. The evacuating system of the sputtering chambers 14 and 15 and the etching chamber 16 is provided with a cryopump in order to achieve an ultimate vacuum of 10 ⁻⁶ Pa.

In the common chamber 11, the processing substrate 10 is placed in the chambers 12-1.
A robot arm 31 for moving to 7 is provided. The substrate holding portion of the robot arm 31 is three-dimensionally movable as shown by the arrow. The robot arm 31 is of a face-down type in which the element formation surface of the processing substrate 10 is transported downward, thereby preventing dust such as particles from adhering to the element formation surface.

The load lock chambers 12 and 13 store the processing substrate 10
This is a room for carrying in and out of the equipment. The processing substrate 10 is stored in the substrate transport cassettes 32 and 33, and is carried in and out of the apparatus.

The sputtering chambers 14 and 15 have substantially the same structure, and the configuration of the sputtering chamber 14 will be described with reference to FIG. In this embodiment, a germanium film is formed in the sputtering chamber 14 or 15.

In the sputtering chamber 14, the target support 4
1, a target 42, a shutter 43, and a face-down type substrate holder 44 are provided. The substrate holder 44 is designed to support a few millimeters of the edge of the processing substrate 10 so that contamination of the substrate 10 is minimized.

A DC current is supplied from a DC power supply (not shown) to the target via the target 41. The specifications of the gas supply system and the like are determined depending on the material to be formed in the sputtering chambers 14 and 15.

In this embodiment, the etching chamber 16 has substantially the same structure as the sputtering chambers 14 and 15, but an RF power supply is connected instead of the DC power supply, and the RF power is supplied to the substrate 10. Thus, a negative self-bias voltage is applied.

In this embodiment, the surface of the amorphous silicon film is cleaned by lightly sputtering the surface of the amorphous silicon film with a rare gas (eg, argon or helium) in the etching chamber 16 (to etch the surface layer). Cleaning the surface.

The heating chamber 17 is a chamber for the crystallization step, and has a configuration capable of performing an RTA process as a heating means from the viewpoint of throughput. Face-down type substrate holder 51
And heating lamps 52 and 53 for emitting infrared light for heating the substrate 10 from both sides. The heating lamp 53 serves as a main lamp for heating the main surface of the substrate.

The method of using the processing apparatus shown in FIG. 9 in this embodiment will be described below. A substrate to be processed (a substrate on which an amorphous silicon film is formed) 10 is transferred from the load lock chamber 12 into the sputtering apparatus. After the load lock chamber 12 is depressurized, a nitrogen atmosphere is set. The common chamber 11, the sputtering chambers 14, 15, and the etching chamber 16 are also decompressed, and the ultimate pressure is 10 ⁻⁶ Pa.

The gate valve 22 is opened, and the robot arm 3 is opened.
1 moves the substrate 10 to the etching chamber 16. In order to avoid mixing of the atmosphere, the two gate valves 22
27 are controlled not to open simultaneously. The same applies to the following. The substrate is fixed to the substrate holder in the etching chamber 16, and a sputtering process is performed with an argon gas while applying RF power to the substrate. Impurities and natural oxide films on the surface of the amorphous silicon film are removed by the sputtering process.

Next, the substrate 10 is moved to the sputtering chamber 14 to form a germanium film. Then, the substrate is moved to the heating chamber 17. The heating chamber 17 is set in a nitrogen atmosphere, and the substrates are heated by the heating lamps 52 and 53 to crystallize the amorphous silicon film. When the crystallization step is completed, the substrate is moved into the cassette 33 in the load lock chamber 13 and is unloaded from the sputtering device.

Before the crystallization step, in order to suppress oxidation of the germanium film as much as possible, a germanium film is formed in the sputtering chamber 14, and then a silicon nitride film and a silicon oxynitride film are formed on the germanium surface in the sputtering chamber 15. It is also effective to form an insulating film such as the above to cover the germanium surface.

The crystallization step is performed without directly contacting the processing atmosphere by covering the surface of the germanium film with the insulating film.
This configuration is a particularly effective technique not only for use in a multi-chamber processing apparatus as in this embodiment, but also for the case where the crystallization step needs to be performed in an external electric heating furnace.
Of course, it is easy to combine this configuration with the configurations shown in the first to sixth embodiments.

[Embodiment 8] In this embodiment, a plurality of TFTs are manufactured on a glass substrate by using the present invention, and an active matrix liquid crystal display device in which a driver circuit and a pixel matrix circuit are integrally formed is manufactured. 5 is shown in FIG.

The structure of this embodiment can be realized by adding a few additional steps to the steps of the first embodiment. First, the state of FIG. 2D is obtained according to the steps of the first embodiment.
At this time, NTFTs arranged in a matrix are manufactured in a region to be a pixel matrix circuit.

A 50 nm thick first flattening film 501 is formed thereon.
A silicon nitride film, a 25 nm silicon oxide film and a 1 μm thick polyimide film are sequentially laminated to form a laminated film. Other organic resin materials such as acrylic besides polyimide may be used.

Next, the TF constituting the pixel matrix circuit
An opening is provided on the T drain electrode 502. This opening is etched from the top up to the polyimide film and the silicon oxide film, leaving the lowermost silicon nitride film.
After the opening is formed, a black mask 503 made of a conductive film such as titanium is formed.

Then, a polyimide film is formed to a thickness of 500 nm as the second flattening film 504. After the second flattening film 504 is formed, contact holes are opened in the first and second flattening films to form a transparent conductive film (typically, ITO).
A pixel electrode 505 made of a film is formed.

At this time, between the drain electrode 502 and the black mask 503, an auxiliary capacitance having the above-mentioned 50 nm thick silicon nitride film as a dielectric is formed. According to the structure of this embodiment, since the auxiliary capacitance is formed on the TFT, the aperture ratio is not deteriorated.

Through the above steps, a structure as shown in FIG. 5 is completed. An actual active matrix liquid crystal display device is completed by forming an alignment film after forming a pixel electrode, and sandwiching a liquid crystal between the pixel electrode and a counter electrode. Since these cell assembling steps may be performed using known means, description thereof will be omitted.

FIG. 6 schematically shows the appearance of the active matrix type liquid crystal display device thus formed. 6, reference numeral 601 denotes a substrate having an insulating surface; 602, a pixel matrix circuit; 603, a source driver circuit;
Is a gate driver circuit, 605 is a counter electrode, 606 is an FPC (flexible printed circuit), 607,
608 is an externally mounted IC chip.

At this time, for example, the source driver circuit 60
The gate driver circuit 604 and the gate driver circuit 604 are constituted by CMOS circuits as indicated by 600.

In this embodiment, if the pixel electrode is made of a material having a high reflectance, a reflection type liquid crystal display device can be easily manufactured.

As described above, by forming various circuits using the TFT manufactured by utilizing the present invention, an electro-optical device having a circuit on a substrate can be realized.
Although the liquid crystal display device is taken as an example in this embodiment,
It is also possible to manufacture an EL (electroluminescence) display device, an image sensor, and the like.

[Embodiment 9] The electro-optical device as shown in Embodiment 1 is used as displays of various electronic apparatuses. Such electronic devices include video cameras, still cameras, projectors, projection TVs,
Examples include a head-mounted display, car navigation, a personal computer, a portable information terminal (mobile computer, mobile phone, and the like). One example is shown in FIG.

FIG. 7A shows a mobile phone, and a main body 200.
1, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 2006
It consists of. The present invention can be applied to the display device 2004 and the like.

FIG. 7B shows a video camera,
101, display device 2102, audio input unit 2103, operation switch 2104, battery 2105, image receiving unit 210
6. The present invention can be applied to the display device 2102.

FIG. 7C shows a mobile computer (mobile computer), which includes a main body 2201 and a camera section 2.
202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 and so on.

FIG. 7D shows a head-mounted display, which includes a main body 2301, a display device 2302, and a band 2
303. The present invention can be applied to the display device 2302.

FIG. 7E shows a rear type projector, which includes a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The invention can be applied to the display device 2403.

FIG. 7F shows a front type projector, which includes a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The invention can be applied to the display device 2503.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. In particular, it can be said that this is very effective for an electronic device that emphasizes portability.

[0152]

According to the present invention, a semiconductor thin film having high crystallinity can be manufactured in a manufacturing process with high productivity. Then, a semiconductor device having a circuit using a high-performance TFT using such a semiconductor thin film as an active layer can be realized.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a thin film transistor.

FIG. 2 illustrates a manufacturing process of a thin film transistor.

FIG. 3 illustrates a manufacturing process of a thin film transistor.

FIG. 4 illustrates a manufacturing process of a thin film transistor.

FIG. 5 illustrates a structure of an active matrix liquid crystal display device.

FIG. 6 illustrates a structure of an active matrix liquid crystal display device.

FIG. 7 illustrates a structure of an electronic device.

FIG. 8 is a view for explaining an outline of a fixing step.

FIG. 9 illustrates a configuration of a multi-chamber processing apparatus.

Claims (6)

[Claims] 1. A semiconductor device including a circuit including a plurality of TFTs formed on a substrate having an insulating surface, wherein a channel forming region of the plurality of TFTs has a principal orientation plane of a {111} plane. 1 × 10 ¹⁴ to 1 × 10 ²⁰ atoms / cm ^{3 in the} crystalline semiconductor film.
A semiconductor device, wherein germanium is present at a concentration of 1 ×, and the spin density in the crystalline semiconductor film is 5 × 10 ¹⁷ spins / cm ³ or less. 2. A semiconductor device including a circuit including a plurality of TFTs formed on a substrate having an insulating surface, wherein a main orientation plane of a channel forming region of the plurality of TFTs is a {111} plane, and A crystalline semiconductor film that can be considered substantially as a single crystal, wherein the crystalline semiconductor film contains 1 × 10 ¹⁴ to 1 × 10 ²⁰ atoms / cm ³
A semiconductor device, wherein germanium is present at a concentration of 1 ×, and the spin density in the crystalline semiconductor film is 5 × 10 ¹⁷ spins / cm ³ or less. 3. The semiconductor device according to claim 1, wherein the plurality of TFTs are bottom gate type TFTs. 4. A method for manufacturing a semiconductor device including a circuit including a plurality of bottom-gate TFTs formed on a substrate having an insulating surface, wherein: a step of forming an amorphous semiconductor film; Forming a germanium film on the semiconductor film, performing a first heat treatment on the amorphous semiconductor film to change the amorphous semiconductor film into a crystalline semiconductor film, and performing the first heating on the crystalline semiconductor film. Performing a second heat treatment at a temperature higher than the temperature of the treatment. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the germanium film is formed by a sputtering method, a plasma CVD method, or a low pressure thermal CVD method. 6. The method according to claim 4, wherein the first heat treatment is performed.
A method for manufacturing a semiconductor device, wherein the method is performed in a temperature range of 450 to 650 ° C., and the second heat treatment is performed in a temperature range of 800 to 50 ° C.