JPH11298756A - Speed modulation signal generation circuit - Google Patents

Abstract

(57) [Problem] To provide a speed modulation signal generation circuit for performing speed modulation correction without making a black vertical line on a screen unnecessarily thick. A speed modulation correction signal generation circuit for generating a speed modulation correction signal, a delay circuit, an addition circuit, first, second, and third code extraction circuits for extracting + and-signs of an input signal, and SW. And a logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed modulation signal generating circuit for providing speed modulation correction without making a vertical black line thicker than necessary.

[0002]

2. Description of the Related Art In recent years, a speed modulation signal generation circuit has been regarded as important as a circuit for generating a scanning line speed modulation signal of a CRT in a large-screen television receiver.

Hereinafter, an example of the above-described conventional speed modulation signal generation circuit will be described with reference to the drawings.

FIG. 4 is a block diagram of a speed modulation signal generating circuit proposed in Japanese Patent Publication No. Hei 7-118780. In the block diagram of FIG. 4, reference numeral 11 denotes a contrast circuit, 12 denotes a secondary differential waveform generation circuit, 13 denotes a gain control circuit, 14 denotes an addition circuit, 16 denotes a primary differential waveform generation circuit, 17 denotes a gain control circuit, 18 Is an amplification circuit, 19 is an amplitude detection circuit, 20 is an electric contour compensation circuit,
21 is a scanning linear velocity modulation circuit, 22 is a frequency detection circuit, 2
Reference numeral 3 denotes a control signal generation circuit, 5 denotes an image amplification circuit, 7 denotes an auxiliary deflection yoke, and 8 denotes a CRT.

[0005] The operation of the speed modulation signal generating circuit configured as described above will be described below. First,
FIG. 5 is a diagram illustrating the operation of a conventional speed modulation signal generation circuit. FIG. 5A shows an input luminance signal, which is supplied to the contrast circuit 11 and controls the amplitude of the video signal voltage applied to the CRT 8. The signal from the contrast circuit 11 is supplied to a secondary differential waveform generation circuit 12, a primary differential waveform generation circuit 16, a frequency detection circuit 22, and an amplitude detection circuit 19. In the secondary differential waveform creation circuit 12, FIG.
As shown in (b), a secondary differential signal of the input video signal is created.

[0006] In the first-order differential waveform creating circuit 16, FIG.
As shown in (1), a primary differential signal of the input video signal is created. The secondary differential waveform generator 12 supplies the secondary differential signal to the gain control circuit 13, and the primary differential waveform generator 16 supplies the gain control circuit 17. The frequency detection circuit 22 detects the frequency of the video signal and performs, for example, detection of the maximum value and the minimum value of the extracted signal to obtain a voltage indicated by a solid line in FIG. Next, the voltage indicated by the dashed line in FIG. 5F is obtained. The amplitude detection circuit 19 detects the amplitude of the video signal. For example, FIG.
The amplitude of the video signal shown in (a) is detected by comparing with the comparison potential V1.

Therefore, the amplitude detection circuit 19 outputs the
The detection signals indicated by the solid lines (d) and (e) are output. The detection signals from the amplitude detection circuit 19 and the frequency detection circuit 22 are supplied to a control signal generation circuit 23 to generate a control signal for performing gain control. The control signal creation circuit 23 performs weighting based on the frequency band information from the frequency detection circuit 22 and the amplitude information from the amplitude detection circuit 19, and outputs a control signal as shown in FIG. Is done. Since the gain control of the primary differential signal is performed using this signal, the scanning linear velocity modulation signal is a signal whose gain is controlled as shown in FIG.

[0008]

However, the above configuration has the following problems. The output of the scanning linear velocity modulation signal is only gain-controlled as shown in FIG. 5 (h), and the range to be corrected does not change. Therefore, in the case of a signal having an amplitude on the black side as shown in FIG. 5A, the width of the black line becomes unnecessarily thick on the screen, resulting in an unnatural screen.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems, a speed modulation signal generation circuit according to the present invention comprises: a speed modulation correction signal generation circuit for generating a speed modulation correction signal from an input luminance signal; A delay circuit that delays an output signal from the modulation correction signal generation circuit, an addition circuit that receives an output signal of the speed modulation correction signal generation circuit as an input, and a first circuit that extracts + and-signs of the output signal of the delay circuit. , A second code extracting circuit for extracting the + and-signs of the output signal of the adding circuit, and a third code for extracting the + and-signs of the output signal of the speed modulation correction signal generating circuit. An extraction circuit, an SW circuit for switching between an output signal of the speed modulation correction signal generation circuit, an output signal of the delay circuit, and a DC voltage, and an output signal of the first code extraction circuit and a second code extraction circuit. Output signal As input and output signal of the third code extraction circuit and those having a structure of a logic circuit for performing a logic operation.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is characterized in that a speed modulation signal can be corrected without making a vertical black line thicker than necessary. This is a circuit and has an effect of changing the range in which the speed modulation is corrected.

According to a second aspect of the present invention, there is provided a speed modulation correction signal generation circuit for generating a speed modulation correction signal from an input luminance signal, and a delay for delaying an output signal from the speed modulation correction signal generation circuit. Circuit, an addition circuit that receives an output signal of the speed modulation correction signal generation circuit as an input, a first code extraction circuit that extracts the + and-signs of the output signal of the delay circuit, and an output signal of the addition circuit. A second code extraction circuit for extracting the + and-signs, a third code extraction circuit for extracting the + and-signs of the output signal of the speed modulation correction signal generation circuit, and an output of the speed modulation correction signal generation circuit SW for switching between a signal, an output signal of the delay circuit, and a DC voltage
Circuit, an output signal of the first code extraction circuit and the second signal extraction circuit.
And a logic circuit for performing a logical operation by using the output signal of the code extraction circuit and the output signal of the third code extraction circuit as input, and applying speed modulation correction without making the black vertical line on the screen unnecessarily thick. The speed modulation signal generation circuit is characterized in that the speed modulation correction range is changed.

According to a third aspect of the present invention, there is provided a speed modulation correction signal generation circuit for generating a speed modulation correction signal from an input luminance signal, and a delay for delaying an output signal from the speed modulation correction signal generation circuit. Circuit, an addition circuit that receives an output signal of the speed modulation correction signal generation circuit as an input, a first code extraction circuit that extracts the + and-signs of the output signal of the delay circuit, and an output signal of the addition circuit. A second code extraction circuit for extracting the + and-signs, a third code extraction circuit for extracting the + and-signs of the output signal of the speed modulation correction signal generation circuit, and an output of the speed modulation correction signal generation circuit A first SW circuit for switching a signal and an output signal of the delay circuit; an inverted output signal of the first code extraction circuit;
The first AN which receives the output signal of the code extraction circuit of (3) and the output signal of the third code extraction circuit as inputs and performs an AND logic operation
A second circuit for performing an AND logic operation by using as input the D circuit, the output signal of the first code extraction circuit, the inverted output signal of the second code extraction circuit, and the output signal of the third code extraction circuit;
And a NOR circuit which receives output signals of the first and second AND circuits and performs a NOR logical operation,
And a second SW circuit for switching between an output signal of the SW circuit and a DC voltage, wherein the speed modulation correction can be performed without making the black vertical line on the screen unnecessarily thick. This is a signal generation circuit, and has an effect of changing a range in which speed modulation is corrected.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a speed modulation signal generating circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a speed modulation correction signal generation circuit that generates a speed modulation correction signal from an input luminance signal, 102 denotes a delay circuit that delays an output signal from the speed modulation correction signal generation circuit 101, and 103 denotes speed modulation. An addition circuit that receives an output signal of the correction signal generation circuit 101 as an input,
04 is a code extracting circuit for extracting the + and-signs of the output signal of the delay circuit 102, 105 is a code extracting circuit for extracting the + and-signs of the output signal of the adding circuit 103, and 106 is a signal of the speed modulation correction signal generating circuit 101. A sign extraction circuit for extracting the + and-signs of the output signal, 107 is a SW circuit for switching between the output signal of the speed modulation correction signal generation circuit 101, the output signal of the delay circuit 103, and the DC voltage, and 108 is a code extraction circuit 10
The SW circuit 10 receives the output signals of the
7, a logic circuit for outputting a signal for controlling 7, a luminance input signal 109, and a speed modulation correction output signal 110.

The operation of the speed modulation signal generating circuit configured as described above will be described below with reference to FIGS. First, FIG. 3 shows an operation of the first and second embodiments of the present invention. FIG. 3A shows a luminance input signal, and a black video signal exists in a white video signal. The state is shown. When the luminance signal 109 is input to the speed modulation correction signal generation circuit 101, a primary differential signal shown in FIG. 3B is output. An output signal when the signal is input to the delay circuit 102 is shown by a dotted line in FIG.

FIG. 3C shows an output signal after the output signal of the speed modulation correction signal generation circuit 101 and the output signal of the delay circuit 102 are input to the addition circuit 103. The code extracting circuits 104, 105, and 106 output "H" when the signal is lower than the code of the input signal, that is, the average DC level, and output "L" when the signal is higher than or equal to the DC level. 3A, the output waveform of the code extraction circuit 104 is shown in FIG. 3E, and the output waveform of the code extraction circuit 105 is shown in FIG.
(F), the output waveform of the code extraction circuit 106 is as shown in FIG.

These signals are input to a logic circuit 108,
For example, code extracting circuits 104, 105, and 106 (FIG. 3)
When (e), (f), and (d)) are all "H", the SW circuit 107 outputs the signal of the delay circuit 102, and the output signals of the code extraction circuits 104, 105, 106 are "L, H, H "
Alternatively, at the time of “L, L, H”, the SW circuit 107 outputs the DC voltage, and at other times, the SW circuit 107 outputs the signal of the speed correction signal generation circuit 101. By doing so, the speed modulation correction output signal 110 of the SW circuit 107 has a narrower correction signal width as shown in FIG. This means that the correction range on the black side is narrowed on the screen, that is, the black line is prevented from becoming unnecessarily thick.

As described above, according to this embodiment, by providing a circuit for narrowing the speed modulation correction range on the black side, it is possible to perform speed modulation correction without making black vertical lines on the screen unnecessarily thick. Can be.

(Embodiment 2) FIG. 2 is a block diagram of a speed modulation signal generating circuit according to a second embodiment of the present invention. 2, reference numeral 201 denotes a speed modulation correction signal generation circuit that generates a speed modulation correction signal from an input luminance signal, and 202 denotes a speed modulation correction signal generation circuit 2.
The delay circuit 203 delays the output signal from the output signal 01, the adder circuit 203 receives the output signal of the velocity modulation correction signal generation circuit 201 as an input, and the reference numeral 204 denotes + and-of the output signal of the delay circuit 202
A code extracting circuit for extracting a code;
Sign extracting circuit for extracting the + and-signs of the output signal of
Reference numeral 6 denotes + of the output signal of the speed modulation correction signal generation circuit 201,
A code extracting circuit for extracting a code; 207, a SW circuit for switching between an output signal of the velocity modulation correction signal generating circuit 201 and an output signal of the delay circuit 202; 208, a code extracting circuit 2
An AND circuit which performs an AND logic operation by inputting the inverted output signal of the code extraction circuit 04, the output signal of the code extraction circuit 205, and the output signal of the code extraction circuit 206, and 209, the inverted output signal of the code extraction circuit 204 and the inversion of the code extraction circuit 205 An AND circuit which receives the output signal and the output signal of the code extraction circuit 206 as input and performs an AND logic operation, and 210 is AND circuits 208 and 20
A NOR circuit 211 for inputting the output signal of No. 9 and performing a NOR logic operation, a SW circuit 211 for switching between the output signal of the SW circuit 207 and the DC voltage, a luminance input signal 212, and a speed modulation correction output signal 213.

The operation of the speed modulation signal generating circuit configured as described above will be described below with reference to FIGS. First, FIG. 3 shows an operation of the first and second embodiments of the present invention. FIG. 3A shows a luminance input signal, and a black video signal exists in a white video signal. The state is shown. When the luminance signal 212 is input to the speed modulation correction signal generation circuit 201, a primary differential signal shown in FIG. An output signal when the signal is input to the delay circuit 202 is shown by a dotted line in FIG.

FIG. 3C shows an output signal after the output signal of the speed modulation correction signal generation circuit 201 and the output signal of the delay circuit 202 have been input to the addition circuit 203. The code extracting circuits 204, 205, and 206 output "H" when the signal is lower than the code of the input signal, that is, the average DC level, and output "L" when the signal is equal to or higher than the DC level. 3A, the output waveform of the code extraction circuit 204 is shown in FIG. 3E, and the output waveform of the code extraction circuit 205 is shown in FIG.
(F), the output waveform of the code extraction circuit 206 is as shown in FIG.

Next, when the output signal of the code extraction circuit 205 is "L", the output of the SW circuit 207 is sent to the speed modulation correction signal generation circuit side, and when the output signal of the code extraction circuit 205 is "H", the SW is output. The output of the circuit 207 is applied to the delay circuit 202
To the side. Also, code extraction circuits 204, 205, 206
When (FIGS. 3 (e), (f), (d)) are "L, H, H" or "L, L, H", the AND circuit 208, 209 and the NOR circuit 210 apply the DC voltage to the SW circuit 211. , And at other times, to the SW circuit 207 side. By doing so, it can be seen that the speed modulation correction output signal 213 from the SW circuit 211 has a narrower correction signal width as shown in FIG. This means that the correction range on the black side is narrowed on the screen, that is, the black line is prevented from becoming unnecessarily thick.

As described above, according to this embodiment, by providing the circuit for narrowing the speed modulation correction range on the black side, the speed modulation correction can be performed without making the black vertical line on the screen unnecessarily thick. Can be.

[0023]

As described above, the present invention provides a speed modulation correction signal generation circuit for generating a speed modulation correction signal, a delay circuit, an addition circuit, and first and second signals for extracting + and-signs of an input signal. By providing the code extracting circuit, the SW circuit, and the logic circuit of (3), speed modulation correction can be performed without making the black vertical line on the screen unnecessarily thick.

[Brief description of the drawings]

FIG. 1 is a block diagram of a speed modulation signal generation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a velocity modulation signal generation circuit according to a second embodiment of the present invention;

FIG. 3 is an explanatory diagram of the operation of the speed modulation signal generation circuit in the first and second embodiments of the present invention.

FIG. 4 is a block diagram of a conventional speed modulation signal generation circuit.

FIG. 5 is an operation explanatory diagram of a conventional speed modulation signal generation circuit.

[Explanation of symbols]

 Reference Signs List 101 Speed modulation correction signal generation circuit 102 Delay circuit 103 Addition circuit 104 Code extraction circuit 105 Code extraction circuit 106 Code extraction circuit 107 SW circuit 108 Logic circuit 109 Luminance input signal 110 Speed modulation correction output signal

Claims (3)

[Claims] 1. A speed modulation signal generation circuit for performing speed modulation correction without making a black vertical line on a screen unnecessarily thick. 2. A speed modulation correction signal generating circuit for generating a speed modulation correction signal from an input luminance signal; a delay circuit for delaying an output signal from the speed modulation correction signal generating circuit; An adding circuit to which an output signal of the circuit is input; a first sign extracting circuit for extracting + and-signs of the output signal of the delay circuit; and a second sign extracting circuit for extracting + and-signs of the output signal of the adding circuit. Sign extraction circuit;
A third sign extraction circuit for extracting + and-signs of the output signal of the speed modulation correction signal generation circuit, an output signal of the speed modulation correction signal generation circuit, an output signal of the delay circuit, and DC
A SW circuit for switching a voltage; a logic circuit for performing a logical operation by using an output signal of the first code extraction circuit, an output signal of the second code extraction circuit, and an output signal of the third code extraction circuit as inputs And a speed modulation signal generation circuit for performing speed modulation correction without making a black vertical line on a screen unnecessarily thick. 3. A speed modulation correction signal generation circuit for generating a speed modulation correction signal from an input luminance signal, a delay circuit for delaying an output signal from the speed modulation correction signal generation circuit, and a speed modulation correction signal generation circuit. An adding circuit to which an output signal of the circuit is input; a first sign extracting circuit for extracting + and-signs of the output signal of the delay circuit; and a second sign extracting circuit for extracting + and-signs of the output signal of the adding circuit. Sign extraction circuit;
A third code extracting circuit for extracting the + and-signs of the output signal of the speed modulation correction signal generation circuit, and a first switch for switching between the output signal of the speed modulation correction signal generation circuit and the output signal of the delay circuit. A first AND circuit that receives an inverted output signal of the first code extraction circuit, an output signal of the second code extraction circuit, and an output signal of the third code extraction circuit and performs an AND logic operation And a second AND circuit which receives an inverted output signal of the first code extracting circuit, an inverted output signal of the second code extracting circuit, and an output signal of the third code extracting circuit and performs an AND logical operation. And the first,
A NOR circuit which performs an NOR logic operation by receiving an output signal of the AND circuit of the first SW circuit and an output signal of the first SW circuit.
A speed modulation signal generation circuit, comprising: a second SW circuit for switching between a C voltage and a speed modulation signal without making a black vertical line on a screen unnecessarily thick.