JPH11307601A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a semiconductor chip can be easily reduced in size and an electrical connection between a probe needle and a bonding pad can be made well. SOLUTION: In a semiconductor chip 1, an internal circuit region 2b in which an element having a predetermined function is formed and an input / output circuit region 2
and a circuit formation region 2 having a. A plurality of bonding pads 3 serving as electrodes for electrically connecting the semiconductor chip 1 and the outside of the semiconductor chip 1 are arranged on the input / output circuit area 2a along the outer periphery of the input / output circuit area 2a. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a reduced size.
The present invention relates to a semiconductor device in which electrical connection between a probe needle and a bonding pad is made well.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described with reference to the drawings. Referring to FIG. 8, a semiconductor chip 101 has a circuit forming region 102 in which elements such as transistors are formed.
However, it is located so as to occupy the majority. further,
A plurality of bonding pads 103 serving as electrodes for electrically connecting the semiconductor chip 101 and the outside of the semiconductor chip are arranged on the semiconductor chip 101. Each bonding pad 103 is arranged along the outer periphery of the semiconductor chip 101 outside the circuit formation region 102.

[0003] Each bonding pad 103 is
As shown in FIG. 9, the wiring 104 is electrically connected to the input / output circuit 102a in the circuit formation region 102, particularly. FIG. 9 is an enlarged view of a portion A shown in FIG.

A wire such as a gold wire is bonded to each of the bonding pads 103 in an assembly process, so that the bonding pads 103 are electrically connected to external terminals (not shown) such as a lead frame. Become.

By the way, this bonding pad 103
Has a role as a pad for contacting a probe needle of a tester at the time of a wafer test, in addition to a role as a pad for bonding wires.
In other words, in a wafer manufacturing process, it has a role as a pad for contacting a probe needle of a tester to evaluate whether an element formed in a circuit formation region has a predetermined function. It is.

At this time, as shown in FIGS. 9 and 10, when the probe needle 109b is brought into contact with the bonding pad 103, a flaw called a probe mark 112 remains on the surface of the bonding pad 103. In order to improve the electrical connection between the probe needle 109b and the bonding pad 103, the probe mark 112
A certain length is required along the traveling direction of the probe needle 109b.

[0007]

With the recent advancement of functions and miniaturization of semiconductor devices, more pins (electrodes) are required for semiconductor devices, and miniaturization of semiconductor chips themselves is required. It became so.

To cope with this, it is necessary to form more bonding pads in a limited area of the semiconductor chip.

However, as described above, the bonding pad needs an area for securing a probe mark during a wafer test. Ignore this,
When the area of the bonding pad is reduced, the probe needle may protrude from the bonding pad 103 in some cases. For this reason, the probe mark 112 shown in FIG. 9 or FIG. 10 sometimes protrudes from the bonding pad 103. As a result, the electrical connection between the probe needle and the bonding pad becomes unstable, and a reliable wafer test cannot be performed.

On the other hand, if the probe mark is reduced in accordance with the reduced bonding pad area, the electrical connection between the probe needle and the bonding pad becomes unstable, and the wafer test can be performed accurately. Did not.

Furthermore, in order to correspond to the probe needles in the area of the bonding pad that is reduction, spacing L ₁ nearest narrower adjacent probe needles. For this reason, it has become difficult to assemble the probe needles on the probe card, and it has become difficult to adjust the probe needles to ensure contact between the probe needles and the bonding pads.

In order to secure the electrical connectivity between the probe needle and the bonding pad portion and the ease of assembling and adjusting the probe needle as described above, a certain area is required for the bonding pad. However, the semiconductor chip cannot be easily reduced in size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the size of a semiconductor chip can be easily reduced, and good electrical connectivity between a probe needle and a bonding pad can be obtained. An object of the present invention is to provide a semiconductor device having a wire bonding pad.

[0014]

A semiconductor device according to one aspect of the present invention is a semiconductor device having a semiconductor chip, and the semiconductor chip is formed on a surface of a semiconductor substrate and has a predetermined function. And a plurality of bonding pads for performing wire bonding. The bonding pad portion is arranged in the region of the circuit forming portion.

According to this structure, since the bonding pad portion is arranged in the region of the circuit forming portion,
There is no need to secure the bonding pad area separately from the circuit forming area, and the semiconductor chip can be easily reduced in size. Also, in response to the shrinking of semiconductor chips,
It is not necessary to reduce the size of the bonding pad portion, and a desired area is secured, so that good electrical connectivity between the probe needle and the bonding pad portion can be obtained during a wafer test.

Preferably, the planar shape of each bonding pad portion is a rectangular shape having a long side in a direction in which a probe mark generated in contact with the probe needle extends.

In this case, the contact between the probe needle and the bonding pad portion is further improved, and the electrical connectivity is further improved.

More preferably, the bonding pads are arranged offset from each other in the direction in which the long sides extend.

In this case, the positions of the probe needles that are in contact with the adjacent bonding pad portions are shifted from each other, thereby facilitating the assembly and adjustment of the probe needles.

More preferably, the plurality of bonding pad portions are arranged in a staggered manner. In this case, the probe needles are also arranged in a staggered manner with respect to the arrangement of the bonding pad portions, so that assembly and adjustment of the probe needles are further facilitated.

Preferably, each of the bonding pad portions has a first region to which a wire is bonded and a second region to which a probe needle is applied.

In this case, the region to which the probe needle is applied and the region to which the wire is bonded are distinguished, so that the wire can be bonded while avoiding a portion having a probe mark. Is improved.

[0023]

First Embodiment A semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 1, a semiconductor chip 1 includes:
A circuit formation region 2 including an element having a predetermined function such as a transistor is formed on the surface of the silicon substrate so as to substantially occupy the region of the semiconductor chip 1. The circuit formation region 2 is an internal circuit formation region 2 for performing substantial processing.
b, and an input / output circuit area 2a composed of a TTL (Transistor Transitor Logic) circuit or the like. In the circuit formation region 2, the semiconductor chip 1 and the semiconductor chip 1
A plurality of bonding pads 3 serving as electrodes for electrically connecting to the outside are formed. Each bonding pad 3 is particularly arranged on the input / output circuit area 2a. FIG. 2 is an enlarged view of a portion A shown in FIG.

Each bonding pad 3 has a role as a pad for contacting a probe needle of a tester during a wafer test and a role as a pad for bonding wires as described in the section of the prior art. Have.

Here, the wafer test will be described with reference to the drawings. Referring to FIG. 2, the test head 56 of the tester
A probe card 59 is arranged below the baseboard with a performance board 57 and a pogo pin ring 58 interposed therebetween. The probe card 59 includes a probe card substrate 59a and a probe needle 9. The probe needle 9 is assembled and adjusted on the probe card substrate 59a so as to correspond to the arrangement of the bonding pads of the wafer to be measured.

On the other hand, a wafer 60 for measurement is placed on the wafer chuck 61. The wafer test is performed by bringing the probe needles 9 into contact with the bonding pads 103 and electrically connecting the semiconductor chips formed on the wafer 60 and the tester, respectively.

In the semiconductor device described above, at this time, FIG.
As shown in (1), by bringing the probe needle into contact with the bonding pad 3, a probe mark 12 remains on the surface of the bonding pad 3. In order to maintain good electrical contact between the probe needle and the bonding pad 3, it is desirable that the planar shape of the bonding pad 3 be a rectangle having a long side in the direction in which the probe mark 12 extends. For example, when the length of the probe mark 12 in the longitudinal direction is about 40 μm, it is desirable that the length of the long side is about 100 μm. Accordingly, even if the distance L ₁ of the bonding pads 3 adjacent contracted, sufficient probe mark 1
2, the electrical connection between the probe needle and the bonding pad 3 is improved, and a stable wafer test can be performed.

As shown in FIG. 4, below the bonding pad 3, an element forming layer 4 in which elements such as transistors are formed and a metal wiring layer 5 such as aluminum wiring are formed.
The input / output circuit area 2a including the above is located. For this reason, by setting the thickness t of the bonding pad 3 to about 15000 ° and making it sufficiently thicker than the conventional bonding pad, it is possible to suppress the damage at the time of a wafer test or wire bonding from reaching the input / output circuit area 2a. It is desirable to do. Further, the pressure of the probe needle during the wafer test is increased from 10 g / pin to 5 g / pin.
By lowering to pin, damage to the input / output circuit region 2a can be further suppressed.

Further, since the input / output circuit region 2a is located immediately below the bonding pad 3, the bonding pad 3 and the element forming layer 4 can be electrically connected to each other by a wiring having a shortest distance. Thereby, the electrical characteristics of the input / output circuit region can be improved.

By arranging the bonding pad 3 in the input / output circuit area 2a of the circuit formation area 2, it is necessary to secure an area for forming the bonding pad 3 on the silicon substrate separately from the circuit formation area 2. There is no. As a result, as shown in FIG. 1, the semiconductor chip 1 can be more easily reduced in size than the conventional semiconductor chip 101 without being limited by the size and arrangement of the bonding pads 3.

Second Embodiment In the semiconductor device according to the first embodiment, each bonding pad 3 is arranged on the input / output circuit area 2a along the outer periphery. In this case, as the probe needle, it is necessary to assemble the probe to correspond to the distance L ₁ between adjacent bonding pads on the probe card. Therefore, depending on the distance L _1, which may be assemble the probe needles in the probe card becomes difficult. Therefore, a semiconductor device having a bonding pad for solving this problem will be described with reference to the drawings.

Referring to FIG. 5, in the semiconductor device according to the second embodiment, in particular, bonding pads 3a are arranged in a staggered manner along the outer periphery on input / output circuit region 2a. Other configurations are the same as those of the semiconductor device described in the first embodiment.

[0033] In this semiconductor device, even if closely spaced L ₁ between adjacent bonding pads 3a, and the bonding pad 3a, the distance L ₂ between the bonding pads located long side right beside the bonding pads 3a, bonding Because it is longer than the short side of the pad 3a,
Assembly and adjustment of the probe needle to the probe card becomes easier. Thus, the electrical contact between the probe needle and the bonding pad 3a becomes better, and a stable wafer test can be performed.

Third Embodiment In each of the bonding pads 3 and 3a of the semiconductor device according to the first and second embodiments, a wire is bonded to the probe mark 12 in the wire bonding step. Therefore, it is assumed that the wires are not properly bonded to the bonding pads 3 and 3a due to the presence of the probe marks. Therefore, a semiconductor device having a bonding pad for solving this problem will be described with reference to the drawings.

Referring to FIGS. 6 and 7, a third embodiment will be described.
In the semiconductor device according to the above, each bonding pad 3b
It is arranged on the input / output circuit area 2a along its outer periphery. However, unlike the semiconductor device according to the first embodiment, each bonding pad 3b has a probe needle contact area 6a where a probe mark 12 is formed and a wire bonding area 6b where a wire is bonded.
It has longer long sides. Moreover, the probe needle contact areas 6a are arranged in a staggered manner as shown in FIG. Other configurations are the same as those of the semiconductor device described in the first embodiment.

In this semiconductor device, since a portion for forming the probe mark 12 (probe needle contact region 6a) and a portion for bonding the wire (wire bonding region 6b) are distinguished, the wire is connected to the bonding pad 3b.
Can be connected well. Moreover, Embodiment 4
As in the case of the semiconductor device according to the first aspect, assembling and adjustment of the probe needle to the probe card become easier.

In the second and third embodiments,
The arrangement of the bonding pads or the parts to be bonded is exemplified by a staggered arrangement, but is not limited thereto. Even if such a portion is arranged, the positions of the probe needles that are in contact with the bonding pads are shifted from each other, so that the assembly and adjustment of the probe needles become easy, and a stable wafer test can be performed.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0039]

According to the semiconductor device of one aspect of the present invention, since the bonding pad portion is arranged in the region of the circuit forming portion, the region of the bonding pad portion is separated from the region of the circuit forming portion. There is no need to secure them, and the semiconductor chip can be easily reduced in size. In addition, it is not necessary to reduce the size of the bonding pad in accordance with the reduction in the size of the semiconductor chip, and a desired area can be secured. Obtainable.

Preferably, the planar shape of each bonding pad portion is a rectangular shape having a long side in a direction in which a probe mark generated in contact with the probe needle extends.
The contact between the probe needle and the bonding pad portion is further improved, and the electrical connectivity is further improved.

More preferably, the bonding pads are displaced from each other in the direction in which the long sides extend, so that the positions of the probe needles that contact adjacent bonding pad portions are displaced from each other. Adjustment becomes easy.

More preferably, the plurality of bonding pad portions are arranged in a staggered manner, so that the probe needles are also arranged in a staggered manner with respect to the arrangement of the bonding pad portions. Adjustment becomes easier.

Preferably, each bonding pad has a first region to which a wire is bonded and a second region to which a probe needle is applied, so that the region to which the probe needle is applied and the wire are bonded. The region to be probed is distinguished from the region to be bonded, so that the wire can be bonded while avoiding the portion with the probe mark, and the connection between the wire and the bonding pad is improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a wafer test method.

FIG. 3 is a partially enlarged plan view of the semiconductor device shown in FIG. 1;

4 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG.

FIG. 5 is a partially enlarged plan view of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a partially enlarged plan view of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a sectional view of the semiconductor device shown in FIG. 6;

FIG. 8 is a plan view of a conventional semiconductor device.

9 is a partially enlarged plan view of the semiconductor device shown in FIG.

FIG. 10 is a diagram showing a state of contact between a semiconductor chip and a probe needle in a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semiconductor chip, 2 circuit formation area, 2a input / output circuit area, 2b internal circuit area, 3, 3a, 3b bonding pad, 9 probe needle, 4 element formation layer, 5
Metal wiring layer, 6a probe needle contact area, 6b wire bonding area, 12 probe marks.

Claims (5)

[Claims] 1. A semiconductor device comprising a semiconductor chip, wherein the semiconductor chip includes a circuit forming portion having a predetermined function formed on a surface of a semiconductor substrate, and a plurality of bonding pad portions for performing wire bonding. A semiconductor device, wherein the bonding pad portion is disposed in a region of the circuit forming portion. 2. The semiconductor device according to claim 1, wherein the planar shape of each of the bonding pad portions is a rectangular shape having a long side in a direction in which a probe mark generated in contact with a probe needle extends. 3. The semiconductor device according to claim 2, wherein said bonding pad portions are arranged so as to be shifted from each other in a direction in which a long side extends. 4. The semiconductor device according to claim 3, wherein said plurality of bonding pad portions are arranged in a staggered manner. 5. The semiconductor device according to claim 2, wherein each of said bonding pad portions has a first region to which a wire is bonded and a second region to which a probe needle is applied. .