JPH11307938A - Core board, its manufacturing method, and multi-layer printed circuit board - Google Patents
Core board, its manufacturing method, and multi-layer printed circuit boardInfo
- Publication number
- JPH11307938A JPH11307938A JP10124207A JP12420798A JPH11307938A JP H11307938 A JPH11307938 A JP H11307938A JP 10124207 A JP10124207 A JP 10124207A JP 12420798 A JP12420798 A JP 12420798A JP H11307938 A JPH11307938 A JP H11307938A
- Authority
- JP
- Japan
- Prior art keywords
- core substrate
- resin
- conductive
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 52
- 239000011347 resin Substances 0.000 claims abstract description 52
- 238000007747 plating Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 103
- 239000010410 layer Substances 0.000 claims description 60
- 239000004020 conductor Substances 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims description 18
- 229920005992 thermoplastic resin Polymers 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000007772 electroless plating Methods 0.000 description 11
- 239000000243 solution Substances 0.000 description 11
- 239000003795 chemical substances by application Substances 0.000 description 10
- 238000009413 insulation Methods 0.000 description 10
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 9
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 9
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 8
- 239000000945 filler Substances 0.000 description 8
- 239000002245 particle Substances 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000003054 catalyst Substances 0.000 description 6
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 239000002994 raw material Substances 0.000 description 6
- 239000011342 resin composition Substances 0.000 description 6
- 238000002156 mixing Methods 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 229910000365 copper sulfate Inorganic materials 0.000 description 4
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000003756 stirring Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- UMGDCJDMYOKAJW-UHFFFAOYSA-N thiourea Chemical compound NC(N)=S UMGDCJDMYOKAJW-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000000654 additive Substances 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 239000000178 monomer Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- BTJPUDCSZVCXFQ-UHFFFAOYSA-N 2,4-diethylthioxanthen-9-one Chemical compound C1=CC=C2C(=O)C3=CC(CC)=CC(CC)=C3SC2=C1 BTJPUDCSZVCXFQ-UHFFFAOYSA-N 0.000 description 2
- QTWJRLJHJPIABL-UHFFFAOYSA-N 2-methylphenol;3-methylphenol;4-methylphenol Chemical compound CC1=CC=C(O)C=C1.CC1=CC=CC(O)=C1.CC1=CC=CC=C1O QTWJRLJHJPIABL-UHFFFAOYSA-N 0.000 description 2
- KWSLGOVYXMQPPX-UHFFFAOYSA-N 5-[3-(trifluoromethyl)phenyl]-2h-tetrazole Chemical compound FC(F)(F)C1=CC=CC(C2=NNN=N2)=C1 KWSLGOVYXMQPPX-UHFFFAOYSA-N 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 2
- 229910017755 Cu-Sn Inorganic materials 0.000 description 2
- 229910017927 Cu—Sn Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- OWYWGLHRNBIFJP-UHFFFAOYSA-N Ipazine Chemical compound CCN(CC)C1=NC(Cl)=NC(NC(C)C)=N1 OWYWGLHRNBIFJP-UHFFFAOYSA-N 0.000 description 2
- 229910018104 Ni-P Inorganic materials 0.000 description 2
- 229910018536 Ni—P Inorganic materials 0.000 description 2
- 229920012266 Poly(ether sulfone) PES Polymers 0.000 description 2
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- XSQUKJJJFZCRTK-UHFFFAOYSA-N Urea Natural products NC(N)=O XSQUKJJJFZCRTK-UHFFFAOYSA-N 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000002518 antifoaming agent Substances 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 239000011324 bead Substances 0.000 description 2
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 2
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 2
- 239000004327 boric acid Substances 0.000 description 2
- KRVSOGSZCMJSLX-UHFFFAOYSA-L chromic acid Substances O[Cr](O)(=O)=O KRVSOGSZCMJSLX-UHFFFAOYSA-L 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical group [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 229930003836 cresol Natural products 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- AWJWCTOOIBYHON-UHFFFAOYSA-N furo[3,4-b]pyrazine-5,7-dione Chemical compound C1=CN=C2C(=O)OC(=O)C2=N1 AWJWCTOOIBYHON-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- LGQLOGILCSXPEA-UHFFFAOYSA-L nickel sulfate Chemical compound [Ni+2].[O-]S([O-])(=O)=O LGQLOGILCSXPEA-UHFFFAOYSA-L 0.000 description 2
- 229910000363 nickel(II) sulfate Inorganic materials 0.000 description 2
- 229920003986 novolac Polymers 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000003504 photosensitizing agent Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- -1 polytetrafluoroethylene Polymers 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- 229910001379 sodium hypophosphite Inorganic materials 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000004094 surface-active agent Substances 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- ROFVEXUMMXZLPA-UHFFFAOYSA-N Bipyridyl Chemical group N1=CC=CC=C1C1=CC=CC=N1 ROFVEXUMMXZLPA-UHFFFAOYSA-N 0.000 description 1
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 1
- JUWOETZNAMLKMG-UHFFFAOYSA-N [P].[Ni].[Cu] Chemical compound [P].[Ni].[Cu] JUWOETZNAMLKMG-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 230000033116 oxidation-reduction process Effects 0.000 description 1
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
- SUKJFIGYRHOWBL-UHFFFAOYSA-N sodium hypochlorite Chemical compound [Na+].Cl[O-] SUKJFIGYRHOWBL-UHFFFAOYSA-N 0.000 description 1
- 239000012798 spherical particle Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、層間樹脂絶縁層
とバイアホール及び導体回路とを交互に積層してなる多
層プリント配線板用のコア基板、該コア基板の製造方
法、及び、当該コア基板を用いる多層プリント配線板に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a core substrate for a multilayer printed wiring board in which interlayer resin insulating layers, via holes and conductive circuits are alternately laminated, a method of manufacturing the core substrate, and the core substrate. The present invention relates to a multilayer printed wiring board using the same.
【０００２】[0002]
【従来の技術】ビルドアップ式の多層プリント配線板で
は、図９（Ａ）に示すようにコア基板２３０の両面に層
間樹脂絶縁層２５０と導体層２５８とを積層して成り、
層間樹脂絶縁層に形成したバイアホール２６０にて上下
層の接続を行っている。ここで、コア基板２３０として
は、ガラス繊維に樹脂を含浸させてたプリプレグを複数
枚積層した樹脂基板を用いている。コア基板２３０に設
けられる上下層の接続用のスルーホール２３６は、ドリ
ルで穿設された通孔３１６内にめっき膜３１８を析出さ
せることにより形成されている。2. Description of the Related Art A build-up type multilayer printed wiring board is formed by laminating an interlayer resin insulating layer 250 and a conductor layer 258 on both sides of a core substrate 230 as shown in FIG.
The upper and lower layers are connected by via holes 260 formed in the interlayer resin insulating layer. Here, as the core substrate 230, a resin substrate obtained by laminating a plurality of prepregs obtained by impregnating a glass fiber with a resin is used. The through holes 236 for connecting the upper and lower layers provided in the core substrate 230 are formed by depositing a plating film 318 in a through hole 316 formed by a drill.
【０００３】図９（Ａ）に示す多層プリント配線板のＢ
−Ｂ横断面、即ち、コア基板２３０の上面を図９（Ｂ）
に示す。スルーホール２３６の周囲にはランド２３６ａ
が周設され、該ランド２３６ａには、半円状のパッド２
３６ｂが取り付けらている。そして、該半円状のパッド
２３６ｂに、図９（Ａ）に示すようにバイアホール２６
０が接続されている。The multilayer printed wiring board B shown in FIG.
-B cross section, that is, the upper surface of the core substrate 230 is shown in FIG.
Shown in A land 236a is provided around the through hole 236.
Is provided around the land 236a.
36b is attached. Then, the via holes 26 are formed in the semicircular pads 236b as shown in FIG.
0 is connected.
【０００４】[0004]
【発明が解決しようとする課題】従来技術のコア基板で
は、０．３mm径以下のスルーホールを形成することがで
きなかった。即ち、ドリルでは、０．３mm以下の通孔を
穿設することが困難であるため、これがスルーホールを
直径を決定し、コア基板のファインピッチ化を阻む原因
となっていた。In the prior art core substrate, a through hole having a diameter of 0.3 mm or less could not be formed. That is, since it is difficult to form a through hole having a diameter of 0.3 mm or less with a drill, this determines the diameter of the through hole and hinders the fine pitch of the core substrate.
【０００５】また、図９（Ｂ）に示す形状のランド２３
６ａにパッド２３６ｂを付加する構成では、他のスルー
ホール２３６に配設されたランド及びパッドとの絶縁を
保つために、スルーホール相互の間隔を広げざるを得
ず、この点からもスルーホールのファインピッチを行い
得なかった。A land 23 having a shape shown in FIG.
In the configuration in which the pad 236b is added to the through hole 6a, the interval between the through holes must be increased in order to maintain insulation from the lands and pads arranged in the other through holes 236. Fine pitch could not be performed.
【０００６】本発明は、上述した課題を解決するために
なされたものであり、その目的とするところは、微細な
ピッチで上下の接続を取り得るコア基板及びコア基板の
製造方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a core substrate capable of making up and down connections at a fine pitch and a method of manufacturing the core substrate. It is in.
【０００７】本発明は、上述した課題を解決するために
なされたものであり、その目的とするところは、微細な
ピッチで上下の接続を取り得るコア基板を用い、廉価に
構成できる多層プリント配線板を提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multi-layer printed wiring which can be formed at a low cost by using a core substrate capable of connecting up and down at a fine pitch. To provide a board.
【０００８】[0008]
【課題を解決するための手段】請求項１のコア基板は、
上記目的を達成するため、規則的に配列した導体柱を樹
脂で固定してなることを技術的特徴とする。According to the first aspect of the present invention, a core substrate is provided.
In order to achieve the above object, a technical feature is that regularly arranged conductor columns are fixed with resin.
【０００９】請求項２のコア基板は、請求項１におい
て、前記導電柱の径は、０．２５mm以下で０．０５mm以
上であることを技術的特徴とする。A second aspect of the present invention is a core substrate according to the first aspect, wherein the conductive pillar has a diameter of not more than 0.25 mm and not less than 0.05 mm.
【００１０】請求項３のコア基板は、請求項１又は２に
おいて、前記樹脂は、熱可塑性樹脂であることを技術的
特徴とする。A third aspect of the present invention provides the core substrate according to the first or second aspect, wherein the resin is a thermoplastic resin.
【００１１】請求項４のコア基板は、請求項１〜３にお
いて、前記導電柱をコア基板の水平方向に対して対称に
なるように規則的に配列したことを技術的特徴とする。A fourth aspect of the present invention is the core substrate according to the first to third aspects, wherein the conductive columns are regularly arranged so as to be symmetric with respect to the horizontal direction of the core substrate.
【００１２】また、請求項５のコア基板の製造方法は、
以下の（ａ）〜（ｄ）の工程を含むことを技術的特徴と
する。 （ａ）導電体の上に規則的に配列した開口を有するレジ
ストを形成する工程、（ｂ）前記開口にめっきを施し導
電柱を形成する工程、（ｃ）前記レジストを除去する工
程、（ｄ）前記導電柱間に樹脂を充填する工程。Further, the method of manufacturing a core substrate according to claim 5 is
Technical features include the following steps (a) to (d). (A) a step of forming a resist having openings regularly arranged on a conductor, (b) a step of plating the openings to form conductive columns, (c) a step of removing the resist, (d) A) filling a resin between the conductive columns;
【００１３】請求項６は、コア基板に、層間樹脂絶縁層
とバイアホール及び導体回路とを交互に積層してなる多
層プリント配線板であって、前記コア基板が規則的に配
列した導体柱を樹脂で固定してなり、前記コア基板の前
記導電柱の直上に前記バイアホールが形成されているこ
とを技術的特徴とする。According to a sixth aspect of the present invention, there is provided a multilayer printed wiring board in which an interlayer resin insulating layer, via holes, and conductive circuits are alternately laminated on a core substrate. It is technically characterized in that the via hole is formed just above the conductive pillar of the core substrate by being fixed with resin.
【００１４】請求項７は、請求項６において、前記コア
基板の導体柱の内の幾つかが使用されていないことを技
術的特徴とする。A seventh aspect of the present invention is characterized in that, in the sixth aspect, some of the conductor columns of the core substrate are not used.
【００１５】請求項１のコア基板は、スルーホールとし
ての機能を有する導体柱を樹脂で固定してなり、ドリル
により通孔を穿設してスルーホールを形成する必要がな
いため、導電柱を用いることで微細なピッチで上下の接
続を取ることができる。また、導電柱を規則的に配列し
てあるため、コア基板に反り等を発生させず、生産性が
高い。According to the first aspect of the present invention, the conductive pillar having a function as a through hole is fixed with resin, and it is not necessary to form a through hole by drilling a through hole. By using it, the upper and lower connections can be made at a fine pitch. In addition, since the conductive columns are regularly arranged, the core substrate does not warp or the like, and the productivity is high.
【００１６】請求項２のコア基板の導電柱の径は、０．
２５mm以下である。ここで、０．２５mmを越える場合
は、ドリルによりスルーホールを形成することが可能で
ある。他方、導電柱の径は、０．０５mm以上である。こ
れは、コア基板の厚み（例えば、０．３mm）の分の高さ
の導電柱を、レジストの開口内に形成する際に、開口の
径が０．０５mm以下であると、めっき液の回り込みが悪
く導電柱の形成が困難なためである。According to a second aspect of the present invention, the diameter of the conductive pillar of the core substrate is set to 0.1.
It is 25 mm or less. Here, when it exceeds 0.25 mm, a through hole can be formed by a drill. On the other hand, the diameter of the conductive pillar is 0.05 mm or more. This is because when a conductive pillar having a height corresponding to the thickness of the core substrate (for example, 0.3 mm) is formed in the opening of the resist, if the diameter of the opening is 0.05 mm or less, the plating solution flows around. This is because it is difficult to form conductive columns.
【００１７】請求項３のコア基板では、導体柱を固定す
る樹脂が、熱可塑性であるため、誘電率等の電気特性が
良好であり、高周波用の多層プリント配線板に用いるこ
とが可能となる。According to the third aspect of the present invention, since the resin for fixing the conductor pillars is thermoplastic, the electrical properties such as the dielectric constant are good, and the core substrate can be used for a high-frequency multilayer printed wiring board. .
【００１８】請求項４のコア基板では、導電柱をコア基
板の水平方向に対して対称になるように規則的に配列し
てあるため、コア基板に反り等を発生させることがな
い。In the core substrate according to the fourth aspect, since the conductive columns are regularly arranged so as to be symmetrical with respect to the horizontal direction of the core substrate, the core substrate does not warp.
【００１９】請求項５のコア基板の製造方法では、規則
的に配列した開口を有するレジストを形成し、開口にめ
っきを施しスルーホールとして機能する導電柱を規則的
に配列させて形成し、導電柱を樹脂で固めてコア基板を
形成する。ここで、レジストに設ける開口は、スルーホ
ール形成の際に用いたドリルによる通孔よりも小径に形
成できるため、該小径の開口内に形成した導電柱を用い
ることで、微細なピッチで上下の接続を取ることができ
る。また、導電柱を規則的に配列してあるため、コア基
板に反り等を発生させず、生産性が高い。According to a fifth aspect of the present invention, there is provided a method for manufacturing a core substrate, comprising forming a resist having regularly arranged openings, plating the openings, and regularly forming conductive columns functioning as through holes. The pillars are solidified with resin to form a core substrate. Here, since the opening provided in the resist can be formed to have a smaller diameter than the through hole formed by the drill used in forming the through hole, by using the conductive pillar formed in the small-diameter opening, the upper and lower portions can be formed at a fine pitch. You can take a connection. In addition, since the conductive columns are regularly arranged, the core substrate does not warp or the like, and the productivity is high.
【００２０】請求項６の多層プリント配線板では、コア
基板が導体柱を樹脂で固定してなり、ドリルにより通孔
を穿設してスルーホールを形成する必要がないため、微
細なピッチで上下の接続を取ることができる。ここで、
導電柱により微細なピッチで上下の接続をとっても、コ
ア基板上にバイアホールとの接続用のパッドを形成して
は、該パッドを設けることで導電柱を微細なピッチで設
けられなくなる。このため、請求項６の構成では、コア
基板の導電柱の直上にバイアホールを形成することで、
パッドをなくし、微細なピッチで上下の接続を取ること
を可能にする。また、導電柱を規則的に配列してあるた
め、反り等を発生させない。特に、規則的に配列した導
体柱を樹脂で固定した汎用のコア基板を用いるため、廉
価に構成することができる。In the multilayer printed wiring board according to the sixth aspect, since the core substrate is formed by fixing the conductor pillars with resin and there is no need to form a through hole by drilling, a vertical hole is formed at a fine pitch. Can take a connection. here,
Even if the upper and lower connections are made at a fine pitch by the conductive pillars, the pads for connecting to the via holes are formed on the core substrate, and by providing the pads, the conductive pillars cannot be provided at a fine pitch. For this reason, in the configuration of claim 6, by forming a via hole immediately above the conductive pillar of the core substrate,
Eliminates pads and allows up and down connections with fine pitch. Further, since the conductive columns are regularly arranged, no warpage or the like is generated. In particular, since a general-purpose core substrate in which regularly arranged conductor pillars are fixed with resin is used, the configuration can be made at a low cost.
【００２１】請求項７の多層プリント配線板では、コア
基板の導体柱の内の幾つかを使用しないことで、汎用の
コア基板を用いることが可能になり、廉価に構成するこ
とができる。In the multilayer printed wiring board according to the seventh aspect, since some of the conductor pillars of the core substrate are not used, a general-purpose core substrate can be used, and the configuration can be reduced.
【００２２】[0022]
【発明の実施の形態】以下、本発明の実施形態に係る多
層プリント配線板及び該多層プリント配線板に用いるコ
ア基板について図を参照して説明する。図２（Ｆ）は１
実施態様に係るコア基板の断面を示し、図８は、該コア
基板のＡ矢視、即ち、平面図である。コア基板３０は、
円柱条の導電柱１４を樹脂１６により固定してなる。該
導電柱１４は、従来技術のコア基板のスルーホールの機
能を果たし、コア基板の水平方向に対して対称になるよ
うに規則的に配列され、これにより、熱膨張率の異なる
導電柱と樹脂からなるコア基板がヒートサイクルに晒さ
れた際に反りが発生しないよう構成されている。このコ
ア基板３０は、汎用品として設計されている。即ち、従
来技術のコア基板は、各多層プリント配線板毎に専用設
計していたのに対して、本実施形態のコア基板は、種々
の多層プリント配線板に用い得るように設計されてい
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer printed wiring board according to an embodiment of the present invention and a core substrate used for the multilayer printed wiring board will be described below with reference to the drawings. FIG.
FIG. 8 is a cross-sectional view of the core substrate according to the embodiment, and FIG. 8 is a plan view of the core substrate as viewed from an arrow A. The core substrate 30
The conductive strip 14 is fixed by a resin 16. The conductive pillars 14 function as through holes of the core board of the prior art, and are regularly arranged so as to be symmetrical with respect to the horizontal direction of the core board. When the core substrate is exposed to a heat cycle, the core substrate is not warped. The core substrate 30 is designed as a general-purpose product. That is, the core board of the prior art is designed exclusively for each multilayer printed wiring board, whereas the core board of the present embodiment is designed so that it can be used for various multilayer printed wiring boards.
【００２３】コア基板３０は、厚さ０．３mmに形成され
ている。そして、導電柱１４は、直径０．１mmに形成さ
れている。ここで、該導電柱１４は、０．２５mm以下で
０．０５mm以上であることが望ましい。これは、０．２
５mmを越える場合は、従来技術のようにドリルによりス
ルーホールを形成することが可能であるからである。他
方、導電柱の径は、０．０５mm以上であることが望まし
い。これは、コア基板の厚み（０．３mm）の分の高さの
導電柱を、後述するようにレジストの開口内に形成する
際に、開口径が０．０５mm以下であると、めっき液の回
り込みが悪く導電柱の形成が困難なためである。The core substrate 30 is formed with a thickness of 0.3 mm. The conductive pillar 14 has a diameter of 0.1 mm. Here, it is desirable that the conductive pillars 14 are not more than 0.25 mm and not less than 0.05 mm. This is 0.2
If it exceeds 5 mm, it is possible to form a through hole by drilling as in the prior art. On the other hand, the diameter of the conductive pillar is desirably 0.05 mm or more. This is because when a conductive pillar having a height corresponding to the thickness (0.3 mm) of the core substrate is formed in the opening of the resist as described later, if the opening diameter is 0.05 mm or less, the plating solution is This is because the wraparound is poor and it is difficult to form conductive columns.
【００２４】導体柱を固定する樹脂は、フッ素材脂（例
えば、ポリテトラフルオロエチレン）等の熱可塑性樹脂
を用いることが望ましい。これは、熱可塑性樹脂は、誘
電率等の電気特性が良好であり、高周波用の多層プリン
ト配線板に好適に用い得るためである。It is desirable to use a thermoplastic resin such as a fluororesin (for example, polytetrafluoroethylene) as the resin for fixing the conductor columns. This is because the thermoplastic resin has good electrical characteristics such as a dielectric constant and can be suitably used for a high-frequency multilayer printed wiring board.
【００２５】図７は、該コア基板３０を用いた多層プリ
ント配線板の断面を示している。多層コア基板３０の表
面及び裏面にビルドアップ配線層９０Ａ、９０Ｂが形成
されている。該ビルトアップ層９０Ａ、９０Ｂは、バイ
アホール６０及び導体回路５８の形成された層間樹脂絶
縁層５０と、バイアホール１６０及び導体回路１５８の
形成された層間樹脂絶縁層１５０と、からなる。FIG. 7 shows a cross section of a multilayer printed wiring board using the core substrate 30. Build-up wiring layers 90A and 90B are formed on the front and back surfaces of the multilayer core substrate 30. The built-up layers 90A and 90B include an interlayer resin insulation layer 50 having via holes 60 and conductor circuits 58 formed therein, and an interlayer resin insulation layer 150 having via holes 160 and conductor circuits 158 formed therein.
【００２６】表面側には、ＩＣチップのバンプ（図示せ
ず）へ接続するための半田バンプ７６Ｕが形成され、裏
面側には、マザーボードのバンプ（図示せず）へ接続す
るための半田バンプ７６Ｄが形成されている。多層プリ
ント配線板内では、ＩＣチップへ接続する半田バンプ７
６Ｕからの導体回路が、マザーボード側へ接続する半田
バンプ７６Ｄへ接続されている。表側のビルトアップ層
９０Ａと裏側のビルトアップ層９０Ｂとは、コア基板３
０に形成された導電柱１４を介して接続されている。On the front side, solder bumps 76U for connection to bumps (not shown) of the IC chip are formed, and on the back side, solder bumps 76D for connection to bumps (not shown) of the motherboard are formed. Are formed. In a multilayer printed wiring board, solder bumps 7 connected to IC chips
A conductor circuit from 6U is connected to a solder bump 76D connected to the motherboard. The front side built-up layer 90A and the back side built-up layer 90B are
It is connected via a conductive pillar 14 formed at zero.
【００２７】ここで、コア基板の導電柱１４の直上に
は、導体層２４を介してバイアホール６０が接続されて
いる。そして、層間樹脂絶縁層５０に配設される導体回
路５８は、図中に示さないバイアホール６０へ接続され
ている。該導体回路５８は、また、上層のバイアホール
１６０へ接続され、該バイアホール１６０、或いは、バ
イアホール１６０（図中に示さない）へ接続された導体
回路１５８に半田バンプ７６Ｕ、７６Ｄが形成されてい
る。Here, via holes 60 are connected via conductive layers 24 directly above the conductive pillars 14 of the core substrate. The conductor circuit 58 provided in the interlayer resin insulation layer 50 is connected to a via hole 60 not shown in the figure. The conductor circuit 58 is also connected to an upper via hole 160, and solder bumps 76U and 76D are formed on the via hole 160 or on a conductor circuit 158 connected to the via hole 160 (not shown in the figure). ing.
【００２８】この多層プリント配線板においては、バイ
アホールの機能を果たす導電柱１４の直上にバイアホー
ル６０を形成することで、図９（Ｂ）を参照して上述し
た従来技術のバイアホール接続用のパッドをなくしてい
る。即ち、コア基板３０の表面にパッドを設けないこと
で、微細なピッチで導電柱を配設し、上下の接続を取っ
ている。また、図７中の左端の導電柱１４αには、導体
層２４及び導体回路２５が接続されておらず、使用され
ないブランイドとなっている。このように、コア基板の
幾つかの導電柱を使用しないことで、汎用のコア基板３
０にて種々の多層プリント配線板を形成できるように
し、同形状のコア基板の生産数を多くすることで生産性
を高め、コア基板、即ち、多層プリント配線板の製造コ
ストを低減している。In this multilayer printed wiring board, the via hole 60 is formed directly above the conductive pillar 14 which functions as a via hole, thereby forming the via hole connection of the prior art described above with reference to FIG. The pads are gone. That is, since no pads are provided on the surface of the core substrate 30, conductive columns are arranged at a fine pitch, and the upper and lower connections are established. In addition, the conductor layer 24 and the conductor circuit 25 are not connected to the conductive pillar 14α at the left end in FIG. As described above, by not using some conductive pillars of the core substrate, the general-purpose core substrate 3 can be used.
0 enables various multilayer printed wiring boards to be formed, increases productivity by increasing the number of core substrates of the same shape, and reduces the manufacturing cost of the core substrate, that is, the multilayer printed wiring board. .
【００２９】引き続き、図２（Ｆ）に示すコア基板の製
造方法について図１を参照して具体的に説明する。先
ず、図１（Ａ）に示すように銅箔１０の上に市販の厚さ
０．３mmのレジストフィルム１１を密着させる。次に、
図８を参照して上述した規則的に配列された導電柱を形
成し得る０．１mmφの黒円が印刷されたフォトマスクフ
ィルム（図示せず）を密着させ、超高圧水銀灯により５
００mJ／cm2 で露光する。これをＤＭＴＧ溶液でスプレ
ー現像することにより、図１（Ｂ）に示すようにフォト
マスクフィルムに相当する寸法精度に優れた０．１mmφ
の開口（導電柱形成用開口）１２ａを有する厚さ０．３
mmのレジスト１２を形成する。引き続き、下記条件で銅
箔１０に電流を流し、開口１２ａ内に電解銅めっきを施
し、高さ０．３mmの導電柱１４を形成する。なお、レジ
スト１２に設ける開口１２ａは、従来技術で用いられて
いたスルーホール形成の際に用いたドリルによる通孔よ
りも小径に形成できるため、該小径の開口１２ａ内に導
電柱１４を形成することで微細なピッチで上下の接続を
取ることが可能となる。 〔電解めっき水溶液〕 硫酸 １８０ ｇ／ｌ 硫酸銅 ８０ ｇ／ｌ 添加剤（アトテックジャパン製、商品名：カパラシドＧＬ） １ ｍｌ／ｌ 〔電解めっき条件〕 電流密度 １Ａ／ｄｍ2 温度 室温Subsequently, a method of manufacturing the core substrate shown in FIG. 2F will be specifically described with reference to FIG. First, as shown in FIG. 1A, a commercially available resist film 11 having a thickness of 0.3 mm is adhered onto the copper foil 10. next,
A photomask film (not shown) on which a black circle of 0.1 mmφ capable of forming the regularly arranged conductive pillars described above with reference to FIG.
Exposure at 00 mJ / cm 2 . This is spray-developed with a DMTG solution to obtain a 0.1 mmφ excellent in dimensional accuracy equivalent to a photomask film as shown in FIG.
Thickness having an opening (conductive column forming opening) 12a
An mm resist 12 is formed. Subsequently, a current is applied to the copper foil 10 under the following conditions, and electrolytic copper plating is performed in the opening 12a to form a conductive pillar 14 having a height of 0.3 mm. Note that the opening 12a provided in the resist 12 can be formed to have a smaller diameter than a through hole formed by a drill used in forming a through hole used in the prior art, so that the conductive pillar 14 is formed in the small diameter opening 12a. This makes it possible to make up and down connections at a fine pitch. [Electroplating aqueous solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (manufactured by Atotech Japan, trade name: Capparaside GL) 1 ml / l [Electroplating conditions] Current density 1 A / dm 2 Temperature Room temperature
【００３０】次に、レジスト１２を５％のＫＯＨで剥離
する（図１（Ｄ））。その後、熱可塑性樹脂であるフッ
素材脂（ポリテトラフルオロエチレン等）１６を可塑温
度である３７０°Ｃ程度まで加熱して該導電柱１４へ塗
布・充填し、冷却させて硬化させる。ここで、該コア基
板の用いられる多層プリント配線板は、該フッ素樹脂の
可塑温度以下の３００°Ｃ未満で用いられる。本実施形
態では、導電柱１４を固定する樹脂としてフッ素樹脂を
用いるが、エポキシ樹脂、ポリイミド樹脂、ビスマレイ
ミドトリアジン樹脂等の種々の樹脂を用いることがで
き、更に、これら樹脂に樹脂粒子等の粒子を含ませるこ
とも可能である。Next, the resist 12 is stripped with 5% KOH (FIG. 1D). Thereafter, a fluororesin (polytetrafluoroethylene or the like) 16 which is a thermoplastic resin is heated to about 370 ° C. which is a plasticizing temperature, applied and filled in the conductive pillars 14, cooled, and cured. Here, the multilayer printed wiring board used as the core substrate is used at a temperature lower than the plasticization temperature of the fluororesin and lower than 300 ° C. In the present embodiment, a fluororesin is used as a resin for fixing the conductive columns 14, but various resins such as an epoxy resin, a polyimide resin, and a bismaleimide triazine resin can be used. Can also be included.
【００３１】最後に、図２（Ｆ）に示すように上部を樹
脂１６を研磨し、導電柱１４を露出させることで上層
（導体層２４）との接続を確実にする。同様に、下部の
銅箔１０を研磨し、導電柱１４を露出させることで下層
（導体層２４）との接続を確実にする。なお、本実施形
態では、下部の銅箔１０を研磨により一旦剥離している
が、該銅箔１０をエッチングすることで後述する導体層
２４を形成することも可能である。Finally, as shown in FIG. 2 (F), the upper portion is polished with the resin 16 to expose the conductive pillars 14, thereby ensuring the connection with the upper layer (conductor layer 24). Similarly, the lower copper foil 10 is polished to expose the conductive pillars 14, thereby ensuring connection with the lower layer (conductor layer 24). In the present embodiment, the lower copper foil 10 is once peeled off by polishing, but the copper foil 10 may be etched to form a conductor layer 24 described later.
【００３２】引き続き、該コア基板を用いる多層プリン
ト配線板の製造方法について説明する。なお、以下に述
べる方法は、セミアディティブ法による多層プリント配
線板の製造方法に関するものであるが、本発明における
多層プリント配線板の製造方法では、フルアディティブ
法やマルチラミネーション法、ピンラミネーション法を
採用することができる。先ず、本実施形態の多層プリン
ト配線板の製造方法に用いるＡ．無電解めっき用接着
剤、Ｂ．層間樹脂絶縁剤、Ｃ．樹脂充填剤の組成につい
て説明する。Next, a method for manufacturing a multilayer printed wiring board using the core substrate will be described. The method described below relates to a method of manufacturing a multilayer printed wiring board by a semi-additive method, but the method of manufacturing a multilayer printed wiring board in the present invention employs a full additive method, a multi-lamination method, and a pin lamination method. can do. First, a method of manufacturing a multilayer printed wiring board according to the present embodiment will be described. Adhesive for electroless plating, B. Interlayer resin insulation, C.I. The composition of the resin filler will be described.
【００３３】Ａ．無電解めっき用接着剤調製用の原料組
成物（上層用接着剤） 〔樹脂組成物〕クレゾールノボラック型エポキシ樹脂
（日本化薬製、分子量２５００）の２５％アクリル化物
を８０wt％の濃度でＤＭＤＧに溶解させた樹脂液を３５
重量部、感光性モノマー（東亜合成製、アロニックスＭ
３１５）３. １５重量部、消泡剤（サンノプコ製、Ｓ−
６５）０. ５重量部、ＮＭＰ３. ６重量部を攪拌混合し
て得る。A. Raw material composition for preparing adhesive for electroless plating (adhesive for upper layer) [Resin composition] 25% acrylate of cresol novolac type epoxy resin (Nippon Kayaku, molecular weight 2500) at 80 wt% concentration in DMDG 35 dissolved resin solution
Parts by weight, photosensitive monomer (Toa Gosei Co., Aronix M
315) 3.15 parts by weight of an antifoaming agent (manufactured by San Nopco, S-
65) 0.5 parts by weight and 3.6 parts by weight of NMP are obtained by stirring and mixing.
【００３４】〔樹脂組成物〕ポリエーテルスルフォン
（ＰＥＳ）１２重量部、エポキシ樹脂粒子（三洋化成
製、ポリマーポール）の平均粒径１. ０μｍのものを
７. ２重量部、平均粒径０. ５μｍのものを３. ０９重
量部、を混合した後、さらにＮＭＰ３０重量部を添加
し、ビーズミルで攪拌混合して得る。[Resin composition] Polyethersulfone (PES) 12 parts by weight, epoxy resin particles (manufactured by Sanyo Chemical Co., polymer pole) having an average particle diameter of 1.0 μm, 7.2 parts by weight, and an average particle diameter of 0.1 part. After mixing 3.09 parts by weight of a 5 μm one, 30 parts by weight of NMP is further added, and the mixture is stirred and mixed by a bead mill.
【００３５】〔硬化剤組成物〕イミダゾール硬化剤
（四国化成製、２Ｅ ４ＭＺ−ＣＮ ）２重量部、光開
始剤（チバガイギー製、イルガキュア Ｉ−９０７）２
重量部、光増感剤（日本化薬製、ＤＥＴＸ−Ｓ）０. ２
重量部、ＮＭＰ１. ５重量部を攪拌混合して得る。[Curing agent composition] 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), a photoinitiator (Irgacure I-907, manufactured by Ciba Geigy) 2
Parts by weight, photosensitizer (DETX-S, manufactured by Nippon Kayaku) 0.2
Parts by weight and 1.5 parts by weight of NMP are obtained by stirring and mixing.
【００３６】Ｂ．層間樹脂絶縁剤調製用の原料組成物
（下層用接着剤） 〔樹脂組成物〕クレゾールノボラック型エポキシ樹脂
（日本化薬製、分子量２５００）の２５％アクリル化物
を８０wt％の濃度でＤＭＤＧに溶解させた樹脂液を３５
重量部、感光性モノマー（東亜合成製、アロニックスＭ
３１５）４重量部、消泡剤（サンノプコ製、Ｓ−６５）
０. ５重量部、ＮＭＰ３. ６重量部を攪拌混合して得
る。B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 25% acrylate of cresol novolac type epoxy resin (Nippon Kayaku, molecular weight 2500) is dissolved in DMDG at a concentration of 80 wt%. 35 liquid resin
Parts by weight, photosensitive monomer (Toa Gosei Co., Aronix M
315) 4 parts by weight, an antifoaming agent (manufactured by San Nopco, S-65)
0.5 parts by weight and 3.6 parts by weight of NMP are obtained by stirring and mixing.
【００３７】〔樹脂組成物〕ポリエーテルスルフォン
（ＰＥＳ）１２重量部、エポキシ樹脂粒子（三洋化成
製、ポリマーポール）の平均粒径０. ５μｍのものを１
４. ４９重量部、を混合した後、さらにＮＭＰ３０重量
部を添加し、ビーズミルで攪拌混合して得る。[Resin Composition] 12 parts by weight of polyethersulfone (PES) and 1 particle of epoxy resin particles (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle size of 0.5 μm were used.
After mixing 4.49 parts by weight, 30 parts by weight of NMP is further added, and the mixture is stirred and mixed by a bead mill.
【００３８】〔硬化剤組成物〕イミダゾール硬化剤
（四国化成製、２Ｅ ４ＭＺ−ＣＮ）２重量部、光開始
剤（チバガイギー製、イルガキュア Ｉ−９０７）２重
量部、光増感剤（日本化薬製、ＤＥＴＸ−Ｓ）０. ２重
量部、ＮＭＰ１. ５重量部を攪拌混合して得る。[Curing Agent Composition] 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of a photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), and a photosensitizer (Nippon Kayaku) And 0.2 parts by weight of DETX-S) and 1.5 parts by weight of NMP.
【００３９】Ｃ．樹脂充填剤調製用の原料組成物 〔樹脂組成物〕ビスフェノールＡ型エポキシモノマー
（油化シェル製、エピコート８２８）１００重量部、表
面に平均粒径１. ５μｍのＡｌ2 Ｏ3 球状粒子１５０重
量部、Ｎ−メチルピロリドン（ＮＭＰ）３０重量部、レ
ベリング剤（サンノプコ製、ペレノールＳ４）１. ５重
量部を攪拌混合し、その混合物の粘度を２３±１℃で４
５, ０００〜４９, ０００cps に調整する。C. Raw material composition for preparing resin filler [Resin composition] 100 parts by weight of bisphenol A type epoxy monomer (manufactured by Yuka Shell, Epicoat 828), 150 parts by weight of Al 2 O 3 spherical particles having an average particle size of 1.5 μm on the surface , 30 parts by weight of N-methylpyrrolidone (NMP) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) were stirred and mixed, and the viscosity of the mixture was adjusted to 23 ± 1 ° C.
Adjust to 5,000-49,000 cps.
【００４０】〔硬化剤組成物〕イミダゾール硬化剤
（四国化成製、２Ｅ ４ＭＺ−ＣＮ）６. ５重量部。[Curing agent composition] 6.5 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals).
【００４１】引き続き、プリント配線板の製造工程につ
いて図２乃至図９を参照して説明する。 （１）先ず、図２（Ｆ）に示すコア基板３０の両面に無
電解めっき及び電解めっきを行うことによりめっき銅膜
２２を形成する（図２（Ｇ））。次に、パターン状にエ
ッチングすることで、導電柱１４の直上にバイアホール
との接続用の導体層２４と所定パターンの導体回路２５
とを形成する（図１（Ｈ））。Next, the manufacturing process of the printed wiring board will be described with reference to FIGS. (1) First, a plated copper film 22 is formed by performing electroless plating and electrolytic plating on both surfaces of the core substrate 30 shown in FIG. 2 (F) (FIG. 2 (G)). Next, the conductor layer 24 for connection to the via hole and the conductor circuit 25 of a predetermined pattern are formed just above the conductive pillar 14 by etching in a pattern.
(FIG. 1H).
【００４２】（２）この基板３０を水洗いし、乾燥した
後、酸化浴（黒化浴）として、ＮａＯＨ（１０ｇ／
ｌ）、ＮａＣｌＯ2 （４０ｇ／ｌ）、Ｎａ3 Ｏ4 (６ｇ
／ｌ）、還元浴として、ＮａＯＨ（１０ｇ／ｌ）、Ｎａ
ＢＨ4 （６ｇ／ｌ）を用いた酸化−還元処理により、図
２（Ｉ）に示すように導体層２４及び導体回路２５の表
面に粗化層２６を設ける。 （３）上述したＣの樹脂充填剤調製用の原料組成物を混
合混練して樹脂充填剤を得る。(2) After the substrate 30 was washed with water and dried, NaOH (10 g /
l), NaClO 2 (40 g / l), Na 3 O 4 (6 g
/ L), NaOH (10 g / l), Na as a reducing bath
By oxidation-reduction treatment using BH 4 (6 g / l), a roughened layer 26 is provided on the surfaces of the conductor layer 24 and the conductor circuit 25 as shown in FIG. (3) The raw material composition for preparing the resin filler C described above is mixed and kneaded to obtain a resin filler.
【００４３】（４）コア基板３０にマスクを用いて印刷
を行い、充填剤４０を基板３０の表面へ塗布する（図２
（Ｊ）参照）。その後に充填剤４０を熱硬化させる。(4) Printing is performed on the core substrate 30 using a mask, and the filler 40 is applied to the surface of the substrate 30 (FIG. 2).
(J)). After that, the filler 40 is thermally cured.
【００４４】（５）上記（４）の処理を終えた基板３０
を、＃４００のベルト研磨紙（三共理化学製）を用いた
ベルトサンダー研磨により、導体層２４及び導体回路２
５の表面に樹脂充填剤が残らないように研磨し、次い
で、上記ベルトサンダー研磨による傷を取り除くための
バフ研磨をＳｉＣ砥粒にて行う。このような一連の研磨
を基板の他方の面についても同様に行う。次いで、１０
０℃で１時間、１５０℃で１時間の加熱処理を行って樹
脂充填剤４０を硬化させる。このようにして、導体層２
４及び導体回路２５の上面の粗化層を除去して、基板３
０の両面を図３（Ｋ）に示すように平滑化する。(5) The substrate 30 after the processing of the above (4)
Is subjected to belt sanding using # 400 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.) to form the conductor layer 24
5 is polished so that no resin filler remains on the surface, and then buffing is performed with SiC abrasive grains to remove the scratches caused by the belt sander polishing. Such a series of polishing is similarly performed on the other surface of the substrate. Then 10
Heat treatment is performed at 0 ° C. for 1 hour and at 150 ° C. for 1 hour to cure the resin filler 40. Thus, the conductor layer 2
4 and the roughened layer on the upper surface of the conductor circuit 25 are removed, and the substrate 3
0 are smoothed as shown in FIG.
【００４５】（６）上記（５）の処理で露出した導体層
２４及び導体回路２５上面に図３（Ｌ）に示すように、
厚さ２. ５μｍのＣｕ−Ｎｉ−Ｐ合金からなる粗化層
（凹凸層）４２を形成し、さらに、粗化層４２の表面に
厚さ０. ３μｍのＳｎ層（図示せず）を設ける。その形
成方法は以下のようである。基板３０を酸性脱脂してソ
フトエッチングし、次いで、塩化パラジウムと有機酸か
らなる触媒溶液で処理して、Ｐｄ触媒を付与し、この触
媒を活性化した後、硫酸銅８ｇ／ｌ、硫酸ニッケル０.
６ｇ／ｌ、クエン酸１５ｇ／ｌ、次亜リン酸ナトリウム
２９ｇ／ｌ、ホウ酸３１ｇ／ｌ、界面活性剤０. １ｇ／
ｌ、ｐＨ＝９からなる無電解めっき浴にてめっきを施
し、導体回路２４上面にＣｕ−Ｎｉ−Ｐ合金の粗化層４
２を形成する。ついで、ホウフッ化スズ０. １mol ／
ｌ、チオ尿素１. ０mol ／ｌ、温度５０℃、ｐＨ＝１.
２の条件でＣｕ−Ｓｎ置換反応させ、粗化層４２の表面
に厚さ０.３μｍのＳｎ層を設ける。(6) As shown in FIG. 3 (L), on the upper surfaces of the conductor layers 24 and the conductor circuits 25 exposed in the process (5),
A roughened layer (concavo-convex layer) 42 made of a 2.5 μm thick Cu—Ni—P alloy is formed, and a 0.3 μm thick Sn layer (not shown) is provided on the surface of the roughened layer 42. . The formation method is as follows. The substrate 30 was acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l and nickel sulfate 0 .
6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l
1, plating is performed in an electroless plating bath having a pH of 9 and a roughened layer 4 of Cu—Ni—P alloy is formed on the upper surface of the conductor circuit 24.
Form 2 Then, tin borofluoride 0.1 mol /
1, thiourea 1.0 mol / l, temperature 50 ° C., pH = 1.
A Cu—Sn substitution reaction is performed under the conditions of 2 to provide a 0.3 μm thick Sn layer on the surface of the roughened layer 42.
【００４６】（７）上述した組成物Ｂの層間樹脂絶縁剤
調製用の原料組成物を攪拌混合し、粘度１. ５ Pa ・ｓ
に調整して層間樹脂絶縁剤（下層用）を得る。次いで、
上述した組成物Ａの無電解めっき用接着剤調製用の原料
組成物を攪拌混合し、粘度７Pa・ｓに調整して無電解め
っき用接着剤溶液（上層用）を得る。(7) The above-mentioned raw material composition for the preparation of the interlayer resin insulating material of the composition B was mixed with stirring, and the viscosity was 1.5 Pa · s.
To obtain an interlayer resin insulating agent (for lower layer). Then
The raw material composition for preparing the adhesive for electroless plating of the composition A described above is stirred and mixed to adjust the viscosity to 7 Pa · s to obtain an adhesive solution for electroless plating (for the upper layer).
【００４７】（８）上記（６）の基板３０（図３
（Ｌ））の両面に、図３（Ｍ）に示すように上記（７）
で得られた粘度１. ５Pa・ｓの層間樹脂絶縁剤（下層
用）４４を調製後２４時間以内にロールコータで塗布
し、水平状態で２０分間放置してから、６０℃で３０分
の乾燥（プリベーク）を行う。次いで、上記（７）で得
られた粘度７Pa・ｓの感光性の接着剤溶液（上層用）４
６を調製後２４時間以内に塗布し、水平状態で２０分間
放置してから、６０℃で３０分の乾燥（プリベーク）を
行い、厚さ３５μｍの接着剤層５０を形成する。(8) The substrate 30 of the above (6) (FIG. 3)
(L)), as shown in FIG.
The interlayer resin insulating agent (for lower layer) 44 having a viscosity of 1.5 Pa · s obtained in the above was applied by a roll coater within 24 hours after preparation, and left in a horizontal state for 20 minutes, and then dried at 60 ° C. for 30 minutes. (Pre-bake). Next, the photosensitive adhesive solution (for the upper layer) having a viscosity of 7 Pa · s obtained in the above (7) 4
6 is applied within 24 hours after preparation, left in a horizontal state for 20 minutes, and then dried (prebaked) at 60 ° C. for 30 minutes to form an adhesive layer 50 having a thickness of 35 μm.
【００４８】（９）上記（８）で接着剤層５０を形成し
た基板３０の両面に、８５μｍφの黒円が印刷されたフ
ォトマスクフィルム（図示せず）を密着させ、超高圧水
銀灯により５００mJ／cm2 で露光する。これをＤＭＴＧ
溶液でスプレー現像し、さらに、当該基板を超高圧水銀
灯により３０００mJ／cm2 で露光し、１００℃で１時
間、１２０℃で１時間、その後１５０℃で３時間の加熱
処理（ポストベーク）をすることにより、図４（Ｎ）に
示すようにフォトマスクフィルムに相当する寸法精度に
優れた８５μｍφの開口（バイアホール形成用開口）４
８を有する厚さ３５μｍの層間樹脂絶縁層（２層構造）
５０を形成する。なお、バイアホールとなる開口４８に
は、スズめっき層を部分的に露出させる。(9) A photomask film (not shown) on which a black circle of 85 μmφ is printed is brought into close contact with both surfaces of the substrate 30 on which the adhesive layer 50 has been formed in the above (8), and 500 mJ / to exposure in cm 2. This is DMTG
The substrate is exposed to 3000 mJ / cm 2 by an ultra-high pressure mercury lamp, and subjected to a heat treatment (post-bake) at 100 ° C. for 1 hour, 120 ° C. for 1 hour, and then at 150 ° C. for 3 hours. As a result, as shown in FIG. 4 (N), an 85 μmφ opening (via hole forming opening) 4 having excellent dimensional accuracy corresponding to a photomask film.
35 having a thickness of 35 μm and having a thickness of 8 (two-layer structure)
Form 50. Note that the tin plating layer is partially exposed in the opening 48 serving as a via hole.
【００４９】（１０）開口４８が形成された基板３０
を、クロム酸に１９分間浸漬し、層間樹脂絶縁層５０の
表面に存在するエポキシ樹脂粒子を溶解除去することに
より、図４（Ｏ）に示すように当該層間樹脂絶縁層５０
の表面を粗化面５１とし、その後、中和溶液（シプレイ
社製）に浸漬してから水洗いする。さらに、粗面化処理
（粗化深さ３μｍ）した該基板３０の表面に、パラジウ
ム触媒（アトテック製）を付与することにより、層間樹
脂絶縁層５０の表面およびバイアホール用開口４８の内
壁面に触媒核を付ける。(10) The substrate 30 having the opening 48 formed thereon
Is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulation layer 50, thereby forming the interlayer resin insulation layer 50 as shown in FIG.
Is made a roughened surface 51, and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate 30 which has been subjected to the surface roughening treatment (roughening depth: 3 μm), the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48 are formed. Attach catalyst core.
【００５０】（１１）以下に示す組成の無電解銅めっき
水溶液中に基板を浸漬して、図４（Ｐ）に示すように粗
面全体に厚さ０. ６μｍの無電解銅めっき膜５２を形成
する。 〔無電解めっき水溶液〕 ＥＤＴＡ １５０ ｇ／ｌ 硫酸銅 ２０ ｇ／ｌ ＨＣＨＯ ３０ ml ／ｌ ＮａＯＨ ４０ ｇ／ｌ α、α’−ビピリジル ８０ mg ／ｌ ＰＥＧ ０. １ ｇ／ｌ 〔無電解めっき条件〕７０℃の液温度で３０分(11) The substrate is immersed in an aqueous electroless copper plating solution having the following composition to form an electroless copper plating film 52 having a thickness of 0.6 μm on the entire rough surface as shown in FIG. Form. [Electroless plating aqueous solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 30 minutes at 70 ° C liquid temperature
【００５１】（１２）市販のレジストフィルムを貼り付
けた後、マスクを載置して、１００ mJ ／cm2 で露光、
０. ８％炭酸ナトリウムで現像処理し、図５（Ｑ）に示
すように厚さ１５μｍのめっきレジスト５４を設ける。(12) After attaching a commercially available resist film, a mask is placed and exposed at 100 mJ / cm 2 .
After developing with 0.8% sodium carbonate, a plating resist 54 having a thickness of 15 μm is provided as shown in FIG.
【００５２】（１３）次いで、上述した導電柱の形成時
と同様の条件に従い電解銅めっきを施し、厚さ１５μｍ
の電解めっき銅膜５６を形成する（図５（Ｒ））。(13) Next, electrolytic copper plating is performed according to the same conditions as those for forming the above-mentioned conductive pillars, and the thickness is 15 μm.
Is formed (FIG. 5 (R)).
【００５３】（１４）めっきレジスト５６を５％のＫＯ
Ｈで剥離除去した後、そのめっきレジスト５６下の無電
解めっき膜５２を硫酸と過酸化水素の混合液でエッチン
グ処理して溶解除去し、図５（Ｓ）で示すように無電解
銅めっき膜５２と電解銅めっき膜５６からなる厚さ１５
μｍの導体回路５８及びバイアホール６０を形成する。
さらに、７０℃で８００ｇ／ｌのクロム酸に３分間浸漬
して、導体回路５８、バイアホール６０間の無電解めっ
き用接着剤層表面を１μｍエッチング処理し、表面のパ
ラジウム触媒を除去する。(14) The plating resist 56 is made of 5% KO
After stripping and removing with H, the electroless plating film 52 under the plating resist 56 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and as shown in FIG. 52 and a thickness 15 composed of the electrolytic copper plating film 56
A conductor circuit 58 and a via hole 60 of μm are formed.
Further, the surface of the adhesive layer for electroless plating between the conductor circuit 58 and the via hole 60 is etched by 1 μm at 70 ° C. for 3 minutes in 800 g / l chromic acid to remove the palladium catalyst on the surface.
【００５４】（１５）導体回路５８を形成した基板３０
を、硫酸銅８ｇ／ｌ、硫酸ニッケル０．６ｇ／ｌ、クエ
ン酸１５ｇ／ｌ、次亜リン酸ナトリウム２９ｇ／ｌ、ホ
ウ酸３１ｇ／ｌ、界面活性剤０．１ｇ／ｌからなるｐＨ
＝９の無電解めっき液に浸漬し、図６（Ｔ）に示すよう
に該導体回路５８及びバイアホール６０の表面に厚さ３
μｍの銅−ニッケル−リンからなる粗化層６２を形成す
る。ついで、ホウフッ化スズ０．１ｍｏｌ／ｌ、チオ尿
素１．０ｍｏｌ／ｌ、温度５０℃、ｐＨ＝１．２の条件
でＣｕ−Ｓｎ置換反応させ、粗化層６２の表面に０．３
μｍの厚さのＳｎ層を設ける（Ｓｎ層については図示し
ない）。(15) Substrate 30 on which conductor circuit 58 is formed
Was prepared by adding 8 g / l of copper sulfate, 0.6 g / l of nickel sulfate, 15 g / l of citric acid, 29 g / l of sodium hypophosphite, 31 g / l of boric acid, and 0.1 g / l of a surfactant.
= 9, and a thickness of 3 mm was applied to the surfaces of the conductor circuit 58 and the via hole 60 as shown in FIG.
A roughened layer 62 of μm copper-nickel-phosphorus is formed. Then, Cu-Sn substitution reaction was carried out under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C., pH = 1.2, and 0.3 μm was applied to the surface of the roughened layer 62.
A Sn layer having a thickness of μm is provided (the Sn layer is not shown).
【００５５】（１６）（２）〜（１５）の工程を繰り返
すことにより、さらに上層の層間樹脂絶縁層１５０とバ
イアホール１６０及び導体回路１５８を形成する（図６
（Ｕ））。(16) By repeating the steps (2) to (15), an upper interlayer resin insulation layer 150, a via hole 160, and a conductor circuit 158 are further formed (FIG. 6).
(U)).
【００５６】（１７）そして、図７に示すようにパッド
部分に対応する開口部７１を設けた（開口径２００μ
ｍ）ソルダーレジスト層（厚み２０μｍ）７０を形成し
た後、ソルダーレジスト層を補強用の樹脂組成物をソル
ダーレジストの開口群の周囲に塗布し、厚さ４０μｍの
補強層７８を形成する。(17) Then, as shown in FIG. 7, an opening 71 corresponding to the pad portion was provided (opening diameter 200 μm).
m) After the formation of the solder resist layer (thickness: 20 μm) 70, a resin composition for reinforcing the solder resist layer is applied around the opening group of the solder resist to form a reinforcement layer 78 having a thickness of 40 μm.
【００５７】（１８）次に、基板３０を、無電解ニッケ
ルめっき液に２０分間浸漬して、開口部７１に厚さ５μ
ｍのニッケルめっき層７２を形成し、さらに、その基板
３０を、無電解金めっき液に浸漬して、ニッケルめっき
層上に厚さ０．０３μｍの金めっき層７４を形成する。(18) Next, the substrate 30 is immersed in an electroless nickel plating solution for 20 minutes so that the opening 71 has a thickness of 5 μm.
Then, a nickel plating layer 72 having a thickness of 0.03 μm is formed on the nickel plating layer by immersing the substrate 30 in an electroless gold plating solution.
【００５８】（１９）そして、ソルダーレジスト層７０
の開口部７１に、はんだペーストを印刷して、２００℃
でリフローすることによりはんだバンプ７６Ｕ、７６Ｄ
を形成し、はんだパンプを有するプリント配線板を製造
する。(19) The solder resist layer 70
The solder paste is printed on the opening 71 of
Solder bumps 76U, 76D
Is formed, and a printed wiring board having a solder pump is manufactured.
【００５９】本実施形態の多層プリント配線板の製造方
法では、コア基板の導電柱１４の直上にバイアホール６
０を形成することで、コア基板３０表面のバイアホール
６０との接続用パッドをなくし、微細なピッチで導電柱
１４を配設して上下の接続を取っている。また、導電柱
１４を規則的に配列してあるため、コア基板３０に反り
等を発生させず、生産性が高い。In the method of manufacturing a multilayer printed wiring board according to the present embodiment, the via hole 6 is provided immediately above the conductive pillar 14 of the core substrate.
By forming 0, pads for connection with the via holes 60 on the surface of the core substrate 30 are eliminated, and the conductive pillars 14 are arranged at a fine pitch to establish vertical connection. Further, since the conductive pillars 14 are regularly arranged, the core substrate 30 does not warp or the like, and the productivity is high.
【００６０】[0060]
【発明の効果】請求項１及び請求項２のコア基板は、導
電柱を用いることで微細なピッチで上下の接続を取るこ
とができる。また、導電柱を規則的に配列してあるた
め、コア基板に反り等を発生させず、生産性が高い。According to the first and second aspects of the present invention, the upper and lower connections can be made at a fine pitch by using conductive pillars. In addition, since the conductive columns are regularly arranged, the core substrate does not warp or the like, and the productivity is high.
【００６１】請求項３のコア基板では、導体柱を固定す
る樹脂が、熱可塑性であるため、誘電率等の電気特性が
良好であり、高周波用の多層プリント配線板に用いるこ
とが可能となる。According to the third aspect of the present invention, since the resin for fixing the conductor pillars is thermoplastic, the electrical properties such as the dielectric constant are good, and the core substrate can be used for a high-frequency multilayer printed wiring board. .
【００６２】請求項４のコア基板では、導電柱をコア基
板の水平方向に対して対称になるように規則的に配列し
てあるため、コア基板に反り等を発生させることがな
い。In the core substrate according to the fourth aspect, since the conductive columns are regularly arranged so as to be symmetrical with respect to the horizontal direction of the core substrate, the core substrate does not warp or the like.
【００６３】請求項５のコア基板の製造方法では、レジ
ストに設けた小径の開口内に形成した導電柱を用いるこ
とで、微細なピッチで上下の接続を取ることができる。
また、導電柱を規則的に配列してあるため、コア基板に
反り等を発生させず、生産性が高い。In the method of manufacturing a core substrate according to the fifth aspect, by using the conductive pillar formed in the small-diameter opening provided in the resist, the vertical connection can be established at a fine pitch.
In addition, since the conductive columns are regularly arranged, the core substrate does not warp or the like, and the productivity is high.
【００６４】請求項６の多層プリント配線板では、コア
基板が導体柱を樹脂で固定してなるため、微細なピッチ
で上下の接続を取ることができる。更に、コア基板の導
電柱の直上にバイアホールを形成するため、微細なピッ
チで上下の接続を取ることが可能である。また、導電柱
を規則的に配列してあるため、反り等を発生させしな
い。特に、規則的に配列した導体柱を樹脂で固定した汎
用のコア基板を用いるため、廉価に構成することができ
る。In the multilayer printed wiring board according to the sixth aspect, since the core substrate is formed by fixing the conductive pillars with resin, the vertical connection can be established at a fine pitch. Further, since the via holes are formed immediately above the conductive pillars of the core substrate, it is possible to make a vertical connection with a fine pitch. Also, since the conductive columns are regularly arranged, no warpage or the like is generated. In particular, since a general-purpose core substrate in which regularly arranged conductor pillars are fixed with resin is used, the configuration can be made at a low cost.
【００６５】請求項７の多層プリント配線板では、コア
基板の導体柱の内の幾つかを使用しないことで、汎用の
コア基板を用いることが可能になり、廉価に構成するこ
とができる。In the multilayer printed wiring board according to the seventh aspect, since some of the conductor pillars of the core substrate are not used, a general-purpose core substrate can be used, and the configuration can be reduced.
【図１】図１（Ａ）、図１（Ｂ）、図１（Ｃ）、図１
（Ｄ）、図１（Ｅ）は、本発明の１実施形態に係るコア
基板の製造方法の工程図である。1 (A), 1 (B), 1 (C), 1
(D) and FIG. 1 (E) are process diagrams of a method for manufacturing a core substrate according to one embodiment of the present invention.
【図２】図２（Ｆ）、図２（Ｇ）、図２（Ｈ）、図２
（Ｉ）、図２（Ｊ）は、本発明の１実施形態に係る多層
プリント配線板の製造方法の工程図である。2 (F), 2 (G), 2 (H), 2
(I) and FIG. 2 (J) are process diagrams of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
【図３】図３（Ｋ）、図（Ｌ）、図３（Ｍ）は、本発明
の１実施形態に係る多層プリント配線板の製造方法の工
程図である。3 (K), 3 (L) and 3 (M) are process diagrams of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
【図４】図４（Ｎ）、図４（Ｏ）、図４（Ｐ）は、本発
明の１実施形態に係る多層プリント配線板の製造方法の
工程図である。FIGS. 4 (N), 4 (O), and 4 (P) are process diagrams of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
【図５】図５（Ｑ）、図５（Ｒ）、図５（Ｓ）は、本発
明の１実施形態に係る多層プリント配線板の製造方法の
工程図である。FIGS. 5 (Q), 5 (R), and 5 (S) are process diagrams of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
【図６】図６（Ｔ）、図６（Ｕ）は、本発明の１実施形
態に係る多層プリント配線板の製造方法の工程図であ
る。FIGS. 6 (T) and 6 (U) are process diagrams of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
【図７】本発明の１実施形態に係る多層プリント配線板
の製造方法の断面図である。FIG. 7 is a cross-sectional view of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
【図８】本発明の１実施形態に係るコア基板の平面図で
ある。FIG. 8 is a plan view of a core substrate according to one embodiment of the present invention.
【図９】図９（Ａ）は、従来技術に係る多層プリント配
線板の断面図であり、図９（Ｂ）は、図９（Ａ）のＢ−
Ｂ横断面図である。FIG. 9A is a cross-sectional view of a multilayer printed wiring board according to the related art, and FIG. 9B is a cross-sectional view of FIG.
It is a B cross section.
１０ 銅箔（導電体） １２ レジスト １２ａ 開口 １４ 導電柱 １６ 樹脂 ２４ 導体回路 ３０ コア基板 ５０ 層間樹脂絶縁層 ５６ 無電解めっき銅膜 ５８ 導体回路 ６０ バイアホール DESCRIPTION OF SYMBOLS 10 Copper foil (conductor) 12 Resist 12a Opening 14 Conductive pillar 16 Resin 24 Conductor circuit 30 Core substrate 50 Interlayer resin insulation layer 56 Electroless plating copper film 58 Conductor circuit 60 Via hole
Claims (7)
てなることを特徴とする多層プリント配線板用のコア基
板。1. A core substrate for a multilayer printed wiring board, wherein a regularly arranged conductive pillar is fixed with a resin.
０．０５mm以上であることを特徴とする請求項１のコア
基板。2. The core substrate according to claim 1, wherein the diameter of the conductive pillar is not more than 0.25 mm and not less than 0.05 mm.
特徴とする請求項１又は２のコア基板。3. The core substrate according to claim 1, wherein the resin is a thermoplastic resin.
て対称になるように規則的に配列したことを特徴とする
請求項１〜３のいずれか１に記載のコア基板。4. The core substrate according to claim 1, wherein the conductive columns are regularly arranged so as to be symmetric with respect to a horizontal direction of the core substrate.
を特徴とする多層プリント配線板用のコア基板の製造方
法。 （ａ）導電体の上に規則的に配列した開口を有するレジ
ストを形成する工程、（ｂ）前記開口にめっきを施し導
電柱を形成する工程、（ｃ）前記レジストを除去する工
程、（ｄ）前記導電柱間に樹脂を充填する工程。5. A method for manufacturing a core substrate for a multilayer printed wiring board, comprising the following steps (a) to (d). (A) a step of forming a resist having openings regularly arranged on a conductor, (b) a step of plating the openings to form conductive columns, (c) a step of removing the resist, (d) A) filling a resin between the conductive columns;
ール及び導体回路とを交互に積層してなる多層プリント
配線板であって、前記コア基板が規則的に配列した導体
柱を樹脂で固定してなり、前記コア基板の前記導電柱の
直上に前記バイアホールが形成されていることを特徴と
する多層プリント配線板。6. A multilayer printed wiring board in which an interlayer resin insulating layer, via holes, and conductive circuits are alternately laminated on a core substrate, wherein the conductive posts on which the core substrate is regularly arranged are fixed with resin. The multilayer printed wiring board, wherein the via hole is formed immediately above the conductive pillar of the core substrate.
用されていないことを特徴とする請求項６の多層プリン
ト配線板。7. The multilayer printed wiring board according to claim 6, wherein some of the conductor posts of the core substrate are not used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10124207A JPH11307938A (en) | 1998-04-18 | 1998-04-18 | Core board, its manufacturing method, and multi-layer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10124207A JPH11307938A (en) | 1998-04-18 | 1998-04-18 | Core board, its manufacturing method, and multi-layer printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11307938A true JPH11307938A (en) | 1999-11-05 |
Family
ID=14879651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10124207A Pending JPH11307938A (en) | 1998-04-18 | 1998-04-18 | Core board, its manufacturing method, and multi-layer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11307938A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006196785A (en) * | 2005-01-14 | 2006-07-27 | Dainippon Printing Co Ltd | Printed wiring board with built-in electronic components and manufacturing method thereof |
| US7371682B2 (en) | 2003-06-13 | 2008-05-13 | Tdk Corporation | Production method for electronic component and electronic component |
| EP2700090A1 (en) * | 2011-04-21 | 2014-02-26 | Tessera, Inc. | Interposer having molded low cte dielectric |
| JP2023028871A (en) * | 2021-08-20 | 2023-03-03 | 新光電気工業株式会社 | Wiring board and method of manufacturing the same |
| WO2026061105A1 (en) * | 2024-09-23 | 2026-03-26 | 华为技术有限公司 | Package substrate and preparation method therefor, semiconductor stack structure, and electronic device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6144881U (en) * | 1984-08-27 | 1986-03-25 | 日本電気株式会社 | printed wiring board |
| JPS61179597A (en) * | 1985-02-04 | 1986-08-12 | 沖電気工業株式会社 | Formation of multilayer interconnection |
| JPH0513960A (en) * | 1990-08-28 | 1993-01-22 | Ngk Spark Plug Co Ltd | Method for manufacturing multilayer wiring board |
| JPH08139450A (en) * | 1994-11-07 | 1996-05-31 | Toshiba Corp | Method for manufacturing printed wiring board |
| JPH09241419A (en) * | 1996-03-06 | 1997-09-16 | Hitachi Ltd | Solvent-free composition, multilayer wiring board, and methods for producing the same |
| JPH09266375A (en) * | 1996-03-27 | 1997-10-07 | Ibiden Co Ltd | Multilayer printed interconnection board manufacturing method |
| JPH1050882A (en) * | 1996-08-02 | 1998-02-20 | Toppan Printing Co Ltd | Chip carrier and its manufacturing apparatus and manufacturing method |
| JPH1075063A (en) * | 1996-09-02 | 1998-03-17 | Oki Purintetsudo Circuit Kk | Manufacture of post-connection type printed wiring board |
-
1998
- 1998-04-18 JP JP10124207A patent/JPH11307938A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6144881U (en) * | 1984-08-27 | 1986-03-25 | 日本電気株式会社 | printed wiring board |
| JPS61179597A (en) * | 1985-02-04 | 1986-08-12 | 沖電気工業株式会社 | Formation of multilayer interconnection |
| JPH0513960A (en) * | 1990-08-28 | 1993-01-22 | Ngk Spark Plug Co Ltd | Method for manufacturing multilayer wiring board |
| JPH08139450A (en) * | 1994-11-07 | 1996-05-31 | Toshiba Corp | Method for manufacturing printed wiring board |
| JPH09241419A (en) * | 1996-03-06 | 1997-09-16 | Hitachi Ltd | Solvent-free composition, multilayer wiring board, and methods for producing the same |
| JPH09266375A (en) * | 1996-03-27 | 1997-10-07 | Ibiden Co Ltd | Multilayer printed interconnection board manufacturing method |
| JPH1050882A (en) * | 1996-08-02 | 1998-02-20 | Toppan Printing Co Ltd | Chip carrier and its manufacturing apparatus and manufacturing method |
| JPH1075063A (en) * | 1996-09-02 | 1998-03-17 | Oki Purintetsudo Circuit Kk | Manufacture of post-connection type printed wiring board |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7371682B2 (en) | 2003-06-13 | 2008-05-13 | Tdk Corporation | Production method for electronic component and electronic component |
| JP2006196785A (en) * | 2005-01-14 | 2006-07-27 | Dainippon Printing Co Ltd | Printed wiring board with built-in electronic components and manufacturing method thereof |
| EP2700090A1 (en) * | 2011-04-21 | 2014-02-26 | Tessera, Inc. | Interposer having molded low cte dielectric |
| JP2014512695A (en) * | 2011-04-21 | 2014-05-22 | テセラ インコーポレイテッド | Interposer with molded low CTE dielectric |
| JP2023028871A (en) * | 2021-08-20 | 2023-03-03 | 新光電気工業株式会社 | Wiring board and method of manufacturing the same |
| WO2026061105A1 (en) * | 2024-09-23 | 2026-03-26 | 华为技术有限公司 | Package substrate and preparation method therefor, semiconductor stack structure, and electronic device |
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