JPH11355132A - Phase synchronization circuit and camera device - Google Patents

Abstract

(57) [Problem] To output a synchronization signal synchronized with an external reference signal even when the phase is continuously varied. SOLUTION: At different count values Dv counted by a counter block 5-1, setting timing signals A,
Setting timing signal creation block 5-4 for generating B
And a set timing control block 5-5 for changing the set timing control counter value to an externally input pulse generation counter value at any one of the set timing signals A and B. When the timing signal A matches, the setting timing signal B is selected so that the pulse generation counter value does not match the timing value at which the setting timing control counter value is changed to the pulse generation counter value, and phase synchronization is performed. The phase can be continuously varied and adjusted while maintaining the locked state of the loop.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a phase synchronization circuit capable of continuously adjusting the phase of an output signal synchronized with a reference signal, and to a camera device provided with such a phase synchronization circuit. .

[0002]

2. Description of the Related Art For example, in a surveillance system that displays images shot by a plurality of camera devices on a monitor device and monitors the situation, a line lock system is used to synchronize the images shot by the plurality of camera devices. It's being used. The line lock system uses, for example, a voltage cycle (60 Hz) of a commercial AC power supply as an external reference signal, and synchronizes a vertical synchronization signal of, for example, an NTSC video signal captured by a camera device with the external reference signal. is there.

However, when a plurality of camera devices synchronized by the line lock system as described above are applied to a monitoring system, the distance between the monitor device and the place where each camera device is installed is different.
For example, when an image captured by each camera device is displayed while being switched to the same monitor device, there is a problem that a screen is disturbed due to a phase shift.

Therefore, for example, a video signal photographed by a camera device is synchronized with an external reference voltage such as a commercial AC power supply, and the phase of the video signal synchronized with the external reference signal can be arbitrarily adjusted. A synchronous circuit has been previously proposed by the present applicant (Japanese Patent Application No. 7-323572).
issue).

FIG. 8 shows a block diagram of a phase locked loop circuit previously proposed by the present applicant. The phase synchronization circuit shown in FIG. 8 is an example of a circuit for synchronizing an NTSC video signal using a 60 Hz commercial AC power supply as an external synchronization signal, and outputs various synchronization signals synchronized with the external synchronization signal. It is a circuit that can be. Then, the phases of the various synchronization signals to be output can be adjusted.
In the phase locked loop circuit shown in FIG.
1 is shaped into a square wave. The created square wave is input to one of the phase comparators 102 as an external reference signal.

A voltage controlled oscillator (VCO: Voltage
The clock output from the controlled oscillator 104 is input to the synchronization signal generator 105 and counted by the built-in counter block 105-1. The count value Dv of the counter block 105-1 is supplied to the synchronization signal creation block 105-2, and the phase adjustment V
The signal is supplied to the D signal creation block 105-3. The counter block 105-1 includes an H counter for counting the output of the VCO 104, and a V counter for counting the vertical scanning period based on the count value of the H counter. The count value Dv of the V counter is equal to the first count value. The synchronization signal is generated by detecting that the second count value has been counted and further inverted when detecting that the second count value has been further advanced. This synchronization signal is output as various synchronization signals such as a video synchronization VD signal.

Further, an arbitrary set value as digital data is set in the phase adjustment VD signal creation block 105-3, and when the count value Dv of the counter block 105-1 matches the set value, For example, a phase adjustment VD signal having a width of one clock is output. This phase adjustment V
The D signal is used as the other input of the phase comparator 102. The phase difference signal between the phase adjustment VD signal output from the phase comparator 102 and the external reference signal is filtered by a low-pass filter (LPF) 103 and supplied to the VCO 104 to control the oscillation frequency and phase of the VCO 104. ing.

[0008] In the phase locked loop circuit configured as described above,
A phase locked loop (PL) including a phase comparator 102, an LPF 103, a VCO 104, and a synchronization signal generator 105
By the synchronization control of L), the phase of the square wave output as the external reference signal from the square wave creation block 101 matches the phase of the phase adjustment VD signal output from the phase adjustment VD signal creation block 105-3. Is controlled as follows.

[0009] The count value Dv of the counter block 105-1 is output from the various synchronization signals output between the first count value and the second count value, and the phase adjustment VD output at an arbitrary set value. Since the phase difference θ with the signal corresponds to the difference between an arbitrary set value and the first count value Dv, the phase difference θ can be adjusted according to the change of the arbitrary set value. Has been.

[0010]

However, in the above-described phase-locked loop circuit, for example, an arbitrary set value is continuously varied so that a phase adjustment VD signal and various synchronization signals such as a video synchronization VD signal are output. By continuously adjusting the phase difference of
In some cases, the phase locked loop (PLL) may be out of the locked state, failing to perform smooth synchronization control, and causing a problem that the synchronization of the video signal of the camera device with the external reference signal is disturbed.

The operation of each unit when an arbitrary set value is continuously varied will be described below with reference to an operation timing chart shown in FIG. In this example, an arbitrary set value (count value from a pulse generation counter (not shown))
Changes near the center of the period in which the count value of the V counter is “6”.

In this case, first, as shown in FIG.
When the pulse generation counter value is “4”, the phase adjustment VD signal generation block 105-3 outputs a phase adjustment VD signal having a pulse width, for example, at the timing when the count value of the V counter becomes “4”. . Then, when the count value of the V counter becomes “6” to perform the phase adjustment,
When the pulse generation counter value changes from “4” to “5”,
When the count of the V counter advances and the count value of the V counter becomes “5” again as shown in FIG. 7B, the phase adjustment VD signal is output. In other words, the above-described phase synchronization circuit smoothly outputs the phase adjustment VD signal for phase shift adjustment.

However, as shown in FIG.
At the timing when the count value of the V counter becomes “6”,
When the pulse generation counter value changes from "5" to "6",
Since the pulse generation counter value matches the count value of the V counter, the phase adjustment VD signal is output also during this period. That is, if the timing at which the pulse generation counter value changes matches the pulse generation counter value, the two phase adjustment Vs are set at this set value change timing.
The D signal is output.

When the two phase adjusting VD signals are output as described above, if the phase comparator 102 is of the falling edge trigger type, for example, the phase adjusting VD signal is output from the phase comparator 102. The phase difference signal to be output greatly changes, and the phase locked loop, which has been kept in the locked state, becomes unlocked, and the synchronization of the video signal of the camera device with the external reference signal is disturbed.

That is, in the above-described phase locked loop circuit, if, for example, the phase is continuously varied while the phase locked loop is kept in a locked state, a problem occurs that the phase locked loop is unlocked depending on the timing. Will be.

Accordingly, the present invention has been made in view of such a problem, and a phase synchronization circuit capable of outputting a synchronization signal synchronized with an external reference signal even when the phase is continuously varied. It is intended to provide.

[0017]

In order to achieve the above object, a phase locked loop circuit according to the present invention comprises a phase comparator for comparing the phases of a reference signal and an adjustment signal, and a phase output from the phase comparator. A voltage controlled oscillator controlled by a phase difference signal,
A counter for counting the oscillation signal output from the voltage-controlled oscillator, an arbitrary setting value input from the outside,
Setting timing control means for controlling the timing of changing the set timing control counter value to the set value so that they do not coincide with each other; and adjusting signal generation for outputting an adjusting signal when the counter value of the counter reaches the set timing control counter value. Means for outputting a synchronization signal when the counter reaches a predetermined count value.

Further, the camera device of the present invention comprises a phase comparator for comparing the phase of the reference signal with the adjustment signal, a voltage controlled oscillator controlled by a phase difference signal output from the phase comparator, A counter for counting an oscillation signal output from a voltage-controlled oscillator, a setting timing control for controlling an arbitrary setting value input from the outside, and a timing value for changing a setting timing control counter value to the setting value so as not to match Means, an adjusting signal generating means for outputting an adjusting signal when the count value of the counter reaches the set timing control counter value, and a synchronizing signal for outputting a synchronizing signal when the counter reaches a predetermined count value. It is provided with a phase synchronization circuit including a signal generation unit.

According to the present invention, the set timing control means performs control so that an arbitrary set value input from the outside does not coincide with a timing value for changing the set timing control counter value to the set value. Therefore, the timing at which the setting timing control counter value is changed to an arbitrary setting value does not coincide with the timing at which the adjustment signal is output from the adjustment signal generating means.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, as an embodiment of the present invention, a brief description will be given of an outline of a surveillance system constructed by a camera device or the like having a phase locked loop circuit of the present invention. The monitoring system shown in FIG. 1 includes, for example, a plurality of video cameras 51-1, 51-2,... In this case, each video camera 51-
The video taken at 1, 51-2,.
, For example, in order to display multi-images, it is necessary to synchronize the video signals from the respective camera devices. Therefore, each video camera 51-1, 51-2,... For example, a line lock system using a voltage cycle (60 Hz) of a commercial AC voltage is used as a signal. The phase synchronization circuit of the present invention is suitable for constructing such a line lock system of a video camera, for example.

Hereinafter, a phase locked loop circuit according to an embodiment of the present invention will be described. FIG. 2 is a circuit block diagram showing a configuration example of a phase locked loop circuit according to an embodiment of the present invention. The phase synchronization circuit shown in FIG.
An example is shown as a circuit for synchronizing an NTSC video signal using a 0 Hz commercial AC power supply, and is a circuit that can output various synchronization signals synchronized with this external synchronization signal.
Then, the phases of the various synchronization signals to be output can be adjusted. In the phase locked loop shown in FIG.
The 60 Hz commercial AC power supply, which is an external synchronization signal, is shaped into a square wave by the square wave creation block 1. The created square wave is input to one of the phase comparators 2 as an external reference signal.

The clock output from the voltage controlled oscillator (VCO) 4 is input to the synchronizing signal generator 5 and counted by the built-in counter block 5-1.
The counter block 5-1 includes an H counter for counting the output of the VCO 104, and a V counter for counting the vertical scanning period from the count value of the H counter. -2, VD signal creation block for phase adjustment 5-
3 and a setting timing signal creation block 5-4.

The synchronizing signal generation block 5-2 detects that the count value Dv of the counter block 5-1 has been set to the first count value M, and inverts the count value. A synchronization signal that is inverted again upon detecting that the synchronization has been performed is created. This synchronization signal is output from the phase synchronization circuit as various synchronization signals such as a video synchronization VD signal.

A set timing control counter value, which is digital data, is supplied from a set timing control block 5-5, which will be described later, to the phase adjustment VD signal creation block 5-3. Dv
Output a phase adjustment VD signal having a width of, for example, one clock. This phase shift adjustment VD signal is used as the other input of the phase comparator 2. The phase adjustment V output from the phase shift comparator 2
The phase difference signal between the D signal and the external reference signal is filtered by a low-pass filter (LPF) 3 and supplied to a VCO 4.
The oscillation frequency and phase of CO4 are controlled.

Setting timing signal creation block 5-4
Generates and outputs the set timing signals A and B with different counter values based on the counter value Dv of the counter block 5-1.

The setting timing control block 5-5 includes:
The set timing signals A and B generated by the set timing signal creation block 5-4 and an arbitrary set value (pulse generation counter value) X from a pulse generation circuit (not shown) are input. Then, based on the pulse generation counter value, the set timing control counter value is changed and output at one of the set timing signals A and B, as described later.

The operation of the phase locked loop configured as described above will be described with reference to the operation timing chart shown in FIG. The AC power supply waveform shown in FIG. 3A is a square wave generation block 1 including a comparator or a Schmitt trigger circuit.
To form a square wave as shown in FIG. This square wave is input to one of the phase comparators 2 as an external reference signal.

A phase adjusting VD signal shown in FIG. 2E is input to the phase comparator 2, and the phase comparator 2 responds to a phase difference between the input external reference signal and the phase adjusting VD signal. The phase difference signal (PWM signal) is output. This phase difference signal is filtered by the LPF 3 to become an error voltage, and the VCO 4
Supplied to The oscillation frequency and phase of the VCO 4 are controlled by the error voltage, and the frequency and phase of the output clock are controlled. The clock output from the VCO 4 is counted by the counter block 5-1. When the count value Dv (the V counter value shown in FIG. 3C) reaches the first count value M, the synchronization signal generation block 5- 2
Lowers the video synchronization VD signal from a high level to a low level as shown in FIG. Further, when the count advances and the count value Dv becomes the second count value N, the synchronization signal creation block 5-2 changes the video synchronization VD signal from low level to high level as shown in FIG. Launch.

Further, the phase adjustment VD signal creation block 5-3 includes a set timing control counter value and a count value Dv of the counter block 5-1 (FIG. 3C).
(E.g., V counter value shown in FIG. 3), and when they match, a phase adjustment V of one clock width as shown in FIG.
The D signal is output. This phase adjustment VD signal is input to the other side of the phase comparator 2 as described above.

In this way, the video synchronous VD signal shown in FIG. 3D is created. This video synchronous VD signal is generated by a synchronous control of a phase locked loop (PLL) including a phase comparator 2, an LPF 3, a VCO 4 and a synchronous signal generator 5 to form a square wave as an external reference signal shown in FIG. Control is performed so that the phase and the phase of the phase adjustment VD signal shown in FIG.

In the case shown in FIG. 3, since the phase adjustment VD signal is ahead of the video synchronization VD signal by the phase difference θ, the phases of various synchronization signals output from the phase synchronization circuit are obtained by shaping the AC power supply waveform. The phase of the square wave
Phase delayed by only In this case, since the phase difference θ corresponds to the difference between the set fixed count value M and the set timing control counter value, the phase difference θ is adjusted according to the change of the set timing control counter value. You.
Thereby, the phases of the various synchronization signals to be output can be arbitrarily adjusted.

When the set timing control counter value is set to a value slightly before reaching the count value M as shown in FIG. 3C, the phase of the video synchronization VD signal output from the phase synchronization circuit is changed to that of the external synchronization signal. The phase can be delayed from the phase (the phase of the square wave shown in FIG. 3B). FIG. 3 (c)
When the value X ′ slightly after reaching the count value M is set as the set timing control counter value as shown in FIG.
As shown by the broken line, the phase of the video synchronization VD signal output from the phase synchronization circuit can be advanced from the phase of the external synchronization signal (the phase of the square wave shown in FIG. 3B).

Hereinafter, a specific configuration of each block of the above-described synchronization signal generator 5 will be described. FIG.
FIG. 3 is a diagram illustrating an example of a configuration of a phase adjustment VD signal creation block 5-3. The phase adjustment VD signal generation block 5-3 shown in FIG. 4 includes n exclusive OR circuits (EX-OR) 10- provided with the same number n of bits of the count value output from the counter block 5-1. 1 to 10-n, an OR circuit 11 for taking the logical sum of the outputs of the n EX-ORs 10-1 to 10-n, and a D-type flip-flop 12 connected to the OR circuit 11. . n EX-O
One of the inputs of R10-1 to R10-n receives data of an n-bit arbitrary set value X, and the other input receives an n-bit V counter value which is a count value of the counter block 5-1. Dv is input.

Each of the EX-ORs 10-1 to 10-n is
When two input values match, the output level becomes L level. When the input values do not match, an H level is output.
OR circuit 1 for taking the logical sum of the outputs of R10-1 to R10-n
From 1, the L level is output only when the arbitrary set value X matches the V counter value Dv. Therefore, the OR circuit 1
As shown in FIG. 3 (e), when the V counter value Dv reaches the arbitrarily set value X as shown in FIG.
Level. This signal is supplied to the D-type flip-flop 12
And the hazard is removed to obtain a phase adjusting VD signal.

Next, FIG. 5 shows an example of the configuration of the synchronization signal creation block 5-2. 5 includes an N decoder 21 for detecting that the V counter value Dv has become N, an M decoder 22 for detecting that the V counter value Dv has become M, The flip-flop 23 is set by the output of the N decoder 21 and reset by the output of the M decoder 22.

The M decoder 22 decodes the V counter value Dv, outputs an H level when the V counter value Dv becomes M, resets the flip-flop 23, and sets the video synchronous VD signal to an L level. Then, the V counter value D
When v advances and the N decoder 21 decodes that the V counter value Dv has become N, the N decoder 21 outputs an H level and sets the flip-flop 23 to set the video synchronous VD signal to the H level. As a result, FIG.
Can be obtained.

FIG. 6 is a diagram showing an example of the configuration of the setting timing control block. The setting timing control block 5-5 shown in FIG. 6 includes a setting timing switching control unit 6 for outputting a high / low switching signal according to a pulse generation counter value, a switching unit 7 controlled by the switching signal, The memory cell 8 latches an occurrence counter value and outputs the latched value as a set timing control counter value.

The setting timing switching control unit 6 controls the pulse generation counter value X input to the DATA terminal of the storage cell 8 and the timing of the setting timing signal input to the LOAD terminal of the storage cell 8 so that they do not coincide with each other. The switching of the switch 7 is controlled. For this reason, the output timing value “9” of the set timing signal A is stored in advance in the set timing switching control unit 6, and this timing value is compared with the input pulse generation counter value X by a comparator. For example, when the pulse generation counter value X is less than “7” or greater than or equal to “12”, the switching signal is set to the low level and the set timing signal A is supplied to the memory cell 8. Also,
When the pulse generation counter value X is equal to or greater than “7” and less than “12”, for example, the switching signal is set to a high level to perform control such that the set timing signal B is supplied to the memory cell 8.

For example, the setting timing signal A is output at the timing when the V counter value Dv becomes "9", and the setting timing signal B is output at the timing when the V counter value Dv becomes "3". That is, the setting timing switching control unit 6 controls the switching unit 7 so that the setting timing signal B is input to the LOAD terminal of the storage cell 8 at least when the pulse generation counter value X becomes “9”. ing.

As a result, the memory cell 8 latches the pulse generation counter value X at the timing of the set timing signal A or the set timing signal B input through the switch 7, and stores the latched value in the set timing control counter. The value is output to the phase adjustment VD signal creation block 5-3.

FIG. 7 is a timing chart showing the operation of each part when the pulse generation counter value input from the outside is continuously varied in the above-described phase locked loop circuit according to the present embodiment. This will be described with reference to FIG.

In the example described below, the timing at which the pulse generation counter value X changes is the timing at which the count value of the V counter becomes "6". Further, the setting timing signal A generated by the setting timing signal creation block 5-4 is output at a timing when the V counter value Dv becomes “9”, and the setting timing signal B becomes such that the V counter value Dv becomes “3”. It shall be output at the timing.

In this case, since the set timing control counter value is "4" in FIG.
In the D signal creation block 5-3, the value of the V counter is "4".
, A VD signal for phase adjustment having a pulse width of, for example, 1 is output. When the pulse generation counter value X changes from “4” to “5” at the timing when the V counter becomes “6”, the set timing control switching unit 6 sets the storage cell 8
The switching control of the switching device 7 is performed so that the set timing signal A is input to the switching device 7.

At this time, that is, when the V counter value Dv becomes "6" and the pulse generation counter value X changes from "4" to "5", the memory cell 8 still stores the new pulse generation counter value. Since latching is not performed, the set timing control counter value output from the storage cell 8 remains at “4”. Then, when the V counter value Dv becomes "9", that is, when the set timing signal A is supplied to the memory cell 8, the pulse generation counter value "5" is latched as the set timing control counter value. .

Then, the count by the V counter advances, and when the V counter value Dv becomes "5", as shown in FIG. A position adjustment VD signal is output. Then, when the V counter value Dv becomes “6” and the pulse generation counter value X changes from “5” to “6”, the setting timing control switching unit 6 sends the setting timing signal A to the storage cell 8 as described above. Switch 7 so that
Is performed.

Also in this case, even if the V counter value Dv becomes "6" and the pulse generation counter value X changes from "5" to "6", the memory cell 8 does not yet latch the new pulse generation counter value. Therefore, the set timing control counter value output from the memory cell 8 is kept at “5”, and when the V counter value Dv becomes “9”, the pulse generation counter value “6” is set as the set timing control counter value. Latch it.

Then, as the count by the V counter advances, and when the V counter value Dv becomes "6" as shown in FIG. A position adjustment VD signal is output.

At this time, the pulse generation counter value X
Is changed from “6” to “7”, the setting timing control switching unit 6 controls the switching unit 7 so that the setting timing signal B is input to the memory cell 8, and is output from the switching unit 7. The switching signal is switched from a low level to a high level, for example. In this case, the V counter value Dv is "9".
Is satisfied, that is, at the timing when the set timing signal A is output, the pulse generation counter value “7” is not latched in the memory cell 8, and the set timing control counter value remains “6”. .

Then, the count by the V counter advances,
As shown in FIG. 4D, when the V counter value Dv becomes “3”, that is, when the set timing signal B is supplied to the memory cell 8, the pulse generation counter value “7” is set at the set timing. Latched as a control counter value. Thus, when the V counter value Dv becomes “7”, the phase adjustment VD signal having one pulse width is output from the phase adjustment VD signal creation block 5-3.

When the V counter value Dv is "6",
Although the pulse generation counter value X changes from “7” to “8”, the pulse generation counter value “8” is not latched in the memory cell 8 at the timing when the set timing signal A is output, and the pulse generation counter value X is not However, the count by the V counter advances, the V counter value Dv becomes "3" again, and when the set timing signal B is output to the memory cell 8, the pulse generation counter value "8" is used as the set timing control counter value. It will be latched in the storage cell 8.

Thereafter, the pulse generation counter value X becomes "12".
Until the setting timing signal B is output to the memory cell 8 until the pulse generation counter value X
Is latched in the storage cell 8 as the set timing control counter value. Then, when the pulse generation counter value X becomes equal to or more than “12”, the pulse generation counter value is again set as the set timing control counter value at the timing when the set timing signal A is output.
Will be latched.

As described above, in this embodiment, when the pulse generation counter value X and the set timing signal A for latching this counter value Dv in the memory cell 8 are close to each other, the set timing output with a different counter Dv value Using the signal B, the pulse generation counter value X is latched in the storage cell 8 as a set timing control counter value.
As a result, the pulse generation counter value X does not coincide with the timing at which this counter value X is taken in as the set timing control counter value, so that two phase adjustment VD signals are output, and the phase locked loop (PLL) is disabled. Locking can be prevented.

In the present embodiment, for example, the V counter value Dv from which the set timing signal A is output is set to "9", and the pulse generation counter value X is set near the set timing signal A (for example, 7 or more and less than 12). )), The case where the set timing signal B output with the count value “3” is used has been described, but at least the V counter value Dv at which the set timing signal A is output and the pulse generation counter value X match. Only by using the set timing signal B output with a different count value, it is possible to realize the present invention.

In this embodiment, the case where the pulse generation counter value X is continuously increased has been described as an example. However, the case where the pulse generation counter value X is continuously reduced or the pulse generation counter value X is generated at random. Can be realized in the same manner.

Furthermore, in the present embodiment, the phase synchronization circuit of the present invention has been described as being applied to a line lock camera used in a monitoring system or the like. The phase synchronization circuit according to the present invention, which can be used, can be applied to a line lock, a VS (Video Sync) lock, or a VBS (Video Burst Sync) lock of a camera device of an external synchronization system.

[0056]

As described above, in the phase locked loop circuit of the present invention, the set timing control means makes the set value input from the outside coincide with the timing of changing the set timing control counter value to the set value. Since the phase-locked loop is controlled so as not to be locked, the phase can be continuously varied and adjusted while maintaining the locked state of the phase-locked loop.

Further, according to the camera device provided with the phase synchronization circuit of the present invention, the phase adjustment range can be set to 0 ° to 360 °. Therefore, such a camera device is suitable for constructing a line lock system. It is considered very effective.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an outline of a suitable monitoring system using a camera device or the like to which a phase circuit according to an embodiment of the present invention is applied;

FIG. 2 is a circuit block diagram illustrating an example of a configuration of an embodiment of a phase locked loop circuit of the present embodiment.

FIG. 3 is a waveform diagram showing operation timings of the phase locked loop of the embodiment.

FIG. 4 is a circuit block diagram illustrating an example of a detailed configuration of a phase adjustment VD signal generation block in the phase locked loop circuit of the present embodiment.

FIG. 5 is a circuit block diagram illustrating an example of a detailed configuration of a synchronization signal creation block in the phase synchronization circuit of the present embodiment.

FIG. 6 is a circuit block diagram illustrating an example of a detailed configuration of a setting timing control block in the phase locked loop circuit of the present embodiment.

FIG. 7 is a waveform chart showing operation timing when the phase is continuously varied in the phase locked loop circuit of the present embodiment.

FIG. 8 is a circuit block diagram showing an example of a configuration of a phase locked loop circuit previously proposed by the present applicant.

9 is a waveform chart showing operation timings when the phase is continuously varied in the phase locked loop circuit shown in FIG.

[Explanation of symbols]

1 square wave creation block, 2 phase comparator, 3 LP
F, 4 VCO, 5 synchronization signal generator, 5-1 counter block, 5-2 synchronization signal creation block, 5-3
Phase adjustment VD signal creation block, 5-4 setting timing signal creation block, 5-5 setting timing control block, 6 setting timing switch, 7 switch, 8 storage cells, 10-1 to 10-n EX-OR, 11 OR
Circuit, 12,23 flip-flop, 21,22 decoder

Claims (4)

[Claims] 1. A phase comparator for comparing the phases of a reference signal and an adjustment signal, a voltage controlled oscillator controlled by a phase difference signal output from the phase comparator, and an oscillation output from the voltage controlled oscillator. A counter for counting a signal; an externally input arbitrary set value; and a set timing control means for controlling a timing value for changing a set timing control counter value to the set value so as not to match; and a count value of the counter. When the set timing control counter value, the adjustment signal generation means for outputting the adjustment signal, and a synchronization signal generation means for outputting a synchronization signal when the counter reaches a predetermined count value A phase-locked loop, comprising: 2. The setting timing control means includes timing signal generating means for generating first and second setting timing signals output at a predetermined timing, wherein at least the setting value and the first timing signal are provided. 2. The phase-locked loop circuit according to claim 1, wherein when the output timings match, the set timing control counter value is changed to the set value by the second timing signal. 3. A phase comparator for comparing the phases of a reference signal and an adjustment signal, a voltage controlled oscillator controlled by a phase difference signal output from the phase comparator, and an oscillation output from the voltage controlled oscillator. A counter for counting a signal; an externally input arbitrary set value; and a set timing control means for controlling a timing value for changing a set timing control counter value to the set value so as not to match; and a count value of the counter. When the set timing control counter value, the adjustment signal generation means for outputting the adjustment signal, and a synchronization signal generation means for outputting a synchronization signal when the counter reaches a predetermined count value A camera device comprising a phase synchronization circuit comprising: 4. The setting timing control means includes timing signal generating means for generating first and second setting timing signals output at a predetermined timing, and at least the setting value and the first timing signal. 4. The camera device according to claim 3, wherein when the output timings match, the second timing signal changes the set timing control counter value to the set value.