JPH08125529A - PLL circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] The PLL lock time is shortened by generating and outputting a signal having a frequency closest to the input signal in response to switching. [Structure] VCO (Voltage Controlled Osc.) Unit 1
, A programmable frequency divider (1 / N) 2, a phase comparator 3, a low-pass filter (LPF) 4, and an A for converting the integrated voltage value of the low-pass filter 4 into digital data.
RO for storing the / D conversion unit 5 and the lookup table
An M7 and a control unit 8 that controls each unit and supplies a required frequency division ratio to the programmable frequency division unit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a PLL (Phase Locked Loop:
Phase-Locked Loop) circuit.

[0002]

2. Description of the Related Art PDP (plasma display panel)
Various video signals such as an NTSC television signal, a personal computer signal, a non-standard video signal, etc. are input to the display monitor using the above. In order to properly display this video signal, it is necessary to synchronize the phase of the display synchronizing signal on the PDP side with the phase of the input video signal. FIG. 4 shows a conventional PLL circuit capable of widening a frequency band for inputting various video signals. 1 is VCO (Voltage Contro)
lled Osc.) section, 2 is programmable frequency division section (1 /
N), 3 is a phase comparator, 4 is a low-pass filter (LP
F), 10 detects the error voltage of the phase comparator 3,
This is a frequency division ratio generation unit that supplies a required frequency division ratio to the programmable frequency division unit 2 based on the same error voltage.

The output fc of the VCO section 1 is input to the programmable frequency dividing section 2 where it is divided into 1 / N. The phase comparator 3 compares the phase of the output fc / N (comparison signal) of the programmable frequency divider 2 with the reference input signal fIN, and outputs an error voltage according to the phase difference. Low pass filter 4
Forms a PLL control voltage VE for controlling the direction in which the error voltage is integrated to reduce the error voltage, and this is fed back to the VCO unit 1.

By the way, as shown in FIG. 5, the reference input signal fin1 and the discrete comparison signal of the programmable frequency divider 2 of the PLL circuit are f1 and the synchronous convergence range of the PLL circuit is plus or minus with respect to f1. If Δ, this PLL circuit has the reference input signal fin1 at a predetermined synchronization convergence time.
To lock. Next, when the reference input signal is switched to fin2, this reference input signal is fin2, and when the discrete comparison signal of the programmable frequency divider 2 is f1, the PLL
Since it is out of the synchronous convergence range of the circuit, the frequency is not locked as it is. The frequency division ratio generation unit 10 continues to detect the error voltage of the phase comparison unit 3 for a predetermined time ta, and switches the frequency division ratio supplied to the programmable frequency division unit 2 when the error voltage does not lock within a predetermined value. That is, the frequency division ratio is switched so that the discrete comparison signal of the programmable frequency division unit 2 becomes f2. Since the synchronization convergence range of the PLL circuit is plus or minus Δ around f2, this PLL circuit locks to the reference input signal fin2 in a predetermined synchronization convergence time.
Similarly to the above description, when the reference input signal is switched to fin3, the frequency division ratio generation unit 10 continues to detect the error voltage of the phase comparison unit 3 for a predetermined time ta, and the programmable frequency division unit according to the result. 2 is supplied with the required division ratio.

However, a conventional PLL that performs the above-mentioned operation
For example, as shown in FIG. 5, when the comparison signal of the programmable frequency divider 2 is discretely three kinds of f1, f2, and f3, for example, the comparison signal is in phase synchronization with the reference input signal fin1. In this state, when the reference input signal is switched to fin3, the convergence operation is performed while switching the comparison signal of the programmable frequency divider 2 in the order of f2 and f3, so that the synchronous convergence time is three times ta. Therefore, there is a problem that a high-speed response (frequency lock) is difficult when switching the reference input signal.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a PLL circuit capable of responding to the switching of an input video signal at a high speed (frequency lock).

[0007]

In order to achieve the above object, the phases of a reference input signal and a comparison signal are compared by a phase comparison unit, the comparison error is integrated by a low-pass filter, and based on the integration value. A PLL circuit in which the output of the voltage controlled oscillator is controlled so that the comparison error is minimized, and the comparison signal is generated by dividing the output with a required frequency division ratio in the frequency divider. In, a frequency division ratio for generating a comparison signal having a frequency closest to the reference input signal is generated based on the integral value, and the same frequency division ratio is supplied to the frequency division unit.

Further, the phases of the reference input signal and the comparison signal are compared by a phase comparison unit, the comparison error is integrated by a low-pass filter, and voltage control oscillation is performed based on the integration value so that the comparison error is minimized. In the PLL circuit in which the output of the unit is controlled, and the output is divided by a dividing unit with a required division ratio, the corresponding frequency is obtained from the integrated value in the PLL circuit. A frequency division ratio for generating a comparison signal having a frequency closest to the reference input signal is generated based on the corresponding frequency, and the same frequency division ratio is supplied to the frequency division unit.

Further, the phases of the reference input signal and the comparison signal are compared in a phase comparison unit, the comparison error is integrated by a low pass filter, and voltage control oscillation is performed based on the integration value so that the comparison error is minimized. In the PLL circuit in which the comparison signal is generated by controlling the output of the unit and dividing the output by the dividing unit with a required dividing ratio, the frequency detecting unit detects the frequency from the reference input signal. The frequency is detected, a frequency division ratio for generating a comparison signal closest to the frequency is generated based on the frequency, and the frequency division ratio is supplied to the frequency division unit.

[0010]

With the above configuration, when the reference input signal is switched, the frequency division section outputs a predetermined comparison signal (reference comparison signal) having the minimum frequency, for example.
The comparison error integrated value of the low-pass filter is A / D converted, and the required division ratio is obtained from the comparison error magnitude and division ratio lookup table stored in ROM in advance based on the magnitude of the comparison error. , The same frequency division ratio is supplied to the frequency division section.

In another configuration, when the reference input signal is switched, the frequency division section outputs a signal having a predetermined frequency, for example, the minimum frequency (reference signal), and the comparison error integral value of the low-pass filter is set. A / D conversion is performed, and the voltage / frequency conversion unit obtains a corresponding frequency from the magnitude of the comparison error,
The required frequency division ratio is obtained in advance from the lookup table of the frequency and frequency division ratio stored in the ROM, and the same frequency division ratio is supplied to the frequency division unit.

In another configuration, the reference input signal is counted, for example, to find the frequency, and the frequency is obtained. Based on the frequency, the lookup table of the frequency and the frequency division ratio stored in the ROM in advance is used. A required frequency division ratio is obtained and the same frequency division ratio is supplied to the frequency division section. Therefore, in any of the configurations, the frequency division section immediately generates the comparison signal including the reference input signal in the convergence range, so that the PLL synchronously converges at high speed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a PLL according to the present invention.
It is an example block diagram of a circuit. 1 is VCO (Voltag
e Controlled Osc.) section, 2 programmable frequency division section (1 / N), 3 phase comparison section, 4 low pass filter (LPF), 5 converts the integrated voltage value of the low pass filter 4 into digital data A / D conversion unit, 7 is a ROM that stores a look-up table, and 8 is a control unit that controls each unit and supplies a required frequency division ratio to the programmable frequency division unit 2.

The operation of the PLL circuit according to the present invention will be described with reference to FIGS. A description of the PLL operation similar to that of the conventional example is omitted, and an operation of generating a comparison signal having a frequency closest to the frequency of the reference input signal when the reference input signal is switched will be described. When the reference input signal is switched, the programmable frequency division unit 2 is in an output state of, for example, a minimum frequency signal (reference signal) with a predetermined frequency division ratio.
The A / D conversion unit 5 generates voltage data by converting the comparison error integral value (control voltage) of the low-pass filter 4 that controls the VCO 1 into digital data, and supplies the voltage data to the ROM 7. The ROM 7 stores the comparison error integral value stored in advance,
The lookup table corresponding to the frequency division ratio data is referred to, the corresponding frequency division ratio data is read, and the same frequency division ratio data is supplied to the programmable frequency division unit 2 via the control unit 8. In FIG. 2, the horizontal axis indicates the comparison error integrated value (voltage).
When the frequency of the reference input signal is equal to the reference signal, it is zero, and the voltage value proportional to the frequency of the reference input signal is shown.
The vertical axis indicates the frequency division ratio corresponding to the voltage value on the horizontal axis. For example, zero voltage corresponds to the minimum frequency division ratio, and maximum voltage corresponds to the maximum frequency division ratio.

In another configuration example (not shown) in which a voltage / frequency conversion unit is added to the block diagram of the embodiment of the PLL circuit of FIG. 1, the A / D conversion unit 5 has a low-pass filter for controlling the VCO 1. The comparison error integrated value (control voltage) of No. 4 is converted into digital data to generate voltage data, which is supplied to the voltage / frequency conversion unit 6. The voltage / frequency conversion unit 6 generates frequency data corresponding to the voltage data. Generate and ROM7
The ROM 7 stores in advance a look-up table in which the frequency data and the division ratio data are associated with each other, and the look-up table is referred to based on the frequency data to obtain the corresponding division ratio data. And the same frequency division ratio data via the control unit 8 to the programmable frequency division unit 2
It is also possible to supply to. In addition, in the other configuration example,
The horizontal axis of FIG. 2 is the comparison error integrated value (voltage), which is zero when the frequency of the reference input signal is equal to the reference signal, and shows a voltage value proportional to the frequency of the reference input signal. The vertical axis represents the frequency corresponding to the voltage value on the horizontal axis. For example, zero voltage corresponds to the minimum frequency signal (reference signal), and maximum voltage corresponds to the maximum frequency signal.

FIG. 3 is a block diagram of another embodiment of the PLL circuit according to the present invention. Incidentally, the same parts as those in FIG. Reference numeral 9 is, for example, a frequency detector that counts the falling edge of the reference input signal with a counter and obtains its frequency. Based on the frequency of the reference input signal detected by the frequency detection unit 9, the corresponding frequency division ratio data is read from the ROM 7 with reference to the look-up table, and the frequency division ratio data is programmable through the control unit 8. Supply to part 2. The memory for storing the look-up table is not limited to the ROM and may be, for example, EE.
It may be a PROM (electrically rewritable ROM), a rewritable flash memory, or the like. Further, although the comparison signal is generated by frequency division in the above description, it is not limited to frequency division and may be applied to, for example, a circuit configuration in which the oscillation frequency of the VCO is multiplied to obtain a high-speed clock signal. . Further, since the comparison error integrated value is generally an absolute value, there are a frequency division ratio (A) for the positive comparison error integrated value and a frequency division ratio (B) for the positive comparison error integrated value. The frequency ratio (A) is supplied, and it is detected whether or not to lock in a predetermined time. If the frequency is not locked, then the frequency division ratio (B) may be supplied.

[0017]

As described above, the present invention provides a PLL circuit capable of fast frequency locking when switching input video signals. Therefore, when various video signals such as an NTSC TV signal, a personal computer signal and a non-standard video signal are switched and input to a display monitor using a PDP (plasma display panel) or the like, a clock locked to the phase of the reference input signal Generate signals at high speed. Then, there is an advantage that a horizontal synchronizing signal and a vertical synchronizing signal for display are generated based on this clock signal, and the display disorder of the switching screen can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a diagram showing a relationship between a comparison error integral value (control voltage) and a frequency division ratio of the PLL circuit according to the present invention.

FIG. 3 is a block diagram of another embodiment of the PLL circuit according to the present invention.

FIG. 4 shows a conventional PLL circuit that supports a wide frequency band for inputting various video signals.

FIG. 5 is a diagram showing a reference input signal, a comparison signal, and an overlapping lock range of a PLL circuit.

[Explanation of symbols]

 1 VCO (Voltage Controlled Osc.) Section 2 Programmable frequency division section 3 Phase comparison section 4 Low pass filter (LPF) 5 A / D conversion section 6 Voltage / frequency conversion section 7 ROM 8 Control section 9 Frequency detection section 10 Frequency division ratio generation Department

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display area H04L 7/02 B

Claims (8)

[Claims] 1. A voltage controlled oscillator for comparing the phases of a reference input signal and a comparison signal in a phase comparison unit, integrating the comparison error by a low-pass filter, and minimizing the comparison error based on the integrated value. In the PLL circuit in which the comparison signal is generated by controlling the output of the unit and dividing the output by the dividing unit with a required division ratio, A PLL circuit characterized in that a frequency division ratio for generating a comparison signal is generated based on the integrated value, and the same frequency division ratio is supplied to a frequency division unit. 2. The PLL circuit according to claim 1, wherein the integrated value is converted into a digital value by an A / D converter, and the frequency division ratio is obtained from the digital value. 3. The PLL circuit according to claim 2, wherein the frequency division ratio is stored in a ROM as lookup data corresponding to the digital value. 4. A voltage control oscillation for comparing the phases of a reference input signal and a comparison signal in a phase comparison unit, integrating the comparison error by a low pass filter, and minimizing the comparison error based on the integration value. In a PLL circuit in which the output of the unit is controlled and the output is divided by a frequency division unit at a required frequency division ratio, a corresponding frequency is obtained from the integrated value, A PLL circuit characterized in that a frequency division ratio for generating a comparison signal having a frequency closest to the reference input signal is generated based on the corresponding frequency, and the same frequency division ratio is supplied to a frequency division unit. 5. The PLL circuit according to claim 4, wherein the frequency division ratio is stored in a ROM as lookup data corresponding to the corresponding frequency. 6. A voltage-controlled oscillation in which a phase of a reference input signal and that of a comparison signal are compared by a phase comparison unit, the comparison error is integrated by a low-pass filter, and the comparison error is minimized based on the integration value. In the PLL circuit in which the comparison signal is generated by controlling the output of the unit and dividing the output by the dividing unit with a required dividing ratio, the frequency detecting unit detects the frequency from the reference input signal. A PLL circuit which detects the frequency, generates a frequency division ratio for generating a comparison signal closest to the frequency based on the frequency, and supplies the frequency division ratio to a frequency division unit. 7. The PLL according to claim 6, wherein the frequency detecting section comprises a counter for counting the frequency of the reference input signal.
circuit. 8. The PLL circuit according to claim 6, wherein the frequency division ratio is stored in a ROM as lookup data corresponding to the frequency of the reference input signal.