JPH1154733A - Semiconductor integrated circuit device and manufacturing method thereof, semiconductor substrate for semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device including a plurality of types of chips having different chip sizes by preparing one type of diffusion wafer, chips having the same chip size but different arrangements of pads and the like, and a method of manufacturing the same. And a semiconductor substrate. SOLUTION: In a gate array type semiconductor integrated circuit device, the same unit cell 9 composed of the same transistor is arranged on the entire surface of a chip 1. The input / output circuit 3 and the internal circuit 2 forming a chip formed by wiring diffusion wafers are formed from the same transistors forming the same unit cell. By arranging an input / output circuit and an internal circuit at arbitrary positions, a semiconductor integrated circuit having an arbitrary pad arrangement and a semiconductor integrated circuit having an arbitrary chip size can be produced from the same diffusion wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a cell configuration before a wiring process used in a gate array type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A gate array is an array of gates such as inverters and NANDs, which are the basis of a logic circuit, arranged in a row on a semiconductor chip (hereinafter referred to as a chip). The purpose is to simplify the design by structure. Since the design proceeds while expressing all the logic by a limited number of basic gates (hereinafter, referred to as unit cells), both the logic design and the layout design are simplified. The interconnecting of the arranged gates is performed using a passage (channel) between the gate rows. Generally, in a gate array type semiconductor integrated circuit device, a common pattern is formed up to a diffusion step, and a pattern specific to a product is formed in a subsequent wiring step. In a conventional gate array type semiconductor integrated circuit device (gate array chip),
An internal circuit cell forming a unit cell forming a logic circuit and an I / O forming a unit cell forming an input / output circuit
The O cells have different patterns from each other, the internal cells are arranged in a chip central region, and the I / O cells are arranged in a chip peripheral region. That is, cells constituting an internal circuit such as a logic circuit and cells constituting an input / output circuit have different structures such as a gate length and a gate width.

FIGS. 16 and 17 are plan views showing a part of a conventional semiconductor wafer (hereinafter, referred to as a wafer). FIG. 16 shows a part of a wafer (diffusion wafer) subjected to processing up to the diffusion step, and FIG. 17 shows a part of a wafer formed by performing a wiring step of the next step to form a pattern unique to a product. In the chip formation region 11 of the diffusion wafer, an internal circuit formation region 12 is formed at a central portion, and an input / output circuit formation region 13 is defined around the internal circuit formation region 12. The wafer in which the wiring process is performed on the diffusion wafer to form a unique pattern as a product is provided with a pad electrode (pad) in a region where the internal circuit 2 and the input / output circuit 3 are arranged and no peripheral element is formed. 4 are formed. FIG. 18 is a plan view of a chip forming region of a conventional wafer, and FIG. 19 is a plan view showing a conventional chip. As shown in FIG. 18, in the internal circuit formation region 12, unit cells 5 composed of the same transistor are arranged in a matrix. In the input / output circuit formation region 13, a plurality of unit cells 6 each including a transistor whose type and size are not fixed are arranged. The transistors of the input / output circuit are not always the same as the transistors of the internal circuit, and usually the type and size are not constant. FIG.
8 is subjected to a wiring process to obtain a chip 1 shown in FIG.
Is formed. Pads 4 are formed in the peripheral portion of the chip 1, and the pads 4 are electrically connected to the input / output circuit 3, and the input / output circuit 3 and the internal circuit 2 are electrically connected to each other by the wiring 7.

[0004]

In the conventional gate array type semiconductor integrated circuit device, the pads are drawn out from the I / O cell portion, so that the arrangement is limited to the chip peripheral portion and the number of pads is limited. Has a specific number.
Therefore, if the number of pads is increased or the pads are arranged at the center of the chip, another diffusion wafer (a non-wired wafer that has not undergone a wiring process: DW (Diffusion)
Wafer)) had to be prepared. Due to recent advances in packaging technology, the range of use of the number of electrode pins of a semiconductor integrated circuit has been widened (about 20 to 300 pins). I needed to. In addition, even if the chip size is the same, a product requiring a pad in the center of the chip requires a separate diffusion wafer, which causes a problem of increasing development costs. FIG.
FIG. 4 is a cross-sectional view illustrating a manufacturing process from a diffusion wafer (DW) to a wafer (W) formed by performing a wiring process. A diffusion region (not shown) forming a transistor is formed on the diffusion wafer 10. Chip forming regions 11 of the same size including a plurality of the diffusion regions are partitioned in a matrix.

[0005] Wiring is performed on the diffusion wafer 10 to form a wafer (W) in which the chip 1 having the input / output circuit, the internal circuit, and the pad is formed in the chip forming region 11. The size of the chip 1 differs depending on the wafer (W) 10, and the chip 1 of the first wafer (W1) 10
Wafer (W2) 10 is larger than chip 1. As described above, to manufacture products having different chip sizes, as described above, the first wafer (W1) has the first diffusion wafer (DW1), and the second wafer (W2) has the second diffusion wafer. As in (DW2), it was necessary to use separate diffusion wafers. The present invention has been made in view of such circumstances, and a plurality of types of integrated circuit chips having different chip sizes by preparing one type of diffusion wafer or integrated circuit chips having the same chip size but different pad arrangements are provided. And a method of manufacturing the same, and a semiconductor substrate on which the semiconductor integrated circuit device is formed.

[0006]

In a semiconductor integrated circuit device of a gate array system, the same unit cell composed of the same transistor is arranged on the entire surface of a chip. Therefore, the input / output circuit and the internal circuit constituting the chip formed by wiring the diffusion wafer are:
They are formed from the same transistors constituting the same unit cell. Further, when the wafer is cut to form a plurality of chips, the transistors of the unit cells can be used for a test element, a mark, and the like arranged in a scribe line region formed on the wafer. By arranging an input / output circuit and an internal circuit at arbitrary positions, a semiconductor integrated circuit having an arbitrary pad arrangement and a semiconductor integrated circuit having an arbitrary chip size can be produced from the same diffusion wafer. That is, a semiconductor substrate for a semiconductor integrated circuit device of the present invention includes a semiconductor wafer and a plurality of unit cells formed on the semiconductor wafer and configured with a plurality of transistors of the same shape arranged in a matrix. The first feature, a semiconductor wafer, a unit cell formed on the semiconductor wafer, and configured from a plurality of transistors of the same shape arranged in a matrix, and formed by wiring the transistors of the unit cell A second feature is that the semiconductor device has a plurality of semiconductor chip areas in which input / output circuits and internal circuits are arranged, and scribe lines formed between the semiconductor chip areas.

According to a semiconductor integrated circuit device of the present invention, a semiconductor substrate, a unit cell composed of a plurality of transistors of the same shape formed on the semiconductor substrate and arranged in a matrix, and a transistor of the unit cell are wired. And an input / output circuit electrically connected to the internal circuit and formed by wiring transistors of the unit cell, and an input / output circuit electrically connected to the input / output circuit and insulated on the unit cell. And a pad electrode formed via a film. A method of manufacturing a semiconductor integrated circuit device according to the present invention includes a first step of arranging unit cells each formed of a plurality of transistors having the same shape in a matrix on a semiconductor wafer, and wiring the transistors of the unit cells. And a second step of arranging a semiconductor chip area on which the input / output circuits and internal circuits are arranged on the semiconductor wafer.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 to FIG.
An example will be described. FIG. 1 is a plan view of a four-chip formation region on a wafer (diffusion wafer) after a diffusion step in which transistors are formed. In each chip forming region 11 on the wafer, a unit cell region 8 is formed almost over the entire surface. Details of the unit cell region 8 are shown in FIG. FIG. 2 is a plan view of one chip forming region on the diffusion wafer. As shown in this figure, unit cells 9 are arranged in a matrix in the unit cell region 8, and are all the same. In a wiring step following the diffusion step, wiring connection of the unit cells 9 is performed to form an internal circuit and an input / output circuit. This unit cell 9 is composed of four transistors. FIG. 3 is a plan view of four chips on a wafer in which wiring is performed on a diffusion wafer to form chips. Unit cell area 8 of each chip 1
Integrated circuit is formed. An internal circuit 2 is formed at the center of the chip 1, and an input / output (I / O) circuit 3 is arranged and formed around the chip around the internal circuit 2. Further, a pad electrode 4 for external connection is formed outside the input / output circuit 3 along a peripheral portion of the unit cell region 8.

FIG. 4 shows details of an integrated circuit formed in the unit cell region 8, and is a plan view of one chip on a wafer subjected to a wiring process. As shown, the unit cells 9 on the chip 1 are connected in an appropriate pattern so as to form an integrated circuit using the wiring 7, and the internal circuit 2, the input / output circuit 3, and the pad 4 are formed. The internal circuit 2 and the input / output circuit 3 are electrically connected by the wiring 7, and the input / output circuit 3 and the pad 4 are also electrically connected by the wiring 7. The chip shown in FIG. 4 differs from the chip shown in FIG. 3 in that the internal circuit 2 is arranged and formed on one side of the chip 1. The pad 4 is formed so as to be biased on one side opposite to the side on which the internal circuit 2 is disposed. The input / output circuit 3 is disposed between the internal circuit 2 and the pad 4. As described above, according to the present invention, the input / output circuit 3 and the internal circuit 2 can be arranged at any place in the chip.

Next, an internal structure below the pad in a portion along the line AA 'in FIG. 4 will be described with reference to FIG. A field oxide film 21 serving as an element isolation region is formed by a LOCOS method or the like on a surface region of a semiconductor substrate 1 made of, for example, silicon, which forms a chip. The source / drain region 22 is formed in the element region surrounded by the element isolation region. A gate electrode 24 made of polysilicon or the like is formed on the semiconductor substrate 1 between the source / drain regions 22 with a gate oxide film 23 interposed therebetween.
The source / drain region 22, the gate oxide film 23 and the gate electrode 24 constitute a transistor constituting the unit cell 9 shown in FIG. A first interlayer insulating film 25 such as a silicon oxide film covering the gate electrode 24 is formed on the semiconductor substrate 1, and a metal wiring 7 such as aluminum is patterned thereon. The wiring 7 is provided with a second interlayer insulating film 26 such as a silicon oxide film.
In the second interlayer insulating film 26, a contact hole is formed above the wiring 7. Next, a pad 4 made of aluminum or the like is formed on the second interlayer insulating film 26 by patterning. The pad 4 is electrically connected to the wiring 7 via a contact hole. At this time, since the transistor under the pad 4 does not constitute any of the input / output circuit 3 and the internal circuit 2, it is not electrically connected to the wiring 7. Second
An insulating protective film 27 such as a silicon nitride film is formed on the interlayer insulating film 26.

As described above, the pad is formed on the transistor constituting the unit cell with the interlayer insulating film interposed therebetween. However, since this transistor is irrelevant to the internal circuit and the input / output circuit, the pad is mechanically connected to the pad. Even if a typical stress acts, these circuits have no effect. Next, a second embodiment will be described with reference to FIG. The figure is a plan view of the chip. In this embodiment, a chip having a structure different from that of FIG. 3 or FIG. 4 is formed from the diffusion wafer shown in FIG. This chip 1 forms a single integrated circuit by combining four chips of the diffusion wafer. In this case, a product of two kinds of chip sizes is made from one kind of diffusion wafer. However, if the basic chip size is reduced, a product of any chip size is made from one kind of diffusion wafer. be able to. As shown in the figure, a wiring process is performed on the diffusion wafer to form a four-chip forming region as one chip. An internal circuit 2 is formed at the center of the chip 1, and an input / output circuit 3 is arranged and formed around the chip around the internal circuit 2. Further, a pad electrode 4 for external connection is formed outside the input / output circuit 3 along a peripheral portion of the unit cell region 8.

Next, the structure of the unit cell formed on the wafer used in the first and second embodiments will be described with reference to FIGS. Each figure is a schematic circuit diagram of a unit cell. The unit cell 9 has a predetermined number of transistors, which are operatively connected to form a basic gate such as an inverter or a NAND. FIG. 7 shows a unit cell having four transistors used in the chips shown in FIGS. The transistors are N-channel MOS transistor (Nch) and P
Two channel MOSs (Pch) are used. In the unit cell 9 of FIG. 8, the transistors are an N-channel MOS transistor (Nch) and a P-channel MOS transistor.
(Pch) are used three each. In the unit cell 9 shown in FIG. 9, four N-channel MOS transistors (Nch) and four P-channel MOS (Pch) transistors are used. The unit cell 9 shown in FIG. 10 uses six NPN transistors (NPN) and two resistors (R).

In general, there are a logic design and a circuit design in a semiconductor device design process. In the logic design, an integrated circuit is embodied to a level in units of a lone gate such as an inverter or a NAND based on functional design data. In logic design, design is performed with a focus on the connection relationship between gates, that is, the logic circuit structure. The circuit design step is a step of realizing a combination of a basic logic unit used for a logic cell library and a transistor library obtained by device design, predicting the performance of the transistor library by a circuit simulator, and providing the parameters in the form of parameters. In a conventional gate array type semiconductor integrated circuit device, the structure and size of a transistor used for an internal circuit or an input / output circuit are determined by logic design, whereas in the present invention, one type of transistor having a predetermined performance is used. Circuit design is performed.

FIG. 11 shows a diffusion wafer (DW) of the present invention.
FIG. 4 is a cross-sectional view illustrating a manufacturing process from a wafer (W) formed by performing a wiring process. Diffusion wafer (D
In W) 10, a diffusion region (not shown) forming a transistor is formed. The transistors constitute unit cells arranged in a matrix. Since all the unit cells are the same in the diffusion wafer, it is not necessary to partition the chip formation region in advance. Wiring is applied to this diffusion wafer (DW) 10 to provide an input / output circuit,
A wafer (W) on which a chip 1 having internal circuits and pads is formed is formed. The size of the chip 1 depends on the wafer (W) 10, and the first wafer (W 1) 1
The chip 1 of 0 is larger than the chip 1 of the second wafer (W2) 10. Thus, products with different chip sizes are made from the same diffusion wafer. From one diffusion wafer, third, fourth,.
・ The wafer can be formed.

Next, a third embodiment will be described with reference to FIG. The figure is a plan view of a wafer on which a plurality of chips are formed by performing a wiring process on a diffusion wafer. A plurality of chips 1 are formed in a matrix on the wafer 10 that has been subjected to the wiring process. Each chip 1
An internal circuit 2 is formed in a central portion, and an input / output circuit 3 is formed around the internal circuit. Further, pads (not shown) are formed on four sides of the chip 1. On the wafer 10, unit cells 9 including transistors and the like are formed on almost the entire one main surface of the wafer 10. Some are used for the internal circuit 2 and the input / output circuit 3 in the chip area. The unit cell other than the intended use does not do anything or is given some role as needed. For example, unit cells 9 are also arranged and formed in a region between the chips 1. This region is where a scribe line used when cutting the wafer 10 to cut out the chips 1 is arranged and formed, and the wafer 10 is cut along this line. Since the unit cell 9 formed at this position is not used for the internal circuit 2 or the input / output circuit 3, it can be used for a test circuit for inspecting the performance of the chip 1 or an alignment mark at the time of cutting.

Next, the operation and effect of the present invention will be described with reference to the input / output circuits shown in FIGS. FIG. 13 is a circuit diagram showing the present invention and a conventional input / output circuit, FIG. 14 is a block diagram schematically showing the internal structure of the input / output circuit of the present invention, and FIG. It is a block diagram which shows typically. The input / output circuit has an output buffer and an input buffer, one end of which is connected to a pad (input / output terminal) and the other end of which is connected to an internal circuit. The transistors are N-channel MOS transistors Q1, Q3, Q
5 and P-channel MOS transistors Q2, Q4, Q6
It is composed of In the transistor Q1, one of the source / drain regions is connected to a pad, and the other is grounded. In the transistor Q2, one of a source / drain region is connected to a pad, and one of the source / drain regions of the transistor Q1 is connected, and the other is connected to a power supply. In the transistor Q3, one of a source / drain region is connected to the gate of the transistor Q2, and the other is grounded. In the transistor Q4, one of a source / drain region is connected to the gate of the transistor Q2, and is connected to one of the source / drain regions of the transistor Q3, and the other is connected to a power supply. In the transistor Q5, one of a source / drain region is connected to the gate of the transistor Q1, and the other is grounded.
The transistor Q6 has one of a source / drain region connected to the gate of the transistor Q1 and one of the source / drain regions of the transistor Q5, and the other connected to a power supply.

FIGS. 14 and 15 show the size of the transistors constituting such an input / output circuit in terms of the area shown in FIGS.
become that way. That is, the size of the diffusion region (SDG) in which the gate is formed represents the size of the transistor. Conventionally, as shown in FIG. 15, a diffusion region corresponding to the size of a transistor is formed, so that a plurality of types of diffusion regions having different areas are formed, whereas the transistor of the present invention shown in FIG. All of the diffusion regions have the same size, and one transistor includes a plurality of diffusion regions. That is, one transistor includes at least one small transistor, and only the small transistor is formed on the chip.

[0018]

In the conventional gate array type semiconductor integrated circuit device, when developing products having different numbers of pins, it is necessary to prepare five to seven types of diffusion wafers having different chip sizes. . Further, even if the pad electrodes are arranged inside the chip even for the same chip size, another diffusion wafer is required, and development costs for preparing the diffusion wafer and enormous costs for storing a large number of diffusion wafers have been required. According to the present invention, an integrated circuit having a different chip size or an integrated circuit having a different pad arrangement can be provided only by preparing one kind of diffusion wafer.

[Brief description of the drawings]

FIG. 1 is a plan view of a chip formation region of a diffusion wafer according to the present invention.

FIG. 2 is an enlarged plan view of a chip formation region of a diffusion wafer according to the present invention.

FIG. 3 is a plan view of a chip formed on the wafer of the present invention.

FIG. 4 is an enlarged plan view of the chip of the present invention.

FIG. 5 is a sectional view of a portion along the line AA ′ in FIG. 4;

FIG. 6 is a plan view of a chip according to the present invention.

FIG. 7 is a schematic circuit diagram of a unit cell formed on a chip of the present invention.

FIG. 8 is a schematic circuit diagram of a unit cell formed on a chip of the present invention.

FIG. 9 is a schematic circuit diagram of a unit cell formed on a chip of the present invention.

FIG. 10 is a schematic circuit diagram of a unit cell formed on a chip of the present invention.

FIG. 11 is a plan view of a wafer for explaining a manufacturing process of the present invention.

FIG. 12 is a plan view of a wafer according to the present invention.

FIG. 13 is a circuit diagram of an input / output circuit of the semiconductor integrated circuit device of the present invention.

FIG. 14 is a circuit diagram of an input / output circuit of the semiconductor integrated circuit device of the present invention.

FIG. 15 is a circuit diagram of an input / output circuit of a conventional semiconductor integrated circuit device.

FIG. 16 is a plan view of a chip forming region of a conventional diffusion wafer.

FIG. 17 is a plan view of a chip region of a conventional wafer.

FIG. 18 is an enlarged plan view of a chip formation region of a conventional wafer.

FIG. 19 is an enlarged plan view of a conventional chip.

FIG. 20 is a plan view of a wafer for explaining a conventional manufacturing process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Chip (semiconductor substrate), 2 ... Internal circuit, 3 ... Input / output circuit, 4 ... Pad, 5
6, 9 ... unit cell (basic gate), 7 ...
Wiring, 8: Unit cell area, 10: Wafer, 11: Chip formation area, 12: Internal circuit formation area, 13: Input / output circuit formation area,
21 ... field oxide film, 22 ... source / drain region, 23 ... gate oxide film, 24 ... gate electrode, 25, 26 ... interlayer insulating film, 27 ...
・ Protective insulating film.

Claims (8)

[Claims] 1. A semiconductor integrated circuit device comprising: a semiconductor wafer; and a plurality of unit cells formed on the semiconductor wafer and composed of a plurality of transistors of the same shape arranged in a matrix. For semiconductor substrate. 2. A semiconductor wafer, a unit cell formed on the semiconductor wafer and configured by a plurality of transistors of the same shape arranged in a matrix, and an input / output formed by wiring the transistors of the unit cell. A semiconductor substrate for a semiconductor integrated circuit device, comprising: a plurality of semiconductor chip regions in which circuits and internal circuits are arranged; and scribe lines formed between the semiconductor chip regions. 3. The semiconductor integrated circuit device according to claim 2, wherein the transistor of the unit cell arranged in the area where the scribe line is formed is used as a positioning mark or a test element. Semiconductor substrate. 4. An internal circuit formed by wiring a semiconductor substrate, a unit cell formed on the semiconductor substrate and composed of a plurality of transistors of the same shape arranged in a matrix, and transistors of the unit cell. And an input / output circuit electrically connected to the internal circuit and formed by wiring transistors of the unit cell; and an electrical connection to the input / output circuit via an insulating film on the unit cell. A semiconductor integrated circuit device comprising: a formed pad electrode. 5. The semiconductor integrated circuit device according to claim 4, wherein said pad electrode is disposed at a central portion on said semiconductor substrate. 6. The semiconductor integrated circuit device according to claim 4, wherein said pad electrode is arranged at a peripheral portion on said semiconductor substrate. 7. A first step of arranging unit cells composed of a plurality of transistors of the same shape in a matrix on a semiconductor wafer, and an input / output circuit and an internal circuit formed by wiring the transistors of the unit cells. And a second step of arranging a semiconductor chip region on which the semiconductor chips are arranged on the semiconductor wafer. 8. After the first step, a step of arranging transistors of the unit cell and arranging a semiconductor chip region of a predetermined size on a first semiconductor wafer is performed, and then the first step is performed. After that, the transistor of the unit cell is wired on the second semiconductor wafer, and a semiconductor chip area larger than the semiconductor chip area arranged on the first semiconductor wafer is arranged. 8. The method according to claim 7, further comprising the step of arranging semiconductor chip regions having different sizes.