JPH117385A - Operation processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce capacity of memory in which microcode is stored. SOLUTION: An operation processor is provided with an NM memory 42 in which the microcode is stored, an instruction execution block 17 to read a macro code and to execute the instruction based on the microcode and an operation circuit block 18 to perform a specified operation processing according to an instruction of the instruction execution block 17 and when the specified operation processing is performed by the operation circuit block 18, an MM address when the microcode is read is locked until the operation processing is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit, and more particularly, to a reduction in the capacity of a storage device storing its microcode.

[0002]

2. Description of the Related Art Conventionally, for example, an arithmetic processing unit used in a programmable controller (hereinafter referred to as a PC) uses a 4-byte microcode to describe an operation of one cycle (0.05 μS). is there. In the case of such a PC, for example, the execution time is 2.
It took 188 bytes to execute the multiply instruction, which took 35 μS.

FIG. 6 is an explanatory diagram showing the contents of a microcode when performing a conventional multiplication process. As shown, 4
Although seven cycles are required, the instruction execution block (see FIG. 1) is substantially in an unexecuted state during the cycles 6 to 41, and the arithmetic circuit block (see FIG. 1) exclusively performs its arithmetic processing. ing.

[0004]

As described above, the execution of a multiplication instruction requires 188 bytes (47 cycles.times.4) of microcode, but the memory for storing the microcode is necessarily limited in its capacity. Because there is
It has been desired to save memory capacity when storing microcode.

[0005] The present invention has been made in view of such circumstances, and has as its object to provide an arithmetic processing device capable of reducing the capacity of a memory for storing microcode.

[0006]

An arithmetic processing unit according to the present invention comprises: a memory in which microcode is stored; an instruction execution means for reading out microcode and executing an instruction based on the microcode; and an instruction execution means. And an arithmetic circuit for performing a predetermined arithmetic processing in accordance with the instruction. When the arithmetic circuit performs the predetermined arithmetic processing, the address for reading the microcode is locked until the arithmetic processing is completed.

[0007]

FIG. 1 is a block diagram showing a configuration of a gate array of an arithmetic processing unit according to one embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a gate array, 11 to 19
Are functional blocks included in the gate array 10, respectively. Reference numeral 11 denotes a CPU interface block, which performs an interface between the gate array 10 and the external CPUs 31 and 32. Reference numeral 12 denotes a trap circuit block, which traps a UM (user memory) address. Reference numeral 13 denotes a UM memory interface block which exchanges a user program with the UM memory 41. 14 is an MM memory interface block, which is an MM memory 4
2 and microloading. Reference numeral 15 denotes a VM memory interface block, which exchanges status and data with the VM memory 43. An instruction decode block 16 analyzes an instruction word and generates a microcode address corresponding to the analysis result. Reference numeral 17 denotes an instruction execution block, which executes an instruction based on microcode. Reference numeral 18 denotes an arithmetic circuit block which performs arithmetic processing. Reference numeral 19 denotes a control block, which controls the entire gate array 10.

FIG. 2 is an explanatory diagram of a cycle of the pipeline processing of the gate array 10 of FIG. As shown in the figure, in the cycle 1, the instruction word is read from the UM memory 41 by the UM memory interface block 13, and in the cycle 2, the instruction word is decoded by the instruction decode block 16, and in the cycle 3, the instruction word is read by the MM memory interface block 14. The microload corresponding to the decoded instruction word is read from the MM memory 42, and in cycle 4, the instruction execution block 17 executes the instruction based on the microcode.

FIG. 3 is an explanatory diagram showing an example of instruction execution by pipeline processing. In the illustrated example, the instruction execution is completed every cycle after cycle 4.

FIG. 4 is a diagram showing the contents of the microcode when performing the multiplication processing in the arithmetic processing unit of FIG.
The data of the accumulator of the instruction execution block 17 is set to the operation input A of the operation circuit block 18, the data of the data register of the instruction execution block 17 is set to the operation input B of the operation circuit block 18, and the operation command is reset. Thus, the operation up to the point where the clock is started is the same as the conventional one (see FIG. 6), but the subsequent processing is different from the conventional one. Microcode "Multiplication instruction start / MM
When the multiplication is started based on the "address hold instruction", the MM address is held at the address at that time (without incrementing). For example, the MM address is held.
By setting the microcode having such contents, the instruction decode block 16 allows the operation circuit block 1
Until the multiplication is completed at 8, the above-mentioned microcode at the same address is read out, thereby holding the MM address. When the arithmetic circuit block 18 completes the arithmetic processing, the subsequent processing is the same as in the conventional case, the MM address is incremented, the arithmetic result is set in the accumulator of the instruction execution block 17, and the clock is stopped. , The operation result flag is processed, and the instruction execution is completed.

FIG. 5 is a time chart showing the above processing. In FIG. 5, processing 1 corresponds to the microcode "multiplication instruction start / MM address hold instruction" in FIG. 4, and processing 2 corresponds to the microcode "MM address hold instruction if the operation is not completed". MM address is "n + 2" →
"N + 3" → "n + 2" → "n + 3"... MM addresses "n + 2" and "n + 3" are repeated, so that the process 2 is repeated. That is, in the conventional method, the MM address is incremented when the processing of each cycle is completed, but in the present embodiment, the MM address is locked as described above. Therefore, in the present embodiment, the MM memory 42 has a storage capacity for 12 cycles. Thus, in connection with the prior art of FIG. 6, a memory saving of (47−12) × 4 = 140 bytes.

The arithmetic processing in the present invention is not limited to the above-described multiplication processing, but also includes arithmetic operations such as division, rotation, shift, and the like, which are processed in the arithmetic circuit block 18.

[0013]

As described above, according to the present invention, a memory in which microcode is stored, instruction execution means for reading out microcode and executing an instruction based on the microcode, and instructions in accordance with instructions from the instruction execution means An arithmetic circuit for performing predetermined arithmetic processing, and when the arithmetic circuit performs the predetermined arithmetic processing, an address for reading the microcode is locked until the arithmetic processing is completed. The capacity of the memory to be stored can be saved, and the memory can be used for other purposes.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an arithmetic processing device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a cycle of a pipeline process of the arithmetic processing device of FIG. 1;

FIG. 3 is an explanatory diagram showing an example of instruction execution by pipeline processing.

FIG. 4 is a diagram showing the contents of a microcode when performing a multiplication process in the arithmetic processing device of FIG. 1;

FIG. 5 is a time chart showing the processing of FIG. 3;

FIG. 6 is an explanatory diagram showing the contents of microcode when performing a conventional multiplication process.

Claims (1)

[Claims] 1. A memory in which microcode is stored;
An instruction execution unit that reads the microcode and executes an instruction based on the microcode; and an operation circuit that performs a predetermined operation according to an instruction from the instruction execution unit, and causes the operation circuit to perform the predetermined operation. An arithmetic processing device, wherein an address for reading the microcode is locked until the arithmetic processing is completed.