JPS5248979A - Process for production of complementary type mos integrated circuit de vice - Google Patents

Process for production of complementary type mos integrated circuit de vice

Info

Publication number
JPS5248979A
JPS5248979A JP50124917A JP12491775A JPS5248979A JP S5248979 A JPS5248979 A JP S5248979A JP 50124917 A JP50124917 A JP 50124917A JP 12491775 A JP12491775 A JP 12491775A JP S5248979 A JPS5248979 A JP S5248979A
Authority
JP
Japan
Prior art keywords
vice
production
integrated circuit
type mos
complementary type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50124917A
Other languages
English (en)
Inventor
Masahiko Yasuoka
Hiroshi Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP50124917A priority Critical patent/JPS5248979A/ja
Priority to US05/732,859 priority patent/US4084311A/en
Publication of JPS5248979A publication Critical patent/JPS5248979A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP50124917A 1975-10-17 1975-10-17 Process for production of complementary type mos integrated circuit de vice Pending JPS5248979A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP50124917A JPS5248979A (en) 1975-10-17 1975-10-17 Process for production of complementary type mos integrated circuit de vice
US05/732,859 US4084311A (en) 1975-10-17 1976-10-15 Process for preparing complementary MOS integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50124917A JPS5248979A (en) 1975-10-17 1975-10-17 Process for production of complementary type mos integrated circuit de vice

Publications (1)

Publication Number Publication Date
JPS5248979A true JPS5248979A (en) 1977-04-19

Family

ID=14897315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50124917A Pending JPS5248979A (en) 1975-10-17 1975-10-17 Process for production of complementary type mos integrated circuit de vice

Country Status (2)

Country Link
US (1) US4084311A (ja)
JP (1) JPS5248979A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5810856A (ja) * 1981-07-10 1983-01-21 Nec Corp 相補型半導体集積回路装置の製造方法
JPS60153160A (ja) * 1984-01-20 1985-08-12 Sanyo Electric Co Ltd 相補型絶縁ゲ−ト電界効果半導体装置の製造方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4735914A (en) * 1979-03-28 1988-04-05 Honeywell Inc. FET for high reverse bias voltage and geometrical design for low on resistance
US4306916A (en) * 1979-09-20 1981-12-22 American Microsystems, Inc. CMOS P-Well selective implant method
US4280271A (en) * 1979-10-11 1981-07-28 Texas Instruments Incorporated Three level interconnect process for manufacture of integrated circuit devices
JPS56134757A (en) 1980-03-26 1981-10-21 Nec Corp Complementary type mos semiconductor device and its manufacture
DE3133468A1 (de) * 1981-08-25 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen in siliziumgate-technologie
DE3133841A1 (de) * 1981-08-27 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4536223A (en) * 1984-03-29 1985-08-20 Rca Corporation Method of lowering contact resistance of implanted contact regions
US4553315A (en) * 1984-04-05 1985-11-19 Harris Corporation N Contact compensation technique
US4701423A (en) * 1985-12-20 1987-10-20 Ncr Corporation Totally self-aligned CMOS process
JPS6384067A (ja) * 1986-09-27 1988-04-14 Toshiba Corp 半導体装置の製造方法
US4764477A (en) * 1987-04-06 1988-08-16 Motorola, Inc. CMOS process flow with small gate geometry LDO N-channel transistors
US5169796A (en) * 1991-09-19 1992-12-08 Teledyne Industries, Inc. Process for fabricating self-aligned metal gate field effect transistors
WO2000039858A2 (en) 1998-12-28 2000-07-06 Fairchild Semiconductor Corporation Metal gate double diffusion mosfet with improved switching speed and reduced gate tunnel leakage
US7078296B2 (en) 2002-01-16 2006-07-18 Fairchild Semiconductor Corporation Self-aligned trench MOSFETs and methods for making the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5084185A (ja) * 1973-11-27 1975-07-07
JPS50106588A (ja) * 1974-01-29 1975-08-22

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3679492A (en) * 1970-03-23 1972-07-25 Ibm Process for making mosfet's
US3775191A (en) * 1971-06-28 1973-11-27 Bell Canada Northern Electric Modification of channel regions in insulated gate field effect transistors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5084185A (ja) * 1973-11-27 1975-07-07
JPS50106588A (ja) * 1974-01-29 1975-08-22

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5810856A (ja) * 1981-07-10 1983-01-21 Nec Corp 相補型半導体集積回路装置の製造方法
JPS60153160A (ja) * 1984-01-20 1985-08-12 Sanyo Electric Co Ltd 相補型絶縁ゲ−ト電界効果半導体装置の製造方法

Also Published As

Publication number Publication date
US4084311A (en) 1978-04-18

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