JPS53105174A - Adhering method of semiconductor substrate - Google Patents

Adhering method of semiconductor substrate

Info

Publication number
JPS53105174A
JPS53105174A JP1757177A JP1757177A JPS53105174A JP S53105174 A JPS53105174 A JP S53105174A JP 1757177 A JP1757177 A JP 1757177A JP 1757177 A JP1757177 A JP 1757177A JP S53105174 A JPS53105174 A JP S53105174A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
adhering method
substrate
adhering
small
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1757177A
Other languages
Japanese (ja)
Other versions
JPS575056B2 (en
Inventor
Hiroyuki Fujii
Kenichi Tateno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP1757177A priority Critical patent/JPS53105174A/en
Publication of JPS53105174A publication Critical patent/JPS53105174A/en
Publication of JPS575056B2 publication Critical patent/JPS575056B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE: To reduce the frequency in cracking of the substrate due to a heat cycle and to make the in-use amount of Au small, by forming the Ni plated layer containing a small amount of Au on the supporting board of the semiconductor substrate, by making its surface into a rough surface, and by adhering the substrate to its surface with the use of the brazing material of Au or Au alloy.
COPYRIGHT: (C)1978,JPO&Japio
JP1757177A 1977-02-18 1977-02-18 Adhering method of semiconductor substrate Granted JPS53105174A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1757177A JPS53105174A (en) 1977-02-18 1977-02-18 Adhering method of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1757177A JPS53105174A (en) 1977-02-18 1977-02-18 Adhering method of semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS53105174A true JPS53105174A (en) 1978-09-13
JPS575056B2 JPS575056B2 (en) 1982-01-28

Family

ID=11947590

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1757177A Granted JPS53105174A (en) 1977-02-18 1977-02-18 Adhering method of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS53105174A (en)

Also Published As

Publication number Publication date
JPS575056B2 (en) 1982-01-28

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