JPS5422162A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5422162A
JPS5422162A JP8665277A JP8665277A JPS5422162A JP S5422162 A JPS5422162 A JP S5422162A JP 8665277 A JP8665277 A JP 8665277A JP 8665277 A JP8665277 A JP 8665277A JP S5422162 A JPS5422162 A JP S5422162A
Authority
JP
Japan
Prior art keywords
manufacture
semiconductor device
streak
gold
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8665277A
Other languages
Japanese (ja)
Inventor
Hiroaki Shimizu
Tsukasa Hattori
Hiroyuki Baba
Osamu Usuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8665277A priority Critical patent/JPS5422162A/en
Publication of JPS5422162A publication Critical patent/JPS5422162A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/011—Apparatus therefor
    • H10W72/0113—Apparatus for manufacturing die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE: To eliminate virtually the change of the heat resistance by forming and supplying the streak substance of the gold-tin alloy solder onto the element installation base board to be pressure-bonded while being cut into a prescribed shape and then connecting the element.
COPYRIGHT: (C)1979,JPO&Japio
JP8665277A 1977-07-21 1977-07-21 Manufacture of semiconductor device Pending JPS5422162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8665277A JPS5422162A (en) 1977-07-21 1977-07-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8665277A JPS5422162A (en) 1977-07-21 1977-07-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5422162A true JPS5422162A (en) 1979-02-19

Family

ID=13892953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8665277A Pending JPS5422162A (en) 1977-07-21 1977-07-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5422162A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868943A (en) * 1981-10-20 1983-04-25 Mitsubishi Electric Corp Solder material supplier for die bonding
JPS5965532U (en) * 1982-10-23 1984-05-01 日本電気株式会社 Solder supply unit
US5029747A (en) * 1989-12-20 1991-07-09 Microelectronics And Computer Technology Corporation Apparatus for replacing defective electronic components
US5275970A (en) * 1990-10-17 1994-01-04 Nec Corporation Method of forming bonding bumps by punching a metal ribbon
US5516032A (en) * 1993-11-17 1996-05-14 Matsushita Electric Industrial Co., Ltd. Method for forming bump electrode
WO1999004423A1 (en) * 1997-07-14 1999-01-28 Infineon Technologies Ag Method and device for producing a chip-substrate assembly

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868943A (en) * 1981-10-20 1983-04-25 Mitsubishi Electric Corp Solder material supplier for die bonding
JPS5965532U (en) * 1982-10-23 1984-05-01 日本電気株式会社 Solder supply unit
US5029747A (en) * 1989-12-20 1991-07-09 Microelectronics And Computer Technology Corporation Apparatus for replacing defective electronic components
US5275970A (en) * 1990-10-17 1994-01-04 Nec Corporation Method of forming bonding bumps by punching a metal ribbon
US5516032A (en) * 1993-11-17 1996-05-14 Matsushita Electric Industrial Co., Ltd. Method for forming bump electrode
WO1999004423A1 (en) * 1997-07-14 1999-01-28 Infineon Technologies Ag Method and device for producing a chip-substrate assembly
GB2343551A (en) * 1997-07-14 2000-05-10 Infineon Technologies Ag Method and device for producing a chip-substrate assembly
GB2343551B (en) * 1997-07-14 2002-10-30 Infineon Technologies Ag Method and product for producing a chip-substrate connection
US7442582B2 (en) 1997-07-14 2008-10-28 Infineon Technologies Ag Method for producing a chip-substrate connection

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