JPS5373086A - Formation of multilayer wiring structure - Google Patents

Formation of multilayer wiring structure

Info

Publication number
JPS5373086A
JPS5373086A JP14909776A JP14909776A JPS5373086A JP S5373086 A JPS5373086 A JP S5373086A JP 14909776 A JP14909776 A JP 14909776A JP 14909776 A JP14909776 A JP 14909776A JP S5373086 A JPS5373086 A JP S5373086A
Authority
JP
Japan
Prior art keywords
formation
multilayer wiring
wiring structure
section
implanted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14909776A
Other languages
Japanese (ja)
Inventor
Masao Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14909776A priority Critical patent/JPS5373086A/en
Publication of JPS5373086A publication Critical patent/JPS5373086A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE: Impurity atoms are implanted into the wiring polycrystalline Si layer provided on a semiconductor substrate by using an ion-injecting method so that its surface impurity density will become higher than its inside, and a taper-shaped section is obtained by an etching method after heat treatment, thereby preventing the section cracking of the 2nd metal wiring layer.
COPYRIGHT: (C)1978,JPO&Japio
JP14909776A 1976-12-11 1976-12-11 Formation of multilayer wiring structure Pending JPS5373086A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14909776A JPS5373086A (en) 1976-12-11 1976-12-11 Formation of multilayer wiring structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14909776A JPS5373086A (en) 1976-12-11 1976-12-11 Formation of multilayer wiring structure

Publications (1)

Publication Number Publication Date
JPS5373086A true JPS5373086A (en) 1978-06-29

Family

ID=15467620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14909776A Pending JPS5373086A (en) 1976-12-11 1976-12-11 Formation of multilayer wiring structure

Country Status (1)

Country Link
JP (1) JPS5373086A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5561029A (en) * 1978-10-30 1980-05-08 Mitsubishi Electric Corp Method for etching of polycrystal silicon
US5316616A (en) * 1988-02-09 1994-05-31 Fujitsu Limited Dry etching with hydrogen bromide or bromine

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4880440A (en) * 1972-02-02 1973-10-27
JPS49118373A (en) * 1973-03-12 1974-11-12

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4880440A (en) * 1972-02-02 1973-10-27
JPS49118373A (en) * 1973-03-12 1974-11-12

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5561029A (en) * 1978-10-30 1980-05-08 Mitsubishi Electric Corp Method for etching of polycrystal silicon
US5316616A (en) * 1988-02-09 1994-05-31 Fujitsu Limited Dry etching with hydrogen bromide or bromine

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