JPS5460865A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5460865A
JPS5460865A JP12775477A JP12775477A JPS5460865A JP S5460865 A JPS5460865 A JP S5460865A JP 12775477 A JP12775477 A JP 12775477A JP 12775477 A JP12775477 A JP 12775477A JP S5460865 A JPS5460865 A JP S5460865A
Authority
JP
Japan
Prior art keywords
film
layer
sio
type
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12775477A
Other languages
Japanese (ja)
Other versions
JPS6028396B2 (en
Inventor
Minoru Matsumoto
Sadaichi Inaba
Kyoichi Ishii
Mikio Takagi
Tetsushi Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NTT Inc
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP52127754A priority Critical patent/JPS6028396B2/en
Publication of JPS5460865A publication Critical patent/JPS5460865A/en
Publication of JPS6028396B2 publication Critical patent/JPS6028396B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To enhance the frequency characteristics as well as to increase the degree of integration with high output and low noise by forming the convex base layeron the collector region, providing the emitter region within the base layer and then turning these active regions into a cubic structure.
CONSTITUTION: Si3N4 film 42 and SiO2 film 43 are coated on N-type Si substrate 41 to become the collector with removal of film 43 at the edge part, and then the oxidation is given to form thick SiO2 film 44 buried within substrate 41. Then film 42 is removed to form p-type base layer 45 through diffusion onto the substrate surface, and at the same time SiO2 film 46 connecting to film 44 is caused with Si3N4 film 47 and SiO2 film 48 coated on the entire surface. After this, opening 49 is drilled to these lamination film reaching layer 45, and N-type polycrystal Si layer 50 and SiO2 film 51 are grown on the entire surface including opening 49. Using resist film pattern 52, an etching is given to form independent layer 50 on layer 45. And pattern 52 is removed to provide P-type base contact region 53 between layer 50 and pattern 52, and at the same time the impurity is diffused into layer 50 to form N-type emitter region 54 within layer 45
COPYRIGHT: (C)1979,JPO&Japio
JP52127754A 1977-10-24 1977-10-24 Manufacturing method of semiconductor device Expired JPS6028396B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52127754A JPS6028396B2 (en) 1977-10-24 1977-10-24 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52127754A JPS6028396B2 (en) 1977-10-24 1977-10-24 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5460865A true JPS5460865A (en) 1979-05-16
JPS6028396B2 JPS6028396B2 (en) 1985-07-04

Family

ID=14967851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52127754A Expired JPS6028396B2 (en) 1977-10-24 1977-10-24 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6028396B2 (en)

Also Published As

Publication number Publication date
JPS6028396B2 (en) 1985-07-04

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