JPS5469089A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5469089A
JPS5469089A JP13608077A JP13608077A JPS5469089A JP S5469089 A JPS5469089 A JP S5469089A JP 13608077 A JP13608077 A JP 13608077A JP 13608077 A JP13608077 A JP 13608077A JP S5469089 A JPS5469089 A JP S5469089A
Authority
JP
Japan
Prior art keywords
region
layer
film
type
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13608077A
Other languages
Japanese (ja)
Inventor
Tadashi Hirao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13608077A priority Critical patent/JPS5469089A/en
Publication of JPS5469089A publication Critical patent/JPS5469089A/en
Pending legal-status Critical Current

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Landscapes

  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To reduce the occupied area of the device which combines the transistor and the resistance together, by separating the epitaxial layer grown on the semiconductor substrate and then using one region as the active region of the transistor and the other region as the resistance respectively.
CONSTITUTION: N+-type collector buried region 2 is formed through diffusion on P-type si substrate 1, and N-type epitaxial layer 3 is grown on the entire surfce. And the mask comprising SiO2 film 4' and Si3N4 film 4 is formed selectively on layer 3. Surface part 5a, 5b and 5c exposed on layer 3 are etched selectively to form the groove within layer 3, and the groove is then filled with deep oxide film 6a, 6b and 6c. After this, the mask is removed, and P-type base region 8 and collector electrode draw-out mouth 9b are formed thrugh diffusion within layer 3a at the transistor forming region enclosed by film 6b and 6c, with P-type emitter region 9a provided within region 8. at the same time, resistance electrode draw-out mouth 9c is formed through diffusion within layer 3b surrounded by film 6a and 6b and to be the resistance region with attachment of the electrode each.
COPYRIGHT: (C)1979,JPO&Japio
JP13608077A 1977-11-11 1977-11-11 Semiconductor device Pending JPS5469089A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13608077A JPS5469089A (en) 1977-11-11 1977-11-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13608077A JPS5469089A (en) 1977-11-11 1977-11-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5469089A true JPS5469089A (en) 1979-06-02

Family

ID=15166765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13608077A Pending JPS5469089A (en) 1977-11-11 1977-11-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5469089A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6639300B2 (en) 2000-03-24 2003-10-28 Fujitsu Quantum Devices Limited Semiconductor integrated circuit having an integrated resistance region

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6639300B2 (en) 2000-03-24 2003-10-28 Fujitsu Quantum Devices Limited Semiconductor integrated circuit having an integrated resistance region

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