JPS64475A - Test circuit - Google Patents

Test circuit

Info

Publication number
JPS64475A
JPS64475A JP62155989A JP15598987A JPS64475A JP S64475 A JPS64475 A JP S64475A JP 62155989 A JP62155989 A JP 62155989A JP 15598987 A JP15598987 A JP 15598987A JP S64475 A JPS64475 A JP S64475A
Authority
JP
Japan
Prior art keywords
outputted
circuit
article
data
defectiveness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62155989A
Other languages
Japanese (ja)
Other versions
JPH01475A (en
Inventor
Yuichi Suzuki
Takehiro Akiyama
Shinji Saito
Kazuyuki Nonaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP62155989A priority Critical patent/JPS64475A/en
Publication of JPH01475A publication Critical patent/JPH01475A/en
Publication of JPS64475A publication Critical patent/JPS64475A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To enable testing with high reliability by comparing the output signals of an article to be measured and standard sample, applying a negative feedback when there is a phase difference between the signals and deciding non- defectiveness and defectiveness from coincidence and dissidence.
CONSTITUTION: A clock signal of fin/n frequency is outputted from a frequency dividing circuit 6 via a latch circuit 12 when the number of the output pulses of a serial counter 11 is (n). Data A, B are outputted from the standard sample 4 and the article 5 to be measured. Data QA, QB are outputted from FF circuits 7, 8. The phase difference thereof is outputted as a pulse in an E-NOR circuit 9. After the pulses are counted at a specified number of pulses in the counter 11, one pulse is sent to the circuit 12. The clock signal of fin/n+1 is outputted in the circuit 6. The data QA(n+1), QB(n+1) are obtd. from the circuits 7, 9 of this time and an 'H' level signal is outputted from the circuit 9. A non- defectiveness decision signal is outputted from a detecting circuit 10. The synchronization of the sample 4 and the output data of the article 5 to be measured is not obtainable if the article 5 is defective. The article 5 is then decided to be defective.
COPYRIGHT: (C)1989,JPO&Japio
JP62155989A 1987-06-23 1987-06-23 Test circuit Pending JPS64475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62155989A JPS64475A (en) 1987-06-23 1987-06-23 Test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62155989A JPS64475A (en) 1987-06-23 1987-06-23 Test circuit

Publications (2)

Publication Number Publication Date
JPH01475A JPH01475A (en) 1989-01-05
JPS64475A true JPS64475A (en) 1989-01-05

Family

ID=15617918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62155989A Pending JPS64475A (en) 1987-06-23 1987-06-23 Test circuit

Country Status (1)

Country Link
JP (1) JPS64475A (en)

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