JPS5484981A - Production of mos-type semiconductor device - Google Patents

Production of mos-type semiconductor device

Info

Publication number
JPS5484981A
JPS5484981A JP15324777A JP15324777A JPS5484981A JP S5484981 A JPS5484981 A JP S5484981A JP 15324777 A JP15324777 A JP 15324777A JP 15324777 A JP15324777 A JP 15324777A JP S5484981 A JPS5484981 A JP S5484981A
Authority
JP
Japan
Prior art keywords
film
sio2
mask
generated
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15324777A
Other languages
Japanese (ja)
Inventor
Katsuyuki Inayoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15324777A priority Critical patent/JPS5484981A/en
Publication of JPS5484981A publication Critical patent/JPS5484981A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent wiring disconnection by forming SiO2 by the selective oxidation method while using Si3N4 as a mask and making the SiO2 film side face around electrode windows into a gentle inclination. CONSTITUTION:Required N<+>-type and P<+>-type layers are selectively formed on N-type Si substrate 1 by a SiO2 mask, and after that, the mask is removed to generate SiO2 film 9. CVD Si3N4 is provided on film 9 and is opened selectively to generate mask 10. Next, SiO2 11 is generated to warp upward the part around mask 10 by oxidation at approximately 1000 deg.C. Next, film 10 and film 9 under film 9 are removed to expose substrate 1, and SiO2 12 and 13 are generated on the exposed surface by oxiding thermally again. Film 13 is after used as a gate film. After that, after the processing in N2 at approximately 1000 deg.C, film 12 is provided with electrode windows to evaporate Al, and gate electrodes 14 and 15 and source drain wirings 16 to 18 are generated and are covered with PSG 19. In this method, oxide film surface step difference is reduced to decrease disconnection troubles considerably.
JP15324777A 1977-12-20 1977-12-20 Production of mos-type semiconductor device Pending JPS5484981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15324777A JPS5484981A (en) 1977-12-20 1977-12-20 Production of mos-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15324777A JPS5484981A (en) 1977-12-20 1977-12-20 Production of mos-type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5484981A true JPS5484981A (en) 1979-07-06

Family

ID=15558270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15324777A Pending JPS5484981A (en) 1977-12-20 1977-12-20 Production of mos-type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5484981A (en)

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