JPS5522878A - Insulation gate type field effect semiconductor device - Google Patents

Insulation gate type field effect semiconductor device

Info

Publication number
JPS5522878A
JPS5522878A JP10576078A JP10576078A JPS5522878A JP S5522878 A JPS5522878 A JP S5522878A JP 10576078 A JP10576078 A JP 10576078A JP 10576078 A JP10576078 A JP 10576078A JP S5522878 A JPS5522878 A JP S5522878A
Authority
JP
Japan
Prior art keywords
layer
electrode
sio
covered
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10576078A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP10576078A priority Critical patent/JPS5522878A/en
Publication of JPS5522878A publication Critical patent/JPS5522878A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To obtain a MISFET by drawing out a lead of an n+ Si layer from an n- type diffusion layer onto a field insulation layer and further forming an electrode or lead of a p+ Si layer through an insulation film.
CONSTITUTION: A field oxidization fiom 2 is buried in a p-type Si substrate to form an n+epi layer 3 and covered with Pt and others. The layer 3 is etched to selectively form an electrode or leads 4 and 5 on layer 2. Next, SiO26, Si3N37 and SiO28 are put one after another to prevent a charge transfer between a gate film 6 and film 7. Further, a p+epi layer 9 is laminated and is covered with a Mo 10. Next, a gate electrode 15 and capacity 19 are selectively formed by an etching, and n+ layers 13 and 14 are formed by a thermal diffusion from an opening. Successively, SiO216 is covered and an opening is selectively formed and an Al electrode 18 is attached. According to such a process, the lead is introduced onto a buried separation layer from a source and drain by the Si layer having the same conduction mode, the Al layer is provided thereon and an IC circuit having a high density can be formed.
COPYRIGHT: (C)1980,JPO&Japio
JP10576078A 1978-08-30 1978-08-30 Insulation gate type field effect semiconductor device Pending JPS5522878A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10576078A JPS5522878A (en) 1978-08-30 1978-08-30 Insulation gate type field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10576078A JPS5522878A (en) 1978-08-30 1978-08-30 Insulation gate type field effect semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3062571A Division JPS5624385B1 (en) 1971-05-07 1971-05-07

Publications (1)

Publication Number Publication Date
JPS5522878A true JPS5522878A (en) 1980-02-18

Family

ID=14416163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10576078A Pending JPS5522878A (en) 1978-08-30 1978-08-30 Insulation gate type field effect semiconductor device

Country Status (1)

Country Link
JP (1) JPS5522878A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849366A (en) * 1988-01-15 1989-07-18 Industrial Technology Research Institute Method of making a gated isolated structure
US5328861A (en) * 1991-11-25 1994-07-12 Casio Computer Co., Ltd. Method for forming thin film transistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3475234A (en) * 1967-03-27 1969-10-28 Bell Telephone Labor Inc Method for making mis structures

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3475234A (en) * 1967-03-27 1969-10-28 Bell Telephone Labor Inc Method for making mis structures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849366A (en) * 1988-01-15 1989-07-18 Industrial Technology Research Institute Method of making a gated isolated structure
US5328861A (en) * 1991-11-25 1994-07-12 Casio Computer Co., Ltd. Method for forming thin film transistor

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