JPS55111165A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS55111165A
JPS55111165A JP1883679A JP1883679A JPS55111165A JP S55111165 A JPS55111165 A JP S55111165A JP 1883679 A JP1883679 A JP 1883679A JP 1883679 A JP1883679 A JP 1883679A JP S55111165 A JPS55111165 A JP S55111165A
Authority
JP
Japan
Prior art keywords
substrate
main face
brazing material
polycrystalline silicon
flowing out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1883679A
Other languages
Japanese (ja)
Inventor
Koji Kawanami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1883679A priority Critical patent/JPS55111165A/en
Publication of JPS55111165A publication Critical patent/JPS55111165A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Abstract

PURPOSE: To prevent a brazing material from flowing out to a side face and raise reliability, by providing polycrystalline silicon on the peripheral part of one main face of a planar semiconductor.
CONSTITUTION: A planar pn junction 11 is produced on one main face of an n-type silicon substrate. An n+-type region 12 is provided on the other main face of the substrate. A polycrystalline silicon film is coated by monosilane pyrolysis or the like all over the former main face of the substrate and chemically etched into an annular shape 13. The pellet-divided substrate 14 is secured on an electrode 15 by a brazing material 16 such as Ag-Pb-Sn solder and sealed up by resin 17. As a result, the brazing material is prevented by the polycrystalline silicon layer 13 from flowing out, deterioration of electric properties due to short circuit or the like is eliminated and reliability is heightened.
COPYRIGHT: (C)1980,JPO&Japio
JP1883679A 1979-02-20 1979-02-20 Semiconductor device Pending JPS55111165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1883679A JPS55111165A (en) 1979-02-20 1979-02-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1883679A JPS55111165A (en) 1979-02-20 1979-02-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS55111165A true JPS55111165A (en) 1980-08-27

Family

ID=11982640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1883679A Pending JPS55111165A (en) 1979-02-20 1979-02-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55111165A (en)

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