JPS55145352A - Fabricating method of semiconductor chip - Google Patents

Fabricating method of semiconductor chip

Info

Publication number
JPS55145352A
JPS55145352A JP5237779A JP5237779A JPS55145352A JP S55145352 A JPS55145352 A JP S55145352A JP 5237779 A JP5237779 A JP 5237779A JP 5237779 A JP5237779 A JP 5237779A JP S55145352 A JPS55145352 A JP S55145352A
Authority
JP
Japan
Prior art keywords
chips
recesses
wax
semiconductor chip
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5237779A
Other languages
Japanese (ja)
Inventor
Kanichi Tateishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP5237779A priority Critical patent/JPS55145352A/en
Publication of JPS55145352A publication Critical patent/JPS55145352A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices

Landscapes

  • Weting (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To fully automate the fabrication of a diode chip or the like by containing and conveying divided semiconductor chips while regularly aligning the chips to eliminate the necessity of checking or realigning the aligned chips by a manual work. CONSTITUTION:A semiconductor wafer 2 is adhered via wax 3 on a supporting plate 1, and divided into independent chips 2a-2e. Then, the recesses 4a-4c of a transparent retainer tool 4 having holes at the bottom as formed responsive to the chips 2a-2e are so brought oppositely into contact at the recesses 4a-4c with the chips 2a-2e, respectively. Thereafter, the wax 3 is molten and removed in this contacted state to accommodate the respective chips in the recesses for holding the separated chips.
JP5237779A 1979-04-27 1979-04-27 Fabricating method of semiconductor chip Pending JPS55145352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5237779A JPS55145352A (en) 1979-04-27 1979-04-27 Fabricating method of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5237779A JPS55145352A (en) 1979-04-27 1979-04-27 Fabricating method of semiconductor chip

Publications (1)

Publication Number Publication Date
JPS55145352A true JPS55145352A (en) 1980-11-12

Family

ID=12913106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5237779A Pending JPS55145352A (en) 1979-04-27 1979-04-27 Fabricating method of semiconductor chip

Country Status (1)

Country Link
JP (1) JPS55145352A (en)

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