JPS551627A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS551627A
JPS551627A JP7411278A JP7411278A JPS551627A JP S551627 A JPS551627 A JP S551627A JP 7411278 A JP7411278 A JP 7411278A JP 7411278 A JP7411278 A JP 7411278A JP S551627 A JPS551627 A JP S551627A
Authority
JP
Japan
Prior art keywords
channel
drain
transistor
point
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7411278A
Other languages
Japanese (ja)
Inventor
Tetsuya Iizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7411278A priority Critical patent/JPS551627A/en
Publication of JPS551627A publication Critical patent/JPS551627A/en
Priority to US06/254,117 priority patent/US4384300A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211Design considerations for internal polarisation
    • H10D89/213Design considerations for internal polarisation in field-effect devices
    • H10D89/215Design considerations for internal polarisation in field-effect devices comprising arrangements for charge pumping or biasing substrates

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To reduce the power consumption of a semiconductor memory by a constitution where sources of N-channel and P-channel MOS transistors are connected to each other and gates of them are connected to each other and the drain of one of them is connected to the other substrate. CONSTITUTION:Shallow D-type N-channel and P-channel MOS transistors Q1 and Q2 have sources and gates connected to each other respectively, and the drain of the N-channel transistor and the substrate of the P-channel transistor are connected, and the drain of the P-channel transistor and the substrate of the N-channel transistor are connected, and the drain of transistor Q1 and the drain of transistor Q2 are connected to input point K and output point A respectively, and point A is grounded. Transistors Q1 and Q2 have a conductive state in case of a low potential at input point K, and transistors Q1 and Q2 have a non-conductive state in case of a high potential at point K. Then, by using these facts, a memory device having two operation stable points can be constituted.
JP7411278A 1978-06-21 1978-06-21 Semiconductor memory device Pending JPS551627A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP7411278A JPS551627A (en) 1978-06-21 1978-06-21 Semiconductor memory device
US06/254,117 US4384300A (en) 1978-06-21 1981-04-14 Negative resistance device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7411278A JPS551627A (en) 1978-06-21 1978-06-21 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS551627A true JPS551627A (en) 1980-01-08

Family

ID=13537782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7411278A Pending JPS551627A (en) 1978-06-21 1978-06-21 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS551627A (en)

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